add lvds1024*800

hc

2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920

 kernel/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
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@@ -42,6 +42,9 @@
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 	u8 tx_dctrl[] = { 0x00, 0x00, 0x00, 0x04, 0x01 };
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 	void __iomem *lane_base = phy->lane_base;
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+	if (phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK)
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+		tx_dctrl[3] = 0x02;
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+
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 	/* Strength ctrl settings */
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 	for (i = 0; i < 5; i++) {
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 		dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(i),
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@@ -74,9 +77,11 @@
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 			      tx_dctrl[i]);
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 	}
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-	/* Toggle BIT 0 to release freeze I/0 */
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-	dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x05);
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-	dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04);
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+	if (!(phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK)) {
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+		/* Toggle BIT 0 to release freeze I/0 */
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+		dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x05);
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+		dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04);
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+	}
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 }
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 static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
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@@ -93,7 +98,7 @@
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 	DBG("");
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 	if (msm_dsi_dphy_timing_calc_v3(timing, clk_req)) {
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-		dev_err(&phy->pdev->dev,
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+		DRM_DEV_ERROR(&phy->pdev->dev,
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 			"%s: D-PHY timing calculation failed\n", __func__);
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 		return -EINVAL;
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 	}
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@@ -172,7 +177,7 @@
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 	ret = msm_dsi_pll_set_usecase(phy->pll, phy->usecase);
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 	if (ret) {
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-		dev_err(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
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+		DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
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 			__func__, ret);
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 		return ret;
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 	}
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@@ -196,7 +201,7 @@
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 	phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane",
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 				     "DSI_PHY_LANE");
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 	if (IS_ERR(phy->lane_base)) {
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-		dev_err(&pdev->dev, "%s: failed to map phy lane base\n",
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+		DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n",
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 			__func__);
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 		return -ENOMEM;
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 	}
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@@ -221,3 +226,22 @@
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 	.io_start = { 0xae94400, 0xae96400 },
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 	.num_dsi_phy = 2,
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 };
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+
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+const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
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+	.type = MSM_DSI_PHY_10NM,
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+	.src_pll_truthtable = { {false, false}, {true, false} },
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+	.reg_cfg = {
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+		.num = 1,
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+		.regs = {
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+			{"vdds", 36000, 32},
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+		},
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+	},
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+	.ops = {
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+		.enable = dsi_10nm_phy_enable,
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+		.disable = dsi_10nm_phy_disable,
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+		.init = dsi_10nm_phy_init,
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+	},
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+	.io_start = { 0xc994400, 0xc996400 },
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+	.num_dsi_phy = 2,
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+	.quirks = V3_0_0_10NM_OLD_TIMINGS_QUIRK,
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+};