add lvds1024*800

hc

2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920

 kernel/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
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@@ -1,14 +1,6 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #ifndef __DSI_PHY_H__
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@@ -20,6 +12,9 @@
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 #define dsi_phy_read(offset) msm_readl((offset))
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 #define dsi_phy_write(offset, data) msm_writel((data), (offset))
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+
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+/* v3.0.0 10nm implementation that requires the old timings settings */
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+#define V3_0_0_10NM_OLD_TIMINGS_QUIRK	BIT(0)
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 struct msm_dsi_phy_ops {
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 	int (*init) (struct msm_dsi_phy *phy);
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@@ -41,18 +36,22 @@
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 	bool src_pll_truthtable[DSI_MAX][DSI_MAX];
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 	const resource_size_t io_start[DSI_MAX];
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 	const int num_dsi_phy;
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+	const int quirks;
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 };
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 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
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+extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
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 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
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 extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
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 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
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 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
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+extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
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 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
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+extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
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+extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
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+extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
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 struct msm_dsi_dphy_timing {
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-	u32 clk_pre;
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-	u32 clk_post;
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 	u32 clk_zero;
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 	u32 clk_trail;
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 	u32 clk_prepare;
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@@ -103,6 +102,8 @@
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 				struct msm_dsi_phy_clk_request *clk_req);
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 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
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 				struct msm_dsi_phy_clk_request *clk_req);
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+int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
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+				struct msm_dsi_phy_clk_request *clk_req);
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 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
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 				u32 bit_mask);
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 int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);