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2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920 
 kernel/drivers/gpu/drm/msm/adreno/a5xx.xml.h
....@@ -8,19 +8,21 @@
88 git clone https://github.com/freedreno/envytools.git
99 
1010 The rules-ng-ng source files this header was generated from are:
11
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
12
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
13
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  36805 bytes, from 2018-07-03 19:37:13)
14
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  13634 bytes, from 2018-07-03 19:37:13)
15
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  42393 bytes, from 2018-08-06 18:45:45)
16
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
17
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
18
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-08-06 18:45:45)
19
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 101627 bytes, from 2018-08-06 18:45:45)
20
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-07-03 19:37:13)
21
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
11
+- /home/robclark/src/envytools/rnndb/adreno.xml                     (    594 bytes, from 2020-07-23 21:58:14)
12
+- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml        (   1572 bytes, from 2020-07-23 21:58:14)
13
+- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml                (  90159 bytes, from 2020-07-23 21:58:14)
14
+- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml       (  14386 bytes, from 2020-07-23 21:58:14)
15
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml          (  65048 bytes, from 2020-07-23 21:58:14)
16
+- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml                (  84226 bytes, from 2020-07-23 21:58:14)
17
+- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml                ( 112556 bytes, from 2020-07-23 21:58:14)
18
+- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml                ( 149461 bytes, from 2020-07-23 21:58:14)
19
+- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml                ( 184695 bytes, from 2020-07-23 21:58:14)
20
+- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml            (  11218 bytes, from 2020-07-23 21:58:14)
21
+- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml               (   1773 bytes, from 2020-07-23 21:58:14)
22
+- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml (   4559 bytes, from 2020-07-23 21:58:14)
23
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml    (   2872 bytes, from 2020-07-23 21:58:14)
2224 
23
-Copyright (C) 2013-2018 by the following authors:
25
+Copyright (C) 2013-2020 by the following authors:
2426 - Rob Clark <robdclark@gmail.com> (robclark)
2527 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2628 
....@@ -91,6 +93,7 @@
9193 	RB5_R32G32B32A32_FLOAT = 130,
9294 	RB5_R32G32B32A32_UINT = 131,
9395 	RB5_R32G32B32A32_SINT = 132,
96
+	RB5_NONE = 255,
9497 };
9598 
9699 enum a5xx_tile_mode {
....@@ -165,6 +168,7 @@
165168 	VFMT5_32_32_32_32_UINT = 131,
166169 	VFMT5_32_32_32_32_SINT = 132,
167170 	VFMT5_32_32_32_32_FIXED = 133,
171
+	VFMT5_NONE = 255,
168172 };
169173 
170174 enum a5xx_tex_fmt {
....@@ -250,14 +254,7 @@
250254 	TFMT5_ASTC_10x10 = 204,
251255 	TFMT5_ASTC_12x10 = 205,
252256 	TFMT5_ASTC_12x12 = 206,
253
-};
254
-
255
-enum a5xx_tex_fetchsize {
256
-	TFETCH5_1_BYTE = 0,
257
-	TFETCH5_2_BYTE = 1,
258
-	TFETCH5_4_BYTE = 2,
259
-	TFETCH5_8_BYTE = 3,
260
-	TFETCH5_16_BYTE = 4,
257
+	TFMT5_NONE = 255,
261258 };
262259 
263260 enum a5xx_depth_format {
....@@ -1052,8 +1049,18 @@
10521049 {
10531050 	return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK;
10541051 }
1055
-#define A5XX_CP_PROTECT_REG_TRAP_WRITE				0x20000000
1056
-#define A5XX_CP_PROTECT_REG_TRAP_READ				0x40000000
1052
+#define A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK			0x20000000
1053
+#define A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT			29
1054
+static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val)
1055
+{
1056
+	return ((val) << A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK;
1057
+}
1058
+#define A5XX_CP_PROTECT_REG_TRAP_READ__MASK			0x40000000
1059
+#define A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT			30
1060
+static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val)
1061
+{
1062
+	return ((val) << A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_READ__MASK;
1063
+}
10571064 
10581065 #define REG_A5XX_CP_PROTECT_CNTL				0x000008a0
10591066 
....@@ -1825,37 +1832,192 @@
18251832 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI			0x000004d3
18261833 
18271834 #define REG_A5XX_RBBM_STATUS					0x000004f5
1828
-#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB			0x80000000
1829
-#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP			0x40000000
1830
-#define A5XX_RBBM_STATUS_HLSQ_BUSY				0x20000000
1831
-#define A5XX_RBBM_STATUS_VSC_BUSY				0x10000000
1832
-#define A5XX_RBBM_STATUS_TPL1_BUSY				0x08000000
1833
-#define A5XX_RBBM_STATUS_SP_BUSY				0x04000000
1834
-#define A5XX_RBBM_STATUS_UCHE_BUSY				0x02000000
1835
-#define A5XX_RBBM_STATUS_VPC_BUSY				0x01000000
1836
-#define A5XX_RBBM_STATUS_VFDP_BUSY				0x00800000
1837
-#define A5XX_RBBM_STATUS_VFD_BUSY				0x00400000
1838
-#define A5XX_RBBM_STATUS_TESS_BUSY				0x00200000
1839
-#define A5XX_RBBM_STATUS_PC_VSD_BUSY				0x00100000
1840
-#define A5XX_RBBM_STATUS_PC_DCALL_BUSY				0x00080000
1841
-#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY			0x00040000
1842
-#define A5XX_RBBM_STATUS_DCOM_BUSY				0x00020000
1843
-#define A5XX_RBBM_STATUS_COM_BUSY				0x00010000
1844
-#define A5XX_RBBM_STATUS_LRZ_BUZY				0x00008000
1845
-#define A5XX_RBBM_STATUS_A2D_DSP_BUSY				0x00004000
1846
-#define A5XX_RBBM_STATUS_CCUFCHE_BUSY				0x00002000
1847
-#define A5XX_RBBM_STATUS_RB_BUSY				0x00001000
1848
-#define A5XX_RBBM_STATUS_RAS_BUSY				0x00000800
1849
-#define A5XX_RBBM_STATUS_TSE_BUSY				0x00000400
1850
-#define A5XX_RBBM_STATUS_VBIF_BUSY				0x00000200
1851
-#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST			0x00000100
1852
-#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST			0x00000080
1853
-#define A5XX_RBBM_STATUS_CP_BUSY				0x00000040
1854
-#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY			0x00000020
1855
-#define A5XX_RBBM_STATUS_CP_CRASH_BUSY				0x00000010
1856
-#define A5XX_RBBM_STATUS_CP_ETS_BUSY				0x00000008
1857
-#define A5XX_RBBM_STATUS_CP_PFP_BUSY				0x00000004
1858
-#define A5XX_RBBM_STATUS_CP_ME_BUSY				0x00000002
1835
+#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK			0x80000000
1836
+#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT		31
1837
+static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val)
1838
+{
1839
+	return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK;
1840
+}
1841
+#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK		0x40000000
1842
+#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT		30
1843
+static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP(uint32_t val)
1844
+{
1845
+	return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK;
1846
+}
1847
+#define A5XX_RBBM_STATUS_HLSQ_BUSY__MASK			0x20000000
1848
+#define A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT			29
1849
+static inline uint32_t A5XX_RBBM_STATUS_HLSQ_BUSY(uint32_t val)
1850
+{
1851
+	return ((val) << A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT) & A5XX_RBBM_STATUS_HLSQ_BUSY__MASK;
1852
+}
1853
+#define A5XX_RBBM_STATUS_VSC_BUSY__MASK				0x10000000
1854
+#define A5XX_RBBM_STATUS_VSC_BUSY__SHIFT			28
1855
+static inline uint32_t A5XX_RBBM_STATUS_VSC_BUSY(uint32_t val)
1856
+{
1857
+	return ((val) << A5XX_RBBM_STATUS_VSC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VSC_BUSY__MASK;
1858
+}
1859
+#define A5XX_RBBM_STATUS_TPL1_BUSY__MASK			0x08000000
1860
+#define A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT			27
1861
+static inline uint32_t A5XX_RBBM_STATUS_TPL1_BUSY(uint32_t val)
1862
+{
1863
+	return ((val) << A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT) & A5XX_RBBM_STATUS_TPL1_BUSY__MASK;
1864
+}
1865
+#define A5XX_RBBM_STATUS_SP_BUSY__MASK				0x04000000
1866
+#define A5XX_RBBM_STATUS_SP_BUSY__SHIFT				26
1867
+static inline uint32_t A5XX_RBBM_STATUS_SP_BUSY(uint32_t val)
1868
+{
1869
+	return ((val) << A5XX_RBBM_STATUS_SP_BUSY__SHIFT) & A5XX_RBBM_STATUS_SP_BUSY__MASK;
1870
+}
1871
+#define A5XX_RBBM_STATUS_UCHE_BUSY__MASK			0x02000000
1872
+#define A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT			25
1873
+static inline uint32_t A5XX_RBBM_STATUS_UCHE_BUSY(uint32_t val)
1874
+{
1875
+	return ((val) << A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_UCHE_BUSY__MASK;
1876
+}
1877
+#define A5XX_RBBM_STATUS_VPC_BUSY__MASK				0x01000000
1878
+#define A5XX_RBBM_STATUS_VPC_BUSY__SHIFT			24
1879
+static inline uint32_t A5XX_RBBM_STATUS_VPC_BUSY(uint32_t val)
1880
+{
1881
+	return ((val) << A5XX_RBBM_STATUS_VPC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VPC_BUSY__MASK;
1882
+}
1883
+#define A5XX_RBBM_STATUS_VFDP_BUSY__MASK			0x00800000
1884
+#define A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT			23
1885
+static inline uint32_t A5XX_RBBM_STATUS_VFDP_BUSY(uint32_t val)
1886
+{
1887
+	return ((val) << A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFDP_BUSY__MASK;
1888
+}
1889
+#define A5XX_RBBM_STATUS_VFD_BUSY__MASK				0x00400000
1890
+#define A5XX_RBBM_STATUS_VFD_BUSY__SHIFT			22
1891
+static inline uint32_t A5XX_RBBM_STATUS_VFD_BUSY(uint32_t val)
1892
+{
1893
+	return ((val) << A5XX_RBBM_STATUS_VFD_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFD_BUSY__MASK;
1894
+}
1895
+#define A5XX_RBBM_STATUS_TESS_BUSY__MASK			0x00200000
1896
+#define A5XX_RBBM_STATUS_TESS_BUSY__SHIFT			21
1897
+static inline uint32_t A5XX_RBBM_STATUS_TESS_BUSY(uint32_t val)
1898
+{
1899
+	return ((val) << A5XX_RBBM_STATUS_TESS_BUSY__SHIFT) & A5XX_RBBM_STATUS_TESS_BUSY__MASK;
1900
+}
1901
+#define A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK			0x00100000
1902
+#define A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT			20
1903
+static inline uint32_t A5XX_RBBM_STATUS_PC_VSD_BUSY(uint32_t val)
1904
+{
1905
+	return ((val) << A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK;
1906
+}
1907
+#define A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK			0x00080000
1908
+#define A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT			19
1909
+static inline uint32_t A5XX_RBBM_STATUS_PC_DCALL_BUSY(uint32_t val)
1910
+{
1911
+	return ((val) << A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK;
1912
+}
1913
+#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK			0x00040000
1914
+#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT			18
1915
+static inline uint32_t A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY(uint32_t val)
1916
+{
1917
+	return ((val) << A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK;
1918
+}
1919
+#define A5XX_RBBM_STATUS_DCOM_BUSY__MASK			0x00020000
1920
+#define A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT			17
1921
+static inline uint32_t A5XX_RBBM_STATUS_DCOM_BUSY(uint32_t val)
1922
+{
1923
+	return ((val) << A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT) & A5XX_RBBM_STATUS_DCOM_BUSY__MASK;
1924
+}
1925
+#define A5XX_RBBM_STATUS_COM_BUSY__MASK				0x00010000
1926
+#define A5XX_RBBM_STATUS_COM_BUSY__SHIFT			16
1927
+static inline uint32_t A5XX_RBBM_STATUS_COM_BUSY(uint32_t val)
1928
+{
1929
+	return ((val) << A5XX_RBBM_STATUS_COM_BUSY__SHIFT) & A5XX_RBBM_STATUS_COM_BUSY__MASK;
1930
+}
1931
+#define A5XX_RBBM_STATUS_LRZ_BUZY__MASK				0x00008000
1932
+#define A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT			15
1933
+static inline uint32_t A5XX_RBBM_STATUS_LRZ_BUZY(uint32_t val)
1934
+{
1935
+	return ((val) << A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT) & A5XX_RBBM_STATUS_LRZ_BUZY__MASK;
1936
+}
1937
+#define A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK			0x00004000
1938
+#define A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT			14
1939
+static inline uint32_t A5XX_RBBM_STATUS_A2D_DSP_BUSY(uint32_t val)
1940
+{
1941
+	return ((val) << A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT) & A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK;
1942
+}
1943
+#define A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK			0x00002000
1944
+#define A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT			13
1945
+static inline uint32_t A5XX_RBBM_STATUS_CCUFCHE_BUSY(uint32_t val)
1946
+{
1947
+	return ((val) << A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK;
1948
+}
1949
+#define A5XX_RBBM_STATUS_RB_BUSY__MASK				0x00001000
1950
+#define A5XX_RBBM_STATUS_RB_BUSY__SHIFT				12
1951
+static inline uint32_t A5XX_RBBM_STATUS_RB_BUSY(uint32_t val)
1952
+{
1953
+	return ((val) << A5XX_RBBM_STATUS_RB_BUSY__SHIFT) & A5XX_RBBM_STATUS_RB_BUSY__MASK;
1954
+}
1955
+#define A5XX_RBBM_STATUS_RAS_BUSY__MASK				0x00000800
1956
+#define A5XX_RBBM_STATUS_RAS_BUSY__SHIFT			11
1957
+static inline uint32_t A5XX_RBBM_STATUS_RAS_BUSY(uint32_t val)
1958
+{
1959
+	return ((val) << A5XX_RBBM_STATUS_RAS_BUSY__SHIFT) & A5XX_RBBM_STATUS_RAS_BUSY__MASK;
1960
+}
1961
+#define A5XX_RBBM_STATUS_TSE_BUSY__MASK				0x00000400
1962
+#define A5XX_RBBM_STATUS_TSE_BUSY__SHIFT			10
1963
+static inline uint32_t A5XX_RBBM_STATUS_TSE_BUSY(uint32_t val)
1964
+{
1965
+	return ((val) << A5XX_RBBM_STATUS_TSE_BUSY__SHIFT) & A5XX_RBBM_STATUS_TSE_BUSY__MASK;
1966
+}
1967
+#define A5XX_RBBM_STATUS_VBIF_BUSY__MASK			0x00000200
1968
+#define A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT			9
1969
+static inline uint32_t A5XX_RBBM_STATUS_VBIF_BUSY(uint32_t val)
1970
+{
1971
+	return ((val) << A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT) & A5XX_RBBM_STATUS_VBIF_BUSY__MASK;
1972
+}
1973
+#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK		0x00000100
1974
+#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT		8
1975
+static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST(uint32_t val)
1976
+{
1977
+	return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK;
1978
+}
1979
+#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK			0x00000080
1980
+#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT		7
1981
+static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST(uint32_t val)
1982
+{
1983
+	return ((val) << A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK;
1984
+}
1985
+#define A5XX_RBBM_STATUS_CP_BUSY__MASK				0x00000040
1986
+#define A5XX_RBBM_STATUS_CP_BUSY__SHIFT				6
1987
+static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY(uint32_t val)
1988
+{
1989
+	return ((val) << A5XX_RBBM_STATUS_CP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY__MASK;
1990
+}
1991
+#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK			0x00000020
1992
+#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT		5
1993
+static inline uint32_t A5XX_RBBM_STATUS_GPMU_MASTER_BUSY(uint32_t val)
1994
+{
1995
+	return ((val) << A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK;
1996
+}
1997
+#define A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK			0x00000010
1998
+#define A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT			4
1999
+static inline uint32_t A5XX_RBBM_STATUS_CP_CRASH_BUSY(uint32_t val)
2000
+{
2001
+	return ((val) << A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK;
2002
+}
2003
+#define A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK			0x00000008
2004
+#define A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT			3
2005
+static inline uint32_t A5XX_RBBM_STATUS_CP_ETS_BUSY(uint32_t val)
2006
+{
2007
+	return ((val) << A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK;
2008
+}
2009
+#define A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK			0x00000004
2010
+#define A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT			2
2011
+static inline uint32_t A5XX_RBBM_STATUS_CP_PFP_BUSY(uint32_t val)
2012
+{
2013
+	return ((val) << A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK;
2014
+}
2015
+#define A5XX_RBBM_STATUS_CP_ME_BUSY__MASK			0x00000002
2016
+#define A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT			1
2017
+static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val)
2018
+{
2019
+	return ((val) << A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ME_BUSY__MASK;
2020
+}
18592021 #define A5XX_RBBM_STATUS_HI_BUSY				0x00000001
18602022 
18612023 #define REG_A5XX_RBBM_STATUS3					0x00000530
....@@ -1883,14 +2045,6 @@
18832045 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO			0x00000469
18842046 
18852047 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI			0x0000046a
1886
-
1887
-#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0			0x0000046b
1888
-
1889
-#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1			0x0000046c
1890
-
1891
-#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2			0x0000046d
1892
-
1893
-#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3			0x0000046e
18942048 
18952049 #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED			0x0000046f
18962050 
....@@ -2147,6 +2301,8 @@
21472301 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0			0x00000e00
21482302 
21492303 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1			0x00000e01
2304
+
2305
+#define REG_A5XX_HLSQ_DBG_ECO_CNTL				0x00000e04
21502306 
21512307 #define REG_A5XX_HLSQ_ADDR_MODE_CNTL				0x00000e05
21522308 
....@@ -2453,8 +2609,6 @@
24532609 
24542610 #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL			0x0000a894
24552611 
2456
-#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL			0x0000a8a3
2457
-
24582612 #define REG_A5XX_GPMU_WFI_CONFIG				0x0000a8c1
24592613 
24602614 #define REG_A5XX_GPMU_RBBM_INTR_INFO				0x0000a8d6
....@@ -2657,12 +2811,16 @@
26572811 #define REG_A5XX_UNKNOWN_E004					0x0000e004
26582812 
26592813 #define REG_A5XX_GRAS_CNTL					0x0000e005
2660
-#define A5XX_GRAS_CNTL_VARYING					0x00000001
2661
-#define A5XX_GRAS_CNTL_UNK3					0x00000008
2662
-#define A5XX_GRAS_CNTL_XCOORD					0x00000040
2663
-#define A5XX_GRAS_CNTL_YCOORD					0x00000080
2664
-#define A5XX_GRAS_CNTL_ZCOORD					0x00000100
2665
-#define A5XX_GRAS_CNTL_WCOORD					0x00000200
2814
+#define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL				0x00000001
2815
+#define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID			0x00000002
2816
+#define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE				0x00000004
2817
+#define A5XX_GRAS_CNTL_SIZE					0x00000008
2818
+#define A5XX_GRAS_CNTL_COORD_MASK__MASK				0x000003c0
2819
+#define A5XX_GRAS_CNTL_COORD_MASK__SHIFT			6
2820
+static inline uint32_t A5XX_GRAS_CNTL_COORD_MASK(uint32_t val)
2821
+{
2822
+	return ((val) << A5XX_GRAS_CNTL_COORD_MASK__SHIFT) & A5XX_GRAS_CNTL_COORD_MASK__MASK;
2823
+}
26662824 
26672825 #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ			0x0000e006
26682826 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK		0x000003ff
....@@ -2989,12 +3147,16 @@
29893147 #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004
29903148 
29913149 #define REG_A5XX_RB_RENDER_CONTROL0				0x0000e144
2992
-#define A5XX_RB_RENDER_CONTROL0_VARYING				0x00000001
2993
-#define A5XX_RB_RENDER_CONTROL0_UNK3				0x00000008
2994
-#define A5XX_RB_RENDER_CONTROL0_XCOORD				0x00000040
2995
-#define A5XX_RB_RENDER_CONTROL0_YCOORD				0x00000080
2996
-#define A5XX_RB_RENDER_CONTROL0_ZCOORD				0x00000100
2997
-#define A5XX_RB_RENDER_CONTROL0_WCOORD				0x00000200
3150
+#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL			0x00000001
3151
+#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID		0x00000002
3152
+#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE			0x00000004
3153
+#define A5XX_RB_RENDER_CONTROL0_SIZE				0x00000008
3154
+#define A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK		0x000003c0
3155
+#define A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT		6
3156
+static inline uint32_t A5XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
3157
+{
3158
+	return ((val) << A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
3159
+}
29983160 
29993161 #define REG_A5XX_RB_RENDER_CONTROL1				0x0000e145
30003162 #define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK			0x00000001
....@@ -4448,16 +4610,52 @@
44484610 {
44494611 	return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
44504612 }
4613
+#define A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK			0xff000000
4614
+#define A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT			24
4615
+static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
4616
+{
4617
+	return ((val) << A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
4618
+}
44514619 
44524620 #define REG_A5XX_HLSQ_CONTROL_3_REG				0x0000e787
4453
-#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK		0x000000ff
4454
-#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT		0
4455
-static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
4621
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK		0x000000ff
4622
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT		0
4623
+static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
44564624 {
4457
-	return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
4625
+	return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
4626
+}
4627
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK		0x0000ff00
4628
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT		8
4629
+static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
4630
+{
4631
+	return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
4632
+}
4633
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK		0x00ff0000
4634
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT	16
4635
+static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
4636
+{
4637
+	return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
4638
+}
4639
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK	0xff000000
4640
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT	24
4641
+static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
4642
+{
4643
+	return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
44584644 }
44594645 
44604646 #define REG_A5XX_HLSQ_CONTROL_4_REG				0x0000e788
4647
+#define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK		0x000000ff
4648
+#define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT		0
4649
+static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
4650
+{
4651
+	return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
4652
+}
4653
+#define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK		0x0000ff00
4654
+#define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT		8
4655
+static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
4656
+{
4657
+	return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
4658
+}
44614659 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK		0x00ff0000
44624660 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT		16
44634661 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
....@@ -4853,9 +5051,25 @@
48535051 
48545052 #define REG_A5XX_RB_2D_SRC_FLAGS_HI				0x00002141
48555053 
5054
+#define REG_A5XX_RB_2D_SRC_FLAGS_PITCH				0x00002142
5055
+#define A5XX_RB_2D_SRC_FLAGS_PITCH__MASK			0xffffffff
5056
+#define A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT			0
5057
+static inline uint32_t A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val)
5058
+{
5059
+	return ((val >> 6) << A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_SRC_FLAGS_PITCH__MASK;
5060
+}
5061
+
48565062 #define REG_A5XX_RB_2D_DST_FLAGS_LO				0x00002143
48575063 
48585064 #define REG_A5XX_RB_2D_DST_FLAGS_HI				0x00002144
5065
+
5066
+#define REG_A5XX_RB_2D_DST_FLAGS_PITCH				0x00002145
5067
+#define A5XX_RB_2D_DST_FLAGS_PITCH__MASK			0xffffffff
5068
+#define A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT			0
5069
+static inline uint32_t A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
5070
+{
5071
+	return ((val >> 6) << A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_DST_FLAGS_PITCH__MASK;
5072
+}
48595073 
48605074 #define REG_A5XX_GRAS_2D_BLIT_CNTL				0x00002180
48615075 
....@@ -5057,11 +5271,11 @@
50575271 }
50585272 
50595273 #define REG_A5XX_TEX_CONST_2					0x00000002
5060
-#define A5XX_TEX_CONST_2_FETCHSIZE__MASK			0x0000000f
5061
-#define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT			0
5062
-static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val)
5274
+#define A5XX_TEX_CONST_2_PITCHALIGN__MASK			0x0000000f
5275
+#define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT			0
5276
+static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
50635277 {
5064
-	return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK;
5278
+	return ((val) << A5XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A5XX_TEX_CONST_2_PITCHALIGN__MASK;
50655279 }
50665280 #define A5XX_TEX_CONST_2_PITCH__MASK				0x1fffff80
50675281 #define A5XX_TEX_CONST_2_PITCH__SHIFT				7
....@@ -5083,6 +5297,13 @@
50835297 {
50845298 	return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
50855299 }
5300
+#define A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK			0x07800000
5301
+#define A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT			23
5302
+static inline uint32_t A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
5303
+{
5304
+	return ((val >> 12) << A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
5305
+}
5306
+#define A5XX_TEX_CONST_3_TILE_ALL				0x08000000
50865307 #define A5XX_TEX_CONST_3_FLAG					0x10000000
50875308 
50885309 #define REG_A5XX_TEX_CONST_4					0x00000004
....@@ -5195,5 +5416,21 @@
51955416 	return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK;
51965417 }
51975418 
5419
+#define REG_A5XX_UBO_0						0x00000000
5420
+#define A5XX_UBO_0_BASE_LO__MASK				0xffffffff
5421
+#define A5XX_UBO_0_BASE_LO__SHIFT				0
5422
+static inline uint32_t A5XX_UBO_0_BASE_LO(uint32_t val)
5423
+{
5424
+	return ((val) << A5XX_UBO_0_BASE_LO__SHIFT) & A5XX_UBO_0_BASE_LO__MASK;
5425
+}
5426
+
5427
+#define REG_A5XX_UBO_1						0x00000001
5428
+#define A5XX_UBO_1_BASE_HI__MASK				0x0001ffff
5429
+#define A5XX_UBO_1_BASE_HI__SHIFT				0
5430
+static inline uint32_t A5XX_UBO_1_BASE_HI(uint32_t val)
5431
+{
5432
+	return ((val) << A5XX_UBO_1_BASE_HI__SHIFT) & A5XX_UBO_1_BASE_HI__MASK;
5433
+}
5434
+
51985435 
51995436 #endif /* A5XX_XML */