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2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920 
 kernel/drivers/gpu/drm/msm/adreno/a2xx.xml.h
....@@ -8,19 +8,21 @@
88 git clone https://github.com/freedreno/envytools.git
99 
1010 The rules-ng-ng source files this header was generated from are:
11
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
12
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
13
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  36805 bytes, from 2018-07-03 19:37:13)
14
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  13634 bytes, from 2018-07-03 19:37:13)
15
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  42393 bytes, from 2018-08-06 18:45:45)
16
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
17
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
18
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-08-06 18:45:45)
19
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 101627 bytes, from 2018-08-06 18:45:45)
20
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-07-03 19:37:13)
21
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
11
+- /home/robclark/src/envytools/rnndb/adreno.xml                     (    594 bytes, from 2020-07-23 21:58:14)
12
+- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml        (   1572 bytes, from 2020-07-23 21:58:14)
13
+- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml                (  90159 bytes, from 2020-07-23 21:58:14)
14
+- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml       (  14386 bytes, from 2020-07-23 21:58:14)
15
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml          (  65048 bytes, from 2020-07-23 21:58:14)
16
+- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml                (  84226 bytes, from 2020-07-23 21:58:14)
17
+- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml                ( 112556 bytes, from 2020-07-23 21:58:14)
18
+- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml                ( 149461 bytes, from 2020-07-23 21:58:14)
19
+- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml                ( 184695 bytes, from 2020-07-23 21:58:14)
20
+- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml            (  11218 bytes, from 2020-07-23 21:58:14)
21
+- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml               (   1773 bytes, from 2020-07-23 21:58:14)
22
+- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml (   4559 bytes, from 2020-07-23 21:58:14)
23
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml    (   2872 bytes, from 2020-07-23 21:58:14)
2224 
23
-Copyright (C) 2013-2018 by the following authors:
25
+Copyright (C) 2013-2020 by the following authors:
2426 - Rob Clark <robdclark@gmail.com> (robclark)
2527 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2628 
....@@ -210,6 +212,854 @@
210212 	BLEND2_DST_PLUS_SRC_BIAS = 5,
211213 };
212214 
215
+enum a2xx_su_perfcnt_select {
216
+	PERF_PAPC_PASX_REQ = 0,
217
+	PERF_PAPC_PASX_FIRST_VECTOR = 2,
218
+	PERF_PAPC_PASX_SECOND_VECTOR = 3,
219
+	PERF_PAPC_PASX_FIRST_DEAD = 4,
220
+	PERF_PAPC_PASX_SECOND_DEAD = 5,
221
+	PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
222
+	PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
223
+	PERF_PAPC_PA_INPUT_PRIM = 8,
224
+	PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
225
+	PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
226
+	PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
227
+	PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
228
+	PERF_PAPC_CLPR_CULL_PRIM = 13,
229
+	PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
230
+	PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
231
+	PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
232
+	PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
233
+	PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
234
+	PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
235
+	PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
236
+	PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
237
+	PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
238
+	PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
239
+	PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
240
+	PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
241
+	PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
242
+	PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
243
+	PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
244
+	PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
245
+	PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
246
+	PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
247
+	PERF_PAPC_CLSM_NULL_PRIM = 36,
248
+	PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
249
+	PERF_PAPC_CLSM_CLIP_PRIM = 38,
250
+	PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
251
+	PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
252
+	PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
253
+	PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
254
+	PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
255
+	PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
256
+	PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
257
+	PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
258
+	PERF_PAPC_SU_INPUT_PRIM = 47,
259
+	PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
260
+	PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
261
+	PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
262
+	PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
263
+	PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
264
+	PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
265
+	PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
266
+	PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
267
+	PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
268
+	PERF_PAPC_SU_OUTPUT_PRIM = 57,
269
+	PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
270
+	PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
271
+	PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
272
+	PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
273
+	PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
274
+	PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
275
+	PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
276
+	PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
277
+	PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
278
+	PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
279
+	PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
280
+	PERF_PAPC_PASX_REQ_IDLE = 69,
281
+	PERF_PAPC_PASX_REQ_BUSY = 70,
282
+	PERF_PAPC_PASX_REQ_STALLED = 71,
283
+	PERF_PAPC_PASX_REC_IDLE = 72,
284
+	PERF_PAPC_PASX_REC_BUSY = 73,
285
+	PERF_PAPC_PASX_REC_STARVED_SX = 74,
286
+	PERF_PAPC_PASX_REC_STALLED = 75,
287
+	PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
288
+	PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
289
+	PERF_PAPC_CCGSM_IDLE = 78,
290
+	PERF_PAPC_CCGSM_BUSY = 79,
291
+	PERF_PAPC_CCGSM_STALLED = 80,
292
+	PERF_PAPC_CLPRIM_IDLE = 81,
293
+	PERF_PAPC_CLPRIM_BUSY = 82,
294
+	PERF_PAPC_CLPRIM_STALLED = 83,
295
+	PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
296
+	PERF_PAPC_CLIPSM_IDLE = 85,
297
+	PERF_PAPC_CLIPSM_BUSY = 86,
298
+	PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
299
+	PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
300
+	PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
301
+	PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
302
+	PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
303
+	PERF_PAPC_CLIPGA_IDLE = 92,
304
+	PERF_PAPC_CLIPGA_BUSY = 93,
305
+	PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
306
+	PERF_PAPC_CLIPGA_STALLED = 95,
307
+	PERF_PAPC_CLIP_IDLE = 96,
308
+	PERF_PAPC_CLIP_BUSY = 97,
309
+	PERF_PAPC_SU_IDLE = 98,
310
+	PERF_PAPC_SU_BUSY = 99,
311
+	PERF_PAPC_SU_STARVED_CLIP = 100,
312
+	PERF_PAPC_SU_STALLED_SC = 101,
313
+	PERF_PAPC_SU_FACENESS_CULL = 102,
314
+};
315
+
316
+enum a2xx_sc_perfcnt_select {
317
+	SC_SR_WINDOW_VALID = 0,
318
+	SC_CW_WINDOW_VALID = 1,
319
+	SC_QM_WINDOW_VALID = 2,
320
+	SC_FW_WINDOW_VALID = 3,
321
+	SC_EZ_WINDOW_VALID = 4,
322
+	SC_IT_WINDOW_VALID = 5,
323
+	SC_STARVED_BY_PA = 6,
324
+	SC_STALLED_BY_RB_TILE = 7,
325
+	SC_STALLED_BY_RB_SAMP = 8,
326
+	SC_STARVED_BY_RB_EZ = 9,
327
+	SC_STALLED_BY_SAMPLE_FF = 10,
328
+	SC_STALLED_BY_SQ = 11,
329
+	SC_STALLED_BY_SP = 12,
330
+	SC_TOTAL_NO_PRIMS = 13,
331
+	SC_NON_EMPTY_PRIMS = 14,
332
+	SC_NO_TILES_PASSING_QM = 15,
333
+	SC_NO_PIXELS_PRE_EZ = 16,
334
+	SC_NO_PIXELS_POST_EZ = 17,
335
+};
336
+
337
+enum a2xx_vgt_perfcount_select {
338
+	VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
339
+	VGT_SQ_SEND = 1,
340
+	VGT_SQ_STALLED = 2,
341
+	VGT_SQ_STARVED_BUSY = 3,
342
+	VGT_SQ_STARVED_IDLE = 4,
343
+	VGT_SQ_STATIC = 5,
344
+	VGT_PA_EVENT_WINDOW_ACTIVE = 6,
345
+	VGT_PA_CLIP_V_SEND = 7,
346
+	VGT_PA_CLIP_V_STALLED = 8,
347
+	VGT_PA_CLIP_V_STARVED_BUSY = 9,
348
+	VGT_PA_CLIP_V_STARVED_IDLE = 10,
349
+	VGT_PA_CLIP_V_STATIC = 11,
350
+	VGT_PA_CLIP_P_SEND = 12,
351
+	VGT_PA_CLIP_P_STALLED = 13,
352
+	VGT_PA_CLIP_P_STARVED_BUSY = 14,
353
+	VGT_PA_CLIP_P_STARVED_IDLE = 15,
354
+	VGT_PA_CLIP_P_STATIC = 16,
355
+	VGT_PA_CLIP_S_SEND = 17,
356
+	VGT_PA_CLIP_S_STALLED = 18,
357
+	VGT_PA_CLIP_S_STARVED_BUSY = 19,
358
+	VGT_PA_CLIP_S_STARVED_IDLE = 20,
359
+	VGT_PA_CLIP_S_STATIC = 21,
360
+	RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
361
+	RBIU_IMMED_DATA_FIFO_STARVED = 23,
362
+	RBIU_IMMED_DATA_FIFO_STALLED = 24,
363
+	RBIU_DMA_REQUEST_FIFO_STARVED = 25,
364
+	RBIU_DMA_REQUEST_FIFO_STALLED = 26,
365
+	RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
366
+	RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
367
+	BIN_PRIM_NEAR_CULL = 29,
368
+	BIN_PRIM_ZERO_CULL = 30,
369
+	BIN_PRIM_FAR_CULL = 31,
370
+	BIN_PRIM_BIN_CULL = 32,
371
+	BIN_PRIM_FACE_CULL = 33,
372
+	SPARE34 = 34,
373
+	SPARE35 = 35,
374
+	SPARE36 = 36,
375
+	SPARE37 = 37,
376
+	SPARE38 = 38,
377
+	SPARE39 = 39,
378
+	TE_SU_IN_VALID = 40,
379
+	TE_SU_IN_READ = 41,
380
+	TE_SU_IN_PRIM = 42,
381
+	TE_SU_IN_EOP = 43,
382
+	TE_SU_IN_NULL_PRIM = 44,
383
+	TE_WK_IN_VALID = 45,
384
+	TE_WK_IN_READ = 46,
385
+	TE_OUT_PRIM_VALID = 47,
386
+	TE_OUT_PRIM_READ = 48,
387
+};
388
+
389
+enum a2xx_tcr_perfcount_select {
390
+	DGMMPD_IPMUX0_STALL = 0,
391
+	DGMMPD_IPMUX_ALL_STALL = 4,
392
+	OPMUX0_L2_WRITES = 5,
393
+};
394
+
395
+enum a2xx_tp_perfcount_select {
396
+	POINT_QUADS = 0,
397
+	BILIN_QUADS = 1,
398
+	ANISO_QUADS = 2,
399
+	MIP_QUADS = 3,
400
+	VOL_QUADS = 4,
401
+	MIP_VOL_QUADS = 5,
402
+	MIP_ANISO_QUADS = 6,
403
+	VOL_ANISO_QUADS = 7,
404
+	ANISO_2_1_QUADS = 8,
405
+	ANISO_4_1_QUADS = 9,
406
+	ANISO_6_1_QUADS = 10,
407
+	ANISO_8_1_QUADS = 11,
408
+	ANISO_10_1_QUADS = 12,
409
+	ANISO_12_1_QUADS = 13,
410
+	ANISO_14_1_QUADS = 14,
411
+	ANISO_16_1_QUADS = 15,
412
+	MIP_VOL_ANISO_QUADS = 16,
413
+	ALIGN_2_QUADS = 17,
414
+	ALIGN_4_QUADS = 18,
415
+	PIX_0_QUAD = 19,
416
+	PIX_1_QUAD = 20,
417
+	PIX_2_QUAD = 21,
418
+	PIX_3_QUAD = 22,
419
+	PIX_4_QUAD = 23,
420
+	TP_MIPMAP_LOD0 = 24,
421
+	TP_MIPMAP_LOD1 = 25,
422
+	TP_MIPMAP_LOD2 = 26,
423
+	TP_MIPMAP_LOD3 = 27,
424
+	TP_MIPMAP_LOD4 = 28,
425
+	TP_MIPMAP_LOD5 = 29,
426
+	TP_MIPMAP_LOD6 = 30,
427
+	TP_MIPMAP_LOD7 = 31,
428
+	TP_MIPMAP_LOD8 = 32,
429
+	TP_MIPMAP_LOD9 = 33,
430
+	TP_MIPMAP_LOD10 = 34,
431
+	TP_MIPMAP_LOD11 = 35,
432
+	TP_MIPMAP_LOD12 = 36,
433
+	TP_MIPMAP_LOD13 = 37,
434
+	TP_MIPMAP_LOD14 = 38,
435
+};
436
+
437
+enum a2xx_tcm_perfcount_select {
438
+	QUAD0_RD_LAT_FIFO_EMPTY = 0,
439
+	QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
440
+	QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
441
+	QUAD0_RD_LAT_FIFO_FULL = 5,
442
+	QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
443
+	READ_STARVED_QUAD0 = 28,
444
+	READ_STARVED = 32,
445
+	READ_STALLED_QUAD0 = 33,
446
+	READ_STALLED = 37,
447
+	VALID_READ_QUAD0 = 38,
448
+	TC_TP_STARVED_QUAD0 = 42,
449
+	TC_TP_STARVED = 46,
450
+};
451
+
452
+enum a2xx_tcf_perfcount_select {
453
+	VALID_CYCLES = 0,
454
+	SINGLE_PHASES = 1,
455
+	ANISO_PHASES = 2,
456
+	MIP_PHASES = 3,
457
+	VOL_PHASES = 4,
458
+	MIP_VOL_PHASES = 5,
459
+	MIP_ANISO_PHASES = 6,
460
+	VOL_ANISO_PHASES = 7,
461
+	ANISO_2_1_PHASES = 8,
462
+	ANISO_4_1_PHASES = 9,
463
+	ANISO_6_1_PHASES = 10,
464
+	ANISO_8_1_PHASES = 11,
465
+	ANISO_10_1_PHASES = 12,
466
+	ANISO_12_1_PHASES = 13,
467
+	ANISO_14_1_PHASES = 14,
468
+	ANISO_16_1_PHASES = 15,
469
+	MIP_VOL_ANISO_PHASES = 16,
470
+	ALIGN_2_PHASES = 17,
471
+	ALIGN_4_PHASES = 18,
472
+	TPC_BUSY = 19,
473
+	TPC_STALLED = 20,
474
+	TPC_STARVED = 21,
475
+	TPC_WORKING = 22,
476
+	TPC_WALKER_BUSY = 23,
477
+	TPC_WALKER_STALLED = 24,
478
+	TPC_WALKER_WORKING = 25,
479
+	TPC_ALIGNER_BUSY = 26,
480
+	TPC_ALIGNER_STALLED = 27,
481
+	TPC_ALIGNER_STALLED_BY_BLEND = 28,
482
+	TPC_ALIGNER_STALLED_BY_CACHE = 29,
483
+	TPC_ALIGNER_WORKING = 30,
484
+	TPC_BLEND_BUSY = 31,
485
+	TPC_BLEND_SYNC = 32,
486
+	TPC_BLEND_STARVED = 33,
487
+	TPC_BLEND_WORKING = 34,
488
+	OPCODE_0x00 = 35,
489
+	OPCODE_0x01 = 36,
490
+	OPCODE_0x04 = 37,
491
+	OPCODE_0x10 = 38,
492
+	OPCODE_0x11 = 39,
493
+	OPCODE_0x12 = 40,
494
+	OPCODE_0x13 = 41,
495
+	OPCODE_0x18 = 42,
496
+	OPCODE_0x19 = 43,
497
+	OPCODE_0x1A = 44,
498
+	OPCODE_OTHER = 45,
499
+	IN_FIFO_0_EMPTY = 56,
500
+	IN_FIFO_0_LT_HALF_FULL = 57,
501
+	IN_FIFO_0_HALF_FULL = 58,
502
+	IN_FIFO_0_FULL = 59,
503
+	IN_FIFO_TPC_EMPTY = 72,
504
+	IN_FIFO_TPC_LT_HALF_FULL = 73,
505
+	IN_FIFO_TPC_HALF_FULL = 74,
506
+	IN_FIFO_TPC_FULL = 75,
507
+	TPC_TC_XFC = 76,
508
+	TPC_TC_STATE = 77,
509
+	TC_STALL = 78,
510
+	QUAD0_TAPS = 79,
511
+	QUADS = 83,
512
+	TCA_SYNC_STALL = 84,
513
+	TAG_STALL = 85,
514
+	TCB_SYNC_STALL = 88,
515
+	TCA_VALID = 89,
516
+	PROBES_VALID = 90,
517
+	MISS_STALL = 91,
518
+	FETCH_FIFO_STALL = 92,
519
+	TCO_STALL = 93,
520
+	ANY_STALL = 94,
521
+	TAG_MISSES = 95,
522
+	TAG_HITS = 96,
523
+	SUB_TAG_MISSES = 97,
524
+	SET0_INVALIDATES = 98,
525
+	SET1_INVALIDATES = 99,
526
+	SET2_INVALIDATES = 100,
527
+	SET3_INVALIDATES = 101,
528
+	SET0_TAG_MISSES = 102,
529
+	SET1_TAG_MISSES = 103,
530
+	SET2_TAG_MISSES = 104,
531
+	SET3_TAG_MISSES = 105,
532
+	SET0_TAG_HITS = 106,
533
+	SET1_TAG_HITS = 107,
534
+	SET2_TAG_HITS = 108,
535
+	SET3_TAG_HITS = 109,
536
+	SET0_SUB_TAG_MISSES = 110,
537
+	SET1_SUB_TAG_MISSES = 111,
538
+	SET2_SUB_TAG_MISSES = 112,
539
+	SET3_SUB_TAG_MISSES = 113,
540
+	SET0_EVICT1 = 114,
541
+	SET0_EVICT2 = 115,
542
+	SET0_EVICT3 = 116,
543
+	SET0_EVICT4 = 117,
544
+	SET0_EVICT5 = 118,
545
+	SET0_EVICT6 = 119,
546
+	SET0_EVICT7 = 120,
547
+	SET0_EVICT8 = 121,
548
+	SET1_EVICT1 = 130,
549
+	SET1_EVICT2 = 131,
550
+	SET1_EVICT3 = 132,
551
+	SET1_EVICT4 = 133,
552
+	SET1_EVICT5 = 134,
553
+	SET1_EVICT6 = 135,
554
+	SET1_EVICT7 = 136,
555
+	SET1_EVICT8 = 137,
556
+	SET2_EVICT1 = 146,
557
+	SET2_EVICT2 = 147,
558
+	SET2_EVICT3 = 148,
559
+	SET2_EVICT4 = 149,
560
+	SET2_EVICT5 = 150,
561
+	SET2_EVICT6 = 151,
562
+	SET2_EVICT7 = 152,
563
+	SET2_EVICT8 = 153,
564
+	SET3_EVICT1 = 162,
565
+	SET3_EVICT2 = 163,
566
+	SET3_EVICT3 = 164,
567
+	SET3_EVICT4 = 165,
568
+	SET3_EVICT5 = 166,
569
+	SET3_EVICT6 = 167,
570
+	SET3_EVICT7 = 168,
571
+	SET3_EVICT8 = 169,
572
+	FF_EMPTY = 178,
573
+	FF_LT_HALF_FULL = 179,
574
+	FF_HALF_FULL = 180,
575
+	FF_FULL = 181,
576
+	FF_XFC = 182,
577
+	FF_STALLED = 183,
578
+	FG_MASKS = 184,
579
+	FG_LEFT_MASKS = 185,
580
+	FG_LEFT_MASK_STALLED = 186,
581
+	FG_LEFT_NOT_DONE_STALL = 187,
582
+	FG_LEFT_FG_STALL = 188,
583
+	FG_LEFT_SECTORS = 189,
584
+	FG0_REQUESTS = 195,
585
+	FG0_STALLED = 196,
586
+	MEM_REQ512 = 199,
587
+	MEM_REQ_SENT = 200,
588
+	MEM_LOCAL_READ_REQ = 202,
589
+	TC0_MH_STALLED = 203,
590
+};
591
+
592
+enum a2xx_sq_perfcnt_select {
593
+	SQ_PIXEL_VECTORS_SUB = 0,
594
+	SQ_VERTEX_VECTORS_SUB = 1,
595
+	SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
596
+	SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
597
+	SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
598
+	SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
599
+	SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
600
+	SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
601
+	SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
602
+	SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
603
+	SQ_EXPORT_CYCLES = 10,
604
+	SQ_ALU_CST_WRITTEN = 11,
605
+	SQ_TEX_CST_WRITTEN = 12,
606
+	SQ_ALU_CST_STALL = 13,
607
+	SQ_ALU_TEX_STALL = 14,
608
+	SQ_INST_WRITTEN = 15,
609
+	SQ_BOOLEAN_WRITTEN = 16,
610
+	SQ_LOOPS_WRITTEN = 17,
611
+	SQ_PIXEL_SWAP_IN = 18,
612
+	SQ_PIXEL_SWAP_OUT = 19,
613
+	SQ_VERTEX_SWAP_IN = 20,
614
+	SQ_VERTEX_SWAP_OUT = 21,
615
+	SQ_ALU_VTX_INST_ISSUED = 22,
616
+	SQ_TEX_VTX_INST_ISSUED = 23,
617
+	SQ_VC_VTX_INST_ISSUED = 24,
618
+	SQ_CF_VTX_INST_ISSUED = 25,
619
+	SQ_ALU_PIX_INST_ISSUED = 26,
620
+	SQ_TEX_PIX_INST_ISSUED = 27,
621
+	SQ_VC_PIX_INST_ISSUED = 28,
622
+	SQ_CF_PIX_INST_ISSUED = 29,
623
+	SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
624
+	SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
625
+	SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
626
+	SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
627
+	SQ_ALU_NOPS = 34,
628
+	SQ_PRED_SKIP = 35,
629
+	SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
630
+	SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
631
+	SQ_SYNC_TEX_STALL_VTX = 38,
632
+	SQ_SYNC_VC_STALL_VTX = 39,
633
+	SQ_CONSTANTS_USED_SIMD0 = 40,
634
+	SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
635
+	SQ_GPR_STALL_VTX = 42,
636
+	SQ_GPR_STALL_PIX = 43,
637
+	SQ_VTX_RS_STALL = 44,
638
+	SQ_PIX_RS_STALL = 45,
639
+	SQ_SX_PC_FULL = 46,
640
+	SQ_SX_EXP_BUFF_FULL = 47,
641
+	SQ_SX_POS_BUFF_FULL = 48,
642
+	SQ_INTERP_QUADS = 49,
643
+	SQ_INTERP_ACTIVE = 50,
644
+	SQ_IN_PIXEL_STALL = 51,
645
+	SQ_IN_VTX_STALL = 52,
646
+	SQ_VTX_CNT = 53,
647
+	SQ_VTX_VECTOR2 = 54,
648
+	SQ_VTX_VECTOR3 = 55,
649
+	SQ_VTX_VECTOR4 = 56,
650
+	SQ_PIXEL_VECTOR1 = 57,
651
+	SQ_PIXEL_VECTOR23 = 58,
652
+	SQ_PIXEL_VECTOR4 = 59,
653
+	SQ_CONSTANTS_USED_SIMD1 = 60,
654
+	SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
655
+	SQ_SX_MEM_EXP_FULL = 62,
656
+	SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
657
+	SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
658
+	SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
659
+	SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
660
+	SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
661
+	SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68,
662
+	SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
663
+	SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70,
664
+	SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
665
+	SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
666
+	SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
667
+	SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
668
+	SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
669
+	SQ_PERFCOUNT_VTX_POP_THREAD = 76,
670
+	SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
671
+	SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
672
+	SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
673
+	SQ_PERFCOUNT_PIX_POP_THREAD = 80,
674
+	SQ_SYNC_TEX_STALL_PIX = 81,
675
+	SQ_SYNC_VC_STALL_PIX = 82,
676
+	SQ_CONSTANTS_USED_SIMD2 = 83,
677
+	SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
678
+	SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85,
679
+	SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86,
680
+	SQ_ALU0_FIFO_FULL_SIMD0 = 87,
681
+	SQ_ALU1_FIFO_FULL_SIMD0 = 88,
682
+	SQ_ALU0_FIFO_FULL_SIMD1 = 89,
683
+	SQ_ALU1_FIFO_FULL_SIMD1 = 90,
684
+	SQ_ALU0_FIFO_FULL_SIMD2 = 91,
685
+	SQ_ALU1_FIFO_FULL_SIMD2 = 92,
686
+	SQ_ALU0_FIFO_FULL_SIMD3 = 93,
687
+	SQ_ALU1_FIFO_FULL_SIMD3 = 94,
688
+	VC_PERF_STATIC = 95,
689
+	VC_PERF_STALLED = 96,
690
+	VC_PERF_STARVED = 97,
691
+	VC_PERF_SEND = 98,
692
+	VC_PERF_ACTUAL_STARVED = 99,
693
+	PIXEL_THREAD_0_ACTIVE = 100,
694
+	VERTEX_THREAD_0_ACTIVE = 101,
695
+	PIXEL_THREAD_0_NUMBER = 102,
696
+	VERTEX_THREAD_0_NUMBER = 103,
697
+	VERTEX_EVENT_NUMBER = 104,
698
+	PIXEL_EVENT_NUMBER = 105,
699
+	PTRBUFF_EF_PUSH = 106,
700
+	PTRBUFF_EF_POP_EVENT = 107,
701
+	PTRBUFF_EF_POP_NEW_VTX = 108,
702
+	PTRBUFF_EF_POP_DEALLOC = 109,
703
+	PTRBUFF_EF_POP_PVECTOR = 110,
704
+	PTRBUFF_EF_POP_PVECTOR_X = 111,
705
+	PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
706
+	PTRBUFF_PB_DEALLOC = 113,
707
+	PTRBUFF_PI_STATE_PPB_POP = 114,
708
+	PTRBUFF_PI_RTR = 115,
709
+	PTRBUFF_PI_READ_EN = 116,
710
+	PTRBUFF_PI_BUFF_SWAP = 117,
711
+	PTRBUFF_SQ_FREE_BUFF = 118,
712
+	PTRBUFF_SQ_DEC = 119,
713
+	PTRBUFF_SC_VALID_CNTL_EVENT = 120,
714
+	PTRBUFF_SC_VALID_IJ_XFER = 121,
715
+	PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
716
+	PTRBUFF_QUAL_NEW_VECTOR = 123,
717
+	PTRBUFF_QUAL_EVENT = 124,
718
+	PTRBUFF_END_BUFFER = 125,
719
+	PTRBUFF_FILL_QUAD = 126,
720
+	VERTS_WRITTEN_SPI = 127,
721
+	TP_FETCH_INSTR_EXEC = 128,
722
+	TP_FETCH_INSTR_REQ = 129,
723
+	TP_DATA_RETURN = 130,
724
+	SPI_WRITE_CYCLES_SP = 131,
725
+	SPI_WRITES_SP = 132,
726
+	SP_ALU_INSTR_EXEC = 133,
727
+	SP_CONST_ADDR_TO_SQ = 134,
728
+	SP_PRED_KILLS_TO_SQ = 135,
729
+	SP_EXPORT_CYCLES_TO_SX = 136,
730
+	SP_EXPORTS_TO_SX = 137,
731
+	SQ_CYCLES_ELAPSED = 138,
732
+	SQ_TCFS_OPT_ALLOC_EXEC = 139,
733
+	SQ_TCFS_NO_OPT_ALLOC = 140,
734
+	SQ_ALU0_NO_OPT_ALLOC = 141,
735
+	SQ_ALU1_NO_OPT_ALLOC = 142,
736
+	SQ_TCFS_ARB_XFC_CNT = 143,
737
+	SQ_ALU0_ARB_XFC_CNT = 144,
738
+	SQ_ALU1_ARB_XFC_CNT = 145,
739
+	SQ_TCFS_CFS_UPDATE_CNT = 146,
740
+	SQ_ALU0_CFS_UPDATE_CNT = 147,
741
+	SQ_ALU1_CFS_UPDATE_CNT = 148,
742
+	SQ_VTX_PUSH_THREAD_CNT = 149,
743
+	SQ_VTX_POP_THREAD_CNT = 150,
744
+	SQ_PIX_PUSH_THREAD_CNT = 151,
745
+	SQ_PIX_POP_THREAD_CNT = 152,
746
+	SQ_PIX_TOTAL = 153,
747
+	SQ_PIX_KILLED = 154,
748
+};
749
+
750
+enum a2xx_sx_perfcnt_select {
751
+	SX_EXPORT_VECTORS = 0,
752
+	SX_DUMMY_QUADS = 1,
753
+	SX_ALPHA_FAIL = 2,
754
+	SX_RB_QUAD_BUSY = 3,
755
+	SX_RB_COLOR_BUSY = 4,
756
+	SX_RB_QUAD_STALL = 5,
757
+	SX_RB_COLOR_STALL = 6,
758
+};
759
+
760
+enum a2xx_rbbm_perfcount1_sel {
761
+	RBBM1_COUNT = 0,
762
+	RBBM1_NRT_BUSY = 1,
763
+	RBBM1_RB_BUSY = 2,
764
+	RBBM1_SQ_CNTX0_BUSY = 3,
765
+	RBBM1_SQ_CNTX17_BUSY = 4,
766
+	RBBM1_VGT_BUSY = 5,
767
+	RBBM1_VGT_NODMA_BUSY = 6,
768
+	RBBM1_PA_BUSY = 7,
769
+	RBBM1_SC_CNTX_BUSY = 8,
770
+	RBBM1_TPC_BUSY = 9,
771
+	RBBM1_TC_BUSY = 10,
772
+	RBBM1_SX_BUSY = 11,
773
+	RBBM1_CP_COHER_BUSY = 12,
774
+	RBBM1_CP_NRT_BUSY = 13,
775
+	RBBM1_GFX_IDLE_STALL = 14,
776
+	RBBM1_INTERRUPT = 15,
777
+};
778
+
779
+enum a2xx_cp_perfcount_sel {
780
+	ALWAYS_COUNT = 0,
781
+	TRANS_FIFO_FULL = 1,
782
+	TRANS_FIFO_AF = 2,
783
+	RCIU_PFPTRANS_WAIT = 3,
784
+	RCIU_NRTTRANS_WAIT = 6,
785
+	CSF_NRT_READ_WAIT = 8,
786
+	CSF_I1_FIFO_FULL = 9,
787
+	CSF_I2_FIFO_FULL = 10,
788
+	CSF_ST_FIFO_FULL = 11,
789
+	CSF_RING_ROQ_FULL = 13,
790
+	CSF_I1_ROQ_FULL = 14,
791
+	CSF_I2_ROQ_FULL = 15,
792
+	CSF_ST_ROQ_FULL = 16,
793
+	MIU_TAG_MEM_FULL = 18,
794
+	MIU_WRITECLEAN = 19,
795
+	MIU_NRT_WRITE_STALLED = 22,
796
+	MIU_NRT_READ_STALLED = 23,
797
+	ME_WRITE_CONFIRM_FIFO_FULL = 24,
798
+	ME_VS_DEALLOC_FIFO_FULL = 25,
799
+	ME_PS_DEALLOC_FIFO_FULL = 26,
800
+	ME_REGS_VS_EVENT_FIFO_FULL = 27,
801
+	ME_REGS_PS_EVENT_FIFO_FULL = 28,
802
+	ME_REGS_CF_EVENT_FIFO_FULL = 29,
803
+	ME_MICRO_RB_STARVED = 30,
804
+	ME_MICRO_I1_STARVED = 31,
805
+	ME_MICRO_I2_STARVED = 32,
806
+	ME_MICRO_ST_STARVED = 33,
807
+	RCIU_RBBM_DWORD_SENT = 40,
808
+	ME_BUSY_CLOCKS = 41,
809
+	ME_WAIT_CONTEXT_AVAIL = 42,
810
+	PFP_TYPE0_PACKET = 43,
811
+	PFP_TYPE3_PACKET = 44,
812
+	CSF_RB_WPTR_NEQ_RPTR = 45,
813
+	CSF_I1_SIZE_NEQ_ZERO = 46,
814
+	CSF_I2_SIZE_NEQ_ZERO = 47,
815
+	CSF_RBI1I2_FETCHING = 48,
816
+};
817
+
818
+enum a2xx_rb_perfcnt_select {
819
+	RBPERF_CNTX_BUSY = 0,
820
+	RBPERF_CNTX_BUSY_MAX = 1,
821
+	RBPERF_SX_QUAD_STARVED = 2,
822
+	RBPERF_SX_QUAD_STARVED_MAX = 3,
823
+	RBPERF_GA_GC_CH0_SYS_REQ = 4,
824
+	RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
825
+	RBPERF_GA_GC_CH1_SYS_REQ = 6,
826
+	RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
827
+	RBPERF_MH_STARVED = 8,
828
+	RBPERF_MH_STARVED_MAX = 9,
829
+	RBPERF_AZ_BC_COLOR_BUSY = 10,
830
+	RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
831
+	RBPERF_AZ_BC_Z_BUSY = 12,
832
+	RBPERF_AZ_BC_Z_BUSY_MAX = 13,
833
+	RBPERF_RB_SC_TILE_RTR_N = 14,
834
+	RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
835
+	RBPERF_RB_SC_SAMP_RTR_N = 16,
836
+	RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
837
+	RBPERF_RB_SX_QUAD_RTR_N = 18,
838
+	RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
839
+	RBPERF_RB_SX_COLOR_RTR_N = 20,
840
+	RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
841
+	RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
842
+	RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
843
+	RBPERF_ZXP_STALL = 24,
844
+	RBPERF_ZXP_STALL_MAX = 25,
845
+	RBPERF_EVENT_PENDING = 26,
846
+	RBPERF_EVENT_PENDING_MAX = 27,
847
+	RBPERF_RB_MH_VALID = 28,
848
+	RBPERF_RB_MH_VALID_MAX = 29,
849
+	RBPERF_SX_RB_QUAD_SEND = 30,
850
+	RBPERF_SX_RB_COLOR_SEND = 31,
851
+	RBPERF_SC_RB_TILE_SEND = 32,
852
+	RBPERF_SC_RB_SAMPLE_SEND = 33,
853
+	RBPERF_SX_RB_MEM_EXPORT = 34,
854
+	RBPERF_SX_RB_QUAD_EVENT = 35,
855
+	RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
856
+	RBPERF_SC_RB_TILE_EVENT_ALL = 37,
857
+	RBPERF_RB_SC_EZ_SEND = 38,
858
+	RBPERF_RB_SX_INDEX_SEND = 39,
859
+	RBPERF_GMEM_INTFO_RD = 40,
860
+	RBPERF_GMEM_INTF1_RD = 41,
861
+	RBPERF_GMEM_INTFO_WR = 42,
862
+	RBPERF_GMEM_INTF1_WR = 43,
863
+	RBPERF_RB_CP_CONTEXT_DONE = 44,
864
+	RBPERF_RB_CP_CACHE_FLUSH = 45,
865
+	RBPERF_ZPASS_DONE = 46,
866
+	RBPERF_ZCMD_VALID = 47,
867
+	RBPERF_CCMD_VALID = 48,
868
+	RBPERF_ACCUM_GRANT = 49,
869
+	RBPERF_ACCUM_C0_GRANT = 50,
870
+	RBPERF_ACCUM_C1_GRANT = 51,
871
+	RBPERF_ACCUM_FULL_BE_WR = 52,
872
+	RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
873
+	RBPERF_ACCUM_TIMEOUT_PULSE = 54,
874
+	RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
875
+	RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
876
+};
877
+
878
+enum a2xx_mh_perfcnt_select {
879
+	CP_R0_REQUESTS = 0,
880
+	CP_R1_REQUESTS = 1,
881
+	CP_R2_REQUESTS = 2,
882
+	CP_R3_REQUESTS = 3,
883
+	CP_R4_REQUESTS = 4,
884
+	CP_TOTAL_READ_REQUESTS = 5,
885
+	CP_TOTAL_WRITE_REQUESTS = 6,
886
+	CP_TOTAL_REQUESTS = 7,
887
+	CP_DATA_BYTES_WRITTEN = 8,
888
+	CP_WRITE_CLEAN_RESPONSES = 9,
889
+	CP_R0_READ_BURSTS_RECEIVED = 10,
890
+	CP_R1_READ_BURSTS_RECEIVED = 11,
891
+	CP_R2_READ_BURSTS_RECEIVED = 12,
892
+	CP_R3_READ_BURSTS_RECEIVED = 13,
893
+	CP_R4_READ_BURSTS_RECEIVED = 14,
894
+	CP_TOTAL_READ_BURSTS_RECEIVED = 15,
895
+	CP_R0_DATA_BEATS_READ = 16,
896
+	CP_R1_DATA_BEATS_READ = 17,
897
+	CP_R2_DATA_BEATS_READ = 18,
898
+	CP_R3_DATA_BEATS_READ = 19,
899
+	CP_R4_DATA_BEATS_READ = 20,
900
+	CP_TOTAL_DATA_BEATS_READ = 21,
901
+	VGT_R0_REQUESTS = 22,
902
+	VGT_R1_REQUESTS = 23,
903
+	VGT_TOTAL_REQUESTS = 24,
904
+	VGT_R0_READ_BURSTS_RECEIVED = 25,
905
+	VGT_R1_READ_BURSTS_RECEIVED = 26,
906
+	VGT_TOTAL_READ_BURSTS_RECEIVED = 27,
907
+	VGT_R0_DATA_BEATS_READ = 28,
908
+	VGT_R1_DATA_BEATS_READ = 29,
909
+	VGT_TOTAL_DATA_BEATS_READ = 30,
910
+	TC_TOTAL_REQUESTS = 31,
911
+	TC_ROQ_REQUESTS = 32,
912
+	TC_INFO_SENT = 33,
913
+	TC_READ_BURSTS_RECEIVED = 34,
914
+	TC_DATA_BEATS_READ = 35,
915
+	TCD_BURSTS_READ = 36,
916
+	RB_REQUESTS = 37,
917
+	RB_DATA_BYTES_WRITTEN = 38,
918
+	RB_WRITE_CLEAN_RESPONSES = 39,
919
+	AXI_READ_REQUESTS_ID_0 = 40,
920
+	AXI_READ_REQUESTS_ID_1 = 41,
921
+	AXI_READ_REQUESTS_ID_2 = 42,
922
+	AXI_READ_REQUESTS_ID_3 = 43,
923
+	AXI_READ_REQUESTS_ID_4 = 44,
924
+	AXI_READ_REQUESTS_ID_5 = 45,
925
+	AXI_READ_REQUESTS_ID_6 = 46,
926
+	AXI_READ_REQUESTS_ID_7 = 47,
927
+	AXI_TOTAL_READ_REQUESTS = 48,
928
+	AXI_WRITE_REQUESTS_ID_0 = 49,
929
+	AXI_WRITE_REQUESTS_ID_1 = 50,
930
+	AXI_WRITE_REQUESTS_ID_2 = 51,
931
+	AXI_WRITE_REQUESTS_ID_3 = 52,
932
+	AXI_WRITE_REQUESTS_ID_4 = 53,
933
+	AXI_WRITE_REQUESTS_ID_5 = 54,
934
+	AXI_WRITE_REQUESTS_ID_6 = 55,
935
+	AXI_WRITE_REQUESTS_ID_7 = 56,
936
+	AXI_TOTAL_WRITE_REQUESTS = 57,
937
+	AXI_TOTAL_REQUESTS_ID_0 = 58,
938
+	AXI_TOTAL_REQUESTS_ID_1 = 59,
939
+	AXI_TOTAL_REQUESTS_ID_2 = 60,
940
+	AXI_TOTAL_REQUESTS_ID_3 = 61,
941
+	AXI_TOTAL_REQUESTS_ID_4 = 62,
942
+	AXI_TOTAL_REQUESTS_ID_5 = 63,
943
+	AXI_TOTAL_REQUESTS_ID_6 = 64,
944
+	AXI_TOTAL_REQUESTS_ID_7 = 65,
945
+	AXI_TOTAL_REQUESTS = 66,
946
+	AXI_READ_CHANNEL_BURSTS_ID_0 = 67,
947
+	AXI_READ_CHANNEL_BURSTS_ID_1 = 68,
948
+	AXI_READ_CHANNEL_BURSTS_ID_2 = 69,
949
+	AXI_READ_CHANNEL_BURSTS_ID_3 = 70,
950
+	AXI_READ_CHANNEL_BURSTS_ID_4 = 71,
951
+	AXI_READ_CHANNEL_BURSTS_ID_5 = 72,
952
+	AXI_READ_CHANNEL_BURSTS_ID_6 = 73,
953
+	AXI_READ_CHANNEL_BURSTS_ID_7 = 74,
954
+	AXI_READ_CHANNEL_TOTAL_BURSTS = 75,
955
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76,
956
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77,
957
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78,
958
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79,
959
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80,
960
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81,
961
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82,
962
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83,
963
+	AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84,
964
+	AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85,
965
+	AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86,
966
+	AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87,
967
+	AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88,
968
+	AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89,
969
+	AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90,
970
+	AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91,
971
+	AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92,
972
+	AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93,
973
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94,
974
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95,
975
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96,
976
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97,
977
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98,
978
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99,
979
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100,
980
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101,
981
+	AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102,
982
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103,
983
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104,
984
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105,
985
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106,
986
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107,
987
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108,
988
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109,
989
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110,
990
+	AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111,
991
+	TOTAL_MMU_MISSES = 112,
992
+	MMU_READ_MISSES = 113,
993
+	MMU_WRITE_MISSES = 114,
994
+	TOTAL_MMU_HITS = 115,
995
+	MMU_READ_HITS = 116,
996
+	MMU_WRITE_HITS = 117,
997
+	SPLIT_MODE_TC_HITS = 118,
998
+	SPLIT_MODE_TC_MISSES = 119,
999
+	SPLIT_MODE_NON_TC_HITS = 120,
1000
+	SPLIT_MODE_NON_TC_MISSES = 121,
1001
+	STALL_AWAITING_TLB_MISS_FETCH = 122,
1002
+	MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123,
1003
+	MMU_TLB_MISS_DATA_BEATS_READ = 124,
1004
+	CP_CYCLES_HELD_OFF = 125,
1005
+	VGT_CYCLES_HELD_OFF = 126,
1006
+	TC_CYCLES_HELD_OFF = 127,
1007
+	TC_ROQ_CYCLES_HELD_OFF = 128,
1008
+	TC_CYCLES_HELD_OFF_TCD_FULL = 129,
1009
+	RB_CYCLES_HELD_OFF = 130,
1010
+	TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131,
1011
+	TLB_MISS_CYCLES_HELD_OFF = 132,
1012
+	AXI_READ_REQUEST_HELD_OFF = 133,
1013
+	AXI_WRITE_REQUEST_HELD_OFF = 134,
1014
+	AXI_REQUEST_HELD_OFF = 135,
1015
+	AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136,
1016
+	AXI_WRITE_DATA_HELD_OFF = 137,
1017
+	CP_SAME_PAGE_BANK_REQUESTS = 138,
1018
+	VGT_SAME_PAGE_BANK_REQUESTS = 139,
1019
+	TC_SAME_PAGE_BANK_REQUESTS = 140,
1020
+	TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141,
1021
+	RB_SAME_PAGE_BANK_REQUESTS = 142,
1022
+	TOTAL_SAME_PAGE_BANK_REQUESTS = 143,
1023
+	CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144,
1024
+	VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145,
1025
+	TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146,
1026
+	RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147,
1027
+	TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148,
1028
+	TOTAL_MH_READ_REQUESTS = 149,
1029
+	TOTAL_MH_WRITE_REQUESTS = 150,
1030
+	TOTAL_MH_REQUESTS = 151,
1031
+	MH_BUSY = 152,
1032
+	CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153,
1033
+	VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154,
1034
+	TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155,
1035
+	RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156,
1036
+	TC_ROQ_N_VALID_ENTRIES = 157,
1037
+	ARQ_N_ENTRIES = 158,
1038
+	WDB_N_ENTRIES = 159,
1039
+	MH_READ_LATENCY_OUTST_REQ_SUM = 160,
1040
+	MC_READ_LATENCY_OUTST_REQ_SUM = 161,
1041
+	MC_TOTAL_READ_REQUESTS = 162,
1042
+	ELAPSED_CYCLES_MH_GATED_CLK = 163,
1043
+	ELAPSED_CLK_CYCLES = 164,
1044
+	CP_W_16B_REQUESTS = 165,
1045
+	CP_W_32B_REQUESTS = 166,
1046
+	TC_16B_REQUESTS = 167,
1047
+	TC_32B_REQUESTS = 168,
1048
+	PA_REQUESTS = 169,
1049
+	PA_DATA_BYTES_WRITTEN = 170,
1050
+	PA_WRITE_CLEAN_RESPONSES = 171,
1051
+	PA_CYCLES_HELD_OFF = 172,
1052
+	AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173,
1053
+	AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174,
1054
+	AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175,
1055
+	AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176,
1056
+	AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177,
1057
+	AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178,
1058
+	AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179,
1059
+	AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180,
1060
+	AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181,
1061
+};
1062
+
2131063 enum adreno_mmu_clnt_beh {
2141064 	BEH_NEVR = 0,
2151065 	BEH_TRAN_RNG = 1,
....@@ -239,7 +1089,63 @@
2391089 enum sq_tex_filter {
2401090 	SQ_TEX_FILTER_POINT = 0,
2411091 	SQ_TEX_FILTER_BILINEAR = 1,
242
-	SQ_TEX_FILTER_BICUBIC = 2,
1092
+	SQ_TEX_FILTER_BASEMAP = 2,
1093
+	SQ_TEX_FILTER_USE_FETCH_CONST = 3,
1094
+};
1095
+
1096
+enum sq_tex_aniso_filter {
1097
+	SQ_TEX_ANISO_FILTER_DISABLED = 0,
1098
+	SQ_TEX_ANISO_FILTER_MAX_1_1 = 1,
1099
+	SQ_TEX_ANISO_FILTER_MAX_2_1 = 2,
1100
+	SQ_TEX_ANISO_FILTER_MAX_4_1 = 3,
1101
+	SQ_TEX_ANISO_FILTER_MAX_8_1 = 4,
1102
+	SQ_TEX_ANISO_FILTER_MAX_16_1 = 5,
1103
+	SQ_TEX_ANISO_FILTER_USE_FETCH_CONST = 7,
1104
+};
1105
+
1106
+enum sq_tex_dimension {
1107
+	SQ_TEX_DIMENSION_1D = 0,
1108
+	SQ_TEX_DIMENSION_2D = 1,
1109
+	SQ_TEX_DIMENSION_3D = 2,
1110
+	SQ_TEX_DIMENSION_CUBE = 3,
1111
+};
1112
+
1113
+enum sq_tex_border_color {
1114
+	SQ_TEX_BORDER_COLOR_BLACK = 0,
1115
+	SQ_TEX_BORDER_COLOR_WHITE = 1,
1116
+	SQ_TEX_BORDER_COLOR_ACBYCR_BLACK = 2,
1117
+	SQ_TEX_BORDER_COLOR_ACBCRY_BLACK = 3,
1118
+};
1119
+
1120
+enum sq_tex_sign {
1121
+	SQ_TEX_SIGN_UNSIGNED = 0,
1122
+	SQ_TEX_SIGN_SIGNED = 1,
1123
+	SQ_TEX_SIGN_UNSIGNED_BIASED = 2,
1124
+	SQ_TEX_SIGN_GAMMA = 3,
1125
+};
1126
+
1127
+enum sq_tex_endian {
1128
+	SQ_TEX_ENDIAN_NONE = 0,
1129
+	SQ_TEX_ENDIAN_8IN16 = 1,
1130
+	SQ_TEX_ENDIAN_8IN32 = 2,
1131
+	SQ_TEX_ENDIAN_16IN32 = 3,
1132
+};
1133
+
1134
+enum sq_tex_clamp_policy {
1135
+	SQ_TEX_CLAMP_POLICY_D3D = 0,
1136
+	SQ_TEX_CLAMP_POLICY_OGL = 1,
1137
+};
1138
+
1139
+enum sq_tex_num_format {
1140
+	SQ_TEX_NUM_FORMAT_FRAC = 0,
1141
+	SQ_TEX_NUM_FORMAT_INT = 1,
1142
+};
1143
+
1144
+enum sq_tex_type {
1145
+	SQ_TEX_TYPE_0 = 0,
1146
+	SQ_TEX_TYPE_1 = 1,
1147
+	SQ_TEX_TYPE_2 = 2,
1148
+	SQ_TEX_TYPE_3 = 3,
2431149 };
2441150 
2451151 #define REG_A2XX_RBBM_PATCH_RELEASE				0x00000001
....@@ -323,6 +1229,18 @@
3231229 }
3241230 
3251231 #define REG_A2XX_MH_MMU_VA_RANGE				0x00000041
1232
+#define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK		0x00000fff
1233
+#define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT		0
1234
+static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val)
1235
+{
1236
+	return ((val) << A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT) & A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK;
1237
+}
1238
+#define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK			0xfffff000
1239
+#define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT			12
1240
+static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val)
1241
+{
1242
+	return ((val) << A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT) & A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK;
1243
+}
3261244 
3271245 #define REG_A2XX_MH_MMU_PT_BASE					0x00000042
3281246 
....@@ -331,6 +1249,8 @@
3311249 #define REG_A2XX_MH_MMU_TRAN_ERROR				0x00000044
3321250 
3331251 #define REG_A2XX_MH_MMU_INVALIDATE				0x00000045
1252
+#define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL			0x00000001
1253
+#define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC			0x00000002
3341254 
3351255 #define REG_A2XX_MH_MMU_MPU_BASE				0x00000046
3361256 
....@@ -389,12 +1309,19 @@
3891309 #define REG_A2XX_RBBM_READ_ERROR				0x000003b3
3901310 
3911311 #define REG_A2XX_RBBM_INT_CNTL					0x000003b4
1312
+#define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK			0x00000001
1313
+#define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK		0x00000002
1314
+#define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK			0x00080000
3921315 
3931316 #define REG_A2XX_RBBM_INT_STATUS				0x000003b5
3941317 
3951318 #define REG_A2XX_RBBM_INT_ACK					0x000003b6
3961319 
3971320 #define REG_A2XX_MASTER_INT_SIGNAL				0x000003b7
1321
+#define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT			0x00000020
1322
+#define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT			0x04000000
1323
+#define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT			0x40000000
1324
+#define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT			0x80000000
3981325 
3991326 #define REG_A2XX_RBBM_PERIPHID1					0x000003f9
4001327 
....@@ -466,6 +1393,19 @@
4661393 #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE			0x01000000
4671394 #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE			0x02000000
4681395 #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE			0x04000000
1396
+
1397
+#define REG_A2XX_MH_INTERRUPT_MASK				0x00000a42
1398
+#define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR			0x00000001
1399
+#define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR			0x00000002
1400
+#define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT			0x00000004
1401
+
1402
+#define REG_A2XX_MH_INTERRUPT_STATUS				0x00000a43
1403
+
1404
+#define REG_A2XX_MH_INTERRUPT_CLEAR				0x00000a44
1405
+
1406
+#define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1			0x00000a54
1407
+
1408
+#define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2			0x00000a55
4691409 
4701410 #define REG_A2XX_A220_VSC_BIN_SIZE				0x00000c01
4711411 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK			0x0000001f
....@@ -648,6 +1588,18 @@
6481588 #define REG_A2XX_RB_DEBUG_DATA					0x00000f27
6491589 
6501590 #define REG_A2XX_RB_SURFACE_INFO				0x00002000
1591
+#define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK		0x00003fff
1592
+#define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT		0
1593
+static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val)
1594
+{
1595
+	return ((val) << A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT) & A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK;
1596
+}
1597
+#define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK			0x0000c000
1598
+#define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT		14
1599
+static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val)
1600
+{
1601
+	return ((val) << A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT) & A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK;
1602
+}
6511603 
6521604 #define REG_A2XX_RB_COLOR_INFO					0x00002001
6531605 #define A2XX_RB_COLOR_INFO_FORMAT__MASK				0x0000000f
....@@ -679,7 +1631,7 @@
6791631 #define A2XX_RB_COLOR_INFO_BASE__SHIFT				12
6801632 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val)
6811633 {
682
-	return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;
1634
+	return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;
6831635 }
6841636 
6851637 #define REG_A2XX_RB_DEPTH_INFO					0x00002002
....@@ -693,7 +1645,7 @@
6931645 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT			12
6941646 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
6951647 {
696
-	return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
1648
+	return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
6971649 }
6981650 
6991651 #define REG_A2XX_A225_RB_COLOR_INFO3				0x00002005
....@@ -1740,6 +2692,10 @@
17402692 
17412693 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE			0x00002380
17422694 
2695
+#define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_OFFSET			0x00002381
2696
+
2697
+#define REG_A2XX_PA_SU_POLY_OFFSET_BACK_SCALE			0x00002382
2698
+
17432699 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET			0x00002383
17442700 
17452701 #define REG_A2XX_SQ_CONSTANT_0					0x00004000
....@@ -1756,7 +2712,251 @@
17562712 
17572713 #define REG_A2XX_COHER_STATUS_PM4				0x00000a2b
17582714 
2715
+#define REG_A2XX_PA_SU_PERFCOUNTER0_SELECT			0x00000c88
2716
+
2717
+#define REG_A2XX_PA_SU_PERFCOUNTER1_SELECT			0x00000c89
2718
+
2719
+#define REG_A2XX_PA_SU_PERFCOUNTER2_SELECT			0x00000c8a
2720
+
2721
+#define REG_A2XX_PA_SU_PERFCOUNTER3_SELECT			0x00000c8b
2722
+
2723
+#define REG_A2XX_PA_SU_PERFCOUNTER0_LOW				0x00000c8c
2724
+
2725
+#define REG_A2XX_PA_SU_PERFCOUNTER0_HI				0x00000c8d
2726
+
2727
+#define REG_A2XX_PA_SU_PERFCOUNTER1_LOW				0x00000c8e
2728
+
2729
+#define REG_A2XX_PA_SU_PERFCOUNTER1_HI				0x00000c8f
2730
+
2731
+#define REG_A2XX_PA_SU_PERFCOUNTER2_LOW				0x00000c90
2732
+
2733
+#define REG_A2XX_PA_SU_PERFCOUNTER2_HI				0x00000c91
2734
+
2735
+#define REG_A2XX_PA_SU_PERFCOUNTER3_LOW				0x00000c92
2736
+
2737
+#define REG_A2XX_PA_SU_PERFCOUNTER3_HI				0x00000c93
2738
+
2739
+#define REG_A2XX_PA_SC_PERFCOUNTER0_SELECT			0x00000c98
2740
+
2741
+#define REG_A2XX_PA_SC_PERFCOUNTER0_LOW				0x00000c99
2742
+
2743
+#define REG_A2XX_PA_SC_PERFCOUNTER0_HI				0x00000c9a
2744
+
2745
+#define REG_A2XX_VGT_PERFCOUNTER0_SELECT			0x00000c48
2746
+
2747
+#define REG_A2XX_VGT_PERFCOUNTER1_SELECT			0x00000c49
2748
+
2749
+#define REG_A2XX_VGT_PERFCOUNTER2_SELECT			0x00000c4a
2750
+
2751
+#define REG_A2XX_VGT_PERFCOUNTER3_SELECT			0x00000c4b
2752
+
2753
+#define REG_A2XX_VGT_PERFCOUNTER0_LOW				0x00000c4c
2754
+
2755
+#define REG_A2XX_VGT_PERFCOUNTER1_LOW				0x00000c4e
2756
+
2757
+#define REG_A2XX_VGT_PERFCOUNTER2_LOW				0x00000c50
2758
+
2759
+#define REG_A2XX_VGT_PERFCOUNTER3_LOW				0x00000c52
2760
+
2761
+#define REG_A2XX_VGT_PERFCOUNTER0_HI				0x00000c4d
2762
+
2763
+#define REG_A2XX_VGT_PERFCOUNTER1_HI				0x00000c4f
2764
+
2765
+#define REG_A2XX_VGT_PERFCOUNTER2_HI				0x00000c51
2766
+
2767
+#define REG_A2XX_VGT_PERFCOUNTER3_HI				0x00000c53
2768
+
2769
+#define REG_A2XX_TCR_PERFCOUNTER0_SELECT			0x00000e05
2770
+
2771
+#define REG_A2XX_TCR_PERFCOUNTER1_SELECT			0x00000e08
2772
+
2773
+#define REG_A2XX_TCR_PERFCOUNTER0_HI				0x00000e06
2774
+
2775
+#define REG_A2XX_TCR_PERFCOUNTER1_HI				0x00000e09
2776
+
2777
+#define REG_A2XX_TCR_PERFCOUNTER0_LOW				0x00000e07
2778
+
2779
+#define REG_A2XX_TCR_PERFCOUNTER1_LOW				0x00000e0a
2780
+
2781
+#define REG_A2XX_TP0_PERFCOUNTER0_SELECT			0x00000e1f
2782
+
2783
+#define REG_A2XX_TP0_PERFCOUNTER0_HI				0x00000e20
2784
+
2785
+#define REG_A2XX_TP0_PERFCOUNTER0_LOW				0x00000e21
2786
+
2787
+#define REG_A2XX_TP0_PERFCOUNTER1_SELECT			0x00000e22
2788
+
2789
+#define REG_A2XX_TP0_PERFCOUNTER1_HI				0x00000e23
2790
+
2791
+#define REG_A2XX_TP0_PERFCOUNTER1_LOW				0x00000e24
2792
+
2793
+#define REG_A2XX_TCM_PERFCOUNTER0_SELECT			0x00000e54
2794
+
2795
+#define REG_A2XX_TCM_PERFCOUNTER1_SELECT			0x00000e57
2796
+
2797
+#define REG_A2XX_TCM_PERFCOUNTER0_HI				0x00000e55
2798
+
2799
+#define REG_A2XX_TCM_PERFCOUNTER1_HI				0x00000e58
2800
+
2801
+#define REG_A2XX_TCM_PERFCOUNTER0_LOW				0x00000e56
2802
+
2803
+#define REG_A2XX_TCM_PERFCOUNTER1_LOW				0x00000e59
2804
+
2805
+#define REG_A2XX_TCF_PERFCOUNTER0_SELECT			0x00000e5a
2806
+
2807
+#define REG_A2XX_TCF_PERFCOUNTER1_SELECT			0x00000e5d
2808
+
2809
+#define REG_A2XX_TCF_PERFCOUNTER2_SELECT			0x00000e60
2810
+
2811
+#define REG_A2XX_TCF_PERFCOUNTER3_SELECT			0x00000e63
2812
+
2813
+#define REG_A2XX_TCF_PERFCOUNTER4_SELECT			0x00000e66
2814
+
2815
+#define REG_A2XX_TCF_PERFCOUNTER5_SELECT			0x00000e69
2816
+
2817
+#define REG_A2XX_TCF_PERFCOUNTER6_SELECT			0x00000e6c
2818
+
2819
+#define REG_A2XX_TCF_PERFCOUNTER7_SELECT			0x00000e6f
2820
+
2821
+#define REG_A2XX_TCF_PERFCOUNTER8_SELECT			0x00000e72
2822
+
2823
+#define REG_A2XX_TCF_PERFCOUNTER9_SELECT			0x00000e75
2824
+
2825
+#define REG_A2XX_TCF_PERFCOUNTER10_SELECT			0x00000e78
2826
+
2827
+#define REG_A2XX_TCF_PERFCOUNTER11_SELECT			0x00000e7b
2828
+
2829
+#define REG_A2XX_TCF_PERFCOUNTER0_HI				0x00000e5b
2830
+
2831
+#define REG_A2XX_TCF_PERFCOUNTER1_HI				0x00000e5e
2832
+
2833
+#define REG_A2XX_TCF_PERFCOUNTER2_HI				0x00000e61
2834
+
2835
+#define REG_A2XX_TCF_PERFCOUNTER3_HI				0x00000e64
2836
+
2837
+#define REG_A2XX_TCF_PERFCOUNTER4_HI				0x00000e67
2838
+
2839
+#define REG_A2XX_TCF_PERFCOUNTER5_HI				0x00000e6a
2840
+
2841
+#define REG_A2XX_TCF_PERFCOUNTER6_HI				0x00000e6d
2842
+
2843
+#define REG_A2XX_TCF_PERFCOUNTER7_HI				0x00000e70
2844
+
2845
+#define REG_A2XX_TCF_PERFCOUNTER8_HI				0x00000e73
2846
+
2847
+#define REG_A2XX_TCF_PERFCOUNTER9_HI				0x00000e76
2848
+
2849
+#define REG_A2XX_TCF_PERFCOUNTER10_HI				0x00000e79
2850
+
2851
+#define REG_A2XX_TCF_PERFCOUNTER11_HI				0x00000e7c
2852
+
2853
+#define REG_A2XX_TCF_PERFCOUNTER0_LOW				0x00000e5c
2854
+
2855
+#define REG_A2XX_TCF_PERFCOUNTER1_LOW				0x00000e5f
2856
+
2857
+#define REG_A2XX_TCF_PERFCOUNTER2_LOW				0x00000e62
2858
+
2859
+#define REG_A2XX_TCF_PERFCOUNTER3_LOW				0x00000e65
2860
+
2861
+#define REG_A2XX_TCF_PERFCOUNTER4_LOW				0x00000e68
2862
+
2863
+#define REG_A2XX_TCF_PERFCOUNTER5_LOW				0x00000e6b
2864
+
2865
+#define REG_A2XX_TCF_PERFCOUNTER6_LOW				0x00000e6e
2866
+
2867
+#define REG_A2XX_TCF_PERFCOUNTER7_LOW				0x00000e71
2868
+
2869
+#define REG_A2XX_TCF_PERFCOUNTER8_LOW				0x00000e74
2870
+
2871
+#define REG_A2XX_TCF_PERFCOUNTER9_LOW				0x00000e77
2872
+
2873
+#define REG_A2XX_TCF_PERFCOUNTER10_LOW				0x00000e7a
2874
+
2875
+#define REG_A2XX_TCF_PERFCOUNTER11_LOW				0x00000e7d
2876
+
2877
+#define REG_A2XX_SQ_PERFCOUNTER0_SELECT				0x00000dc8
2878
+
2879
+#define REG_A2XX_SQ_PERFCOUNTER1_SELECT				0x00000dc9
2880
+
2881
+#define REG_A2XX_SQ_PERFCOUNTER2_SELECT				0x00000dca
2882
+
2883
+#define REG_A2XX_SQ_PERFCOUNTER3_SELECT				0x00000dcb
2884
+
2885
+#define REG_A2XX_SQ_PERFCOUNTER0_LOW				0x00000dcc
2886
+
2887
+#define REG_A2XX_SQ_PERFCOUNTER0_HI				0x00000dcd
2888
+
2889
+#define REG_A2XX_SQ_PERFCOUNTER1_LOW				0x00000dce
2890
+
2891
+#define REG_A2XX_SQ_PERFCOUNTER1_HI				0x00000dcf
2892
+
2893
+#define REG_A2XX_SQ_PERFCOUNTER2_LOW				0x00000dd0
2894
+
2895
+#define REG_A2XX_SQ_PERFCOUNTER2_HI				0x00000dd1
2896
+
2897
+#define REG_A2XX_SQ_PERFCOUNTER3_LOW				0x00000dd2
2898
+
2899
+#define REG_A2XX_SQ_PERFCOUNTER3_HI				0x00000dd3
2900
+
2901
+#define REG_A2XX_SX_PERFCOUNTER0_SELECT				0x00000dd4
2902
+
2903
+#define REG_A2XX_SX_PERFCOUNTER0_LOW				0x00000dd8
2904
+
2905
+#define REG_A2XX_SX_PERFCOUNTER0_HI				0x00000dd9
2906
+
2907
+#define REG_A2XX_MH_PERFCOUNTER0_SELECT				0x00000a46
2908
+
2909
+#define REG_A2XX_MH_PERFCOUNTER1_SELECT				0x00000a4a
2910
+
2911
+#define REG_A2XX_MH_PERFCOUNTER0_CONFIG				0x00000a47
2912
+
2913
+#define REG_A2XX_MH_PERFCOUNTER1_CONFIG				0x00000a4b
2914
+
2915
+#define REG_A2XX_MH_PERFCOUNTER0_LOW				0x00000a48
2916
+
2917
+#define REG_A2XX_MH_PERFCOUNTER1_LOW				0x00000a4c
2918
+
2919
+#define REG_A2XX_MH_PERFCOUNTER0_HI				0x00000a49
2920
+
2921
+#define REG_A2XX_MH_PERFCOUNTER1_HI				0x00000a4d
2922
+
2923
+#define REG_A2XX_RB_PERFCOUNTER0_SELECT				0x00000f04
2924
+
2925
+#define REG_A2XX_RB_PERFCOUNTER0_LOW				0x00000f08
2926
+
2927
+#define REG_A2XX_RB_PERFCOUNTER0_HI				0x00000f09
2928
+
17592929 #define REG_A2XX_SQ_TEX_0					0x00000000
2930
+#define A2XX_SQ_TEX_0_TYPE__MASK				0x00000003
2931
+#define A2XX_SQ_TEX_0_TYPE__SHIFT				0
2932
+static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val)
2933
+{
2934
+	return ((val) << A2XX_SQ_TEX_0_TYPE__SHIFT) & A2XX_SQ_TEX_0_TYPE__MASK;
2935
+}
2936
+#define A2XX_SQ_TEX_0_SIGN_X__MASK				0x0000000c
2937
+#define A2XX_SQ_TEX_0_SIGN_X__SHIFT				2
2938
+static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val)
2939
+{
2940
+	return ((val) << A2XX_SQ_TEX_0_SIGN_X__SHIFT) & A2XX_SQ_TEX_0_SIGN_X__MASK;
2941
+}
2942
+#define A2XX_SQ_TEX_0_SIGN_Y__MASK				0x00000030
2943
+#define A2XX_SQ_TEX_0_SIGN_Y__SHIFT				4
2944
+static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val)
2945
+{
2946
+	return ((val) << A2XX_SQ_TEX_0_SIGN_Y__SHIFT) & A2XX_SQ_TEX_0_SIGN_Y__MASK;
2947
+}
2948
+#define A2XX_SQ_TEX_0_SIGN_Z__MASK				0x000000c0
2949
+#define A2XX_SQ_TEX_0_SIGN_Z__SHIFT				6
2950
+static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val)
2951
+{
2952
+	return ((val) << A2XX_SQ_TEX_0_SIGN_Z__SHIFT) & A2XX_SQ_TEX_0_SIGN_Z__MASK;
2953
+}
2954
+#define A2XX_SQ_TEX_0_SIGN_W__MASK				0x00000300
2955
+#define A2XX_SQ_TEX_0_SIGN_W__SHIFT				8
2956
+static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val)
2957
+{
2958
+	return ((val) << A2XX_SQ_TEX_0_SIGN_W__SHIFT) & A2XX_SQ_TEX_0_SIGN_W__MASK;
2959
+}
17602960 #define A2XX_SQ_TEX_0_CLAMP_X__MASK				0x00001c00
17612961 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT				10
17622962 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val)
....@@ -1775,14 +2975,46 @@
17752975 {
17762976 	return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK;
17772977 }
1778
-#define A2XX_SQ_TEX_0_PITCH__MASK				0xffc00000
2978
+#define A2XX_SQ_TEX_0_PITCH__MASK				0x7fc00000
17792979 #define A2XX_SQ_TEX_0_PITCH__SHIFT				22
17802980 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val)
17812981 {
17822982 	return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK;
17832983 }
2984
+#define A2XX_SQ_TEX_0_TILED					0x80000000
17842985 
17852986 #define REG_A2XX_SQ_TEX_1					0x00000001
2987
+#define A2XX_SQ_TEX_1_FORMAT__MASK				0x0000003f
2988
+#define A2XX_SQ_TEX_1_FORMAT__SHIFT				0
2989
+static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val)
2990
+{
2991
+	return ((val) << A2XX_SQ_TEX_1_FORMAT__SHIFT) & A2XX_SQ_TEX_1_FORMAT__MASK;
2992
+}
2993
+#define A2XX_SQ_TEX_1_ENDIANNESS__MASK				0x000000c0
2994
+#define A2XX_SQ_TEX_1_ENDIANNESS__SHIFT				6
2995
+static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val)
2996
+{
2997
+	return ((val) << A2XX_SQ_TEX_1_ENDIANNESS__SHIFT) & A2XX_SQ_TEX_1_ENDIANNESS__MASK;
2998
+}
2999
+#define A2XX_SQ_TEX_1_REQUEST_SIZE__MASK			0x00000300
3000
+#define A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT			8
3001
+static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val)
3002
+{
3003
+	return ((val) << A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT) & A2XX_SQ_TEX_1_REQUEST_SIZE__MASK;
3004
+}
3005
+#define A2XX_SQ_TEX_1_STACKED					0x00000400
3006
+#define A2XX_SQ_TEX_1_CLAMP_POLICY__MASK			0x00000800
3007
+#define A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT			11
3008
+static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val)
3009
+{
3010
+	return ((val) << A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT) & A2XX_SQ_TEX_1_CLAMP_POLICY__MASK;
3011
+}
3012
+#define A2XX_SQ_TEX_1_BASE_ADDRESS__MASK			0xfffff000
3013
+#define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT			12
3014
+static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val)
3015
+{
3016
+	return ((val >> 12) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK;
3017
+}
17863018 
17873019 #define REG_A2XX_SQ_TEX_2					0x00000002
17883020 #define A2XX_SQ_TEX_2_WIDTH__MASK				0x00001fff
....@@ -1797,8 +3029,20 @@
17973029 {
17983030 	return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK;
17993031 }
3032
+#define A2XX_SQ_TEX_2_DEPTH__MASK				0xfc000000
3033
+#define A2XX_SQ_TEX_2_DEPTH__SHIFT				26
3034
+static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val)
3035
+{
3036
+	return ((val) << A2XX_SQ_TEX_2_DEPTH__SHIFT) & A2XX_SQ_TEX_2_DEPTH__MASK;
3037
+}
18003038 
18013039 #define REG_A2XX_SQ_TEX_3					0x00000003
3040
+#define A2XX_SQ_TEX_3_NUM_FORMAT__MASK				0x00000001
3041
+#define A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT				0
3042
+static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val)
3043
+{
3044
+	return ((val) << A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT) & A2XX_SQ_TEX_3_NUM_FORMAT__MASK;
3045
+}
18023046 #define A2XX_SQ_TEX_3_SWIZ_X__MASK				0x0000000e
18033047 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT				1
18043048 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val)
....@@ -1823,6 +3067,12 @@
18233067 {
18243068 	return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK;
18253069 }
3070
+#define A2XX_SQ_TEX_3_EXP_ADJUST__MASK				0x0007e000
3071
+#define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT				13
3072
+static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(int32_t val)
3073
+{
3074
+	return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK;
3075
+}
18263076 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK			0x00180000
18273077 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT			19
18283078 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val)
....@@ -1835,6 +3085,104 @@
18353085 {
18363086 	return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK;
18373087 }
3088
+#define A2XX_SQ_TEX_3_MIP_FILTER__MASK				0x01800000
3089
+#define A2XX_SQ_TEX_3_MIP_FILTER__SHIFT				23
3090
+static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val)
3091
+{
3092
+	return ((val) << A2XX_SQ_TEX_3_MIP_FILTER__SHIFT) & A2XX_SQ_TEX_3_MIP_FILTER__MASK;
3093
+}
3094
+#define A2XX_SQ_TEX_3_ANISO_FILTER__MASK			0x0e000000
3095
+#define A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT			25
3096
+static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val)
3097
+{
3098
+	return ((val) << A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT) & A2XX_SQ_TEX_3_ANISO_FILTER__MASK;
3099
+}
3100
+#define A2XX_SQ_TEX_3_BORDER_SIZE__MASK				0x80000000
3101
+#define A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT			31
3102
+static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val)
3103
+{
3104
+	return ((val) << A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT) & A2XX_SQ_TEX_3_BORDER_SIZE__MASK;
3105
+}
3106
+
3107
+#define REG_A2XX_SQ_TEX_4					0x00000004
3108
+#define A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK			0x00000001
3109
+#define A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT			0
3110
+static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val)
3111
+{
3112
+	return ((val) << A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK;
3113
+}
3114
+#define A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK			0x00000002
3115
+#define A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT			1
3116
+static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val)
3117
+{
3118
+	return ((val) << A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK;
3119
+}
3120
+#define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK			0x0000003c
3121
+#define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT			2
3122
+static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val)
3123
+{
3124
+	return ((val) << A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK;
3125
+}
3126
+#define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK			0x000003c0
3127
+#define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT			6
3128
+static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val)
3129
+{
3130
+	return ((val) << A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK;
3131
+}
3132
+#define A2XX_SQ_TEX_4_MAX_ANISO_WALK				0x00000400
3133
+#define A2XX_SQ_TEX_4_MIN_ANISO_WALK				0x00000800
3134
+#define A2XX_SQ_TEX_4_LOD_BIAS__MASK				0x003ff000
3135
+#define A2XX_SQ_TEX_4_LOD_BIAS__SHIFT				12
3136
+static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val)
3137
+{
3138
+	return ((((int32_t)(val * 32.0))) << A2XX_SQ_TEX_4_LOD_BIAS__SHIFT) & A2XX_SQ_TEX_4_LOD_BIAS__MASK;
3139
+}
3140
+#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK			0x07c00000
3141
+#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT			22
3142
+static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val)
3143
+{
3144
+	return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK;
3145
+}
3146
+#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK			0xf8000000
3147
+#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT			27
3148
+static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val)
3149
+{
3150
+	return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK;
3151
+}
3152
+
3153
+#define REG_A2XX_SQ_TEX_5					0x00000005
3154
+#define A2XX_SQ_TEX_5_BORDER_COLOR__MASK			0x00000003
3155
+#define A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT			0
3156
+static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val)
3157
+{
3158
+	return ((val) << A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT) & A2XX_SQ_TEX_5_BORDER_COLOR__MASK;
3159
+}
3160
+#define A2XX_SQ_TEX_5_FORCE_BCW_MAX				0x00000004
3161
+#define A2XX_SQ_TEX_5_TRI_CLAMP__MASK				0x00000018
3162
+#define A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT				3
3163
+static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val)
3164
+{
3165
+	return ((val) << A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT) & A2XX_SQ_TEX_5_TRI_CLAMP__MASK;
3166
+}
3167
+#define A2XX_SQ_TEX_5_ANISO_BIAS__MASK				0x000001e0
3168
+#define A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT				5
3169
+static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val)
3170
+{
3171
+	return ((((int32_t)(val * 1.0))) << A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT) & A2XX_SQ_TEX_5_ANISO_BIAS__MASK;
3172
+}
3173
+#define A2XX_SQ_TEX_5_DIMENSION__MASK				0x00000600
3174
+#define A2XX_SQ_TEX_5_DIMENSION__SHIFT				9
3175
+static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val)
3176
+{
3177
+	return ((val) << A2XX_SQ_TEX_5_DIMENSION__SHIFT) & A2XX_SQ_TEX_5_DIMENSION__MASK;
3178
+}
3179
+#define A2XX_SQ_TEX_5_PACKED_MIPS				0x00000800
3180
+#define A2XX_SQ_TEX_5_MIP_ADDRESS__MASK				0xfffff000
3181
+#define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT			12
3182
+static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val)
3183
+{
3184
+	return ((val >> 12) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK;
3185
+}
18383186 
18393187 
18403188 #endif /* A2XX_XML */