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2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920 
 kernel/drivers/gpu/drm/i915/i915_vgpu.c
....@@ -21,7 +21,8 @@
2121  * SOFTWARE.
2222  */
2323 
24
-#include "intel_drv.h"
24
+#include "i915_drv.h"
25
+#include "i915_pvinfo.h"
2526 #include "i915_vgpu.h"
2627 
2728 /**
....@@ -52,38 +53,85 @@
5253  */
5354 
5455 /**
55
- * i915_check_vgpu - detect virtual GPU
56
+ * intel_vgpu_detect - detect virtual GPU
5657  * @dev_priv: i915 device private
5758  *
5859  * This function is called at the initialization stage, to detect whether
5960  * running on a vGPU.
6061  */
61
-void i915_check_vgpu(struct drm_i915_private *dev_priv)
62
+void intel_vgpu_detect(struct drm_i915_private *dev_priv)
6263 {
64
+	struct pci_dev *pdev = dev_priv->drm.pdev;
6365 	u64 magic;
6466 	u16 version_major;
67
+	void __iomem *shared_area;
6568 
6669 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
6770 
68
-	magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
69
-	if (magic != VGT_MAGIC)
71
+	/*
72
+	 * This is called before we setup the main MMIO BAR mappings used via
73
+	 * the uncore structure, so we need to access the BAR directly. Since
74
+	 * we do not support VGT on older gens, return early so we don't have
75
+	 * to consider differently numbered or sized MMIO bars
76
+	 */
77
+	if (INTEL_GEN(dev_priv) < 6)
7078 		return;
7179 
72
-	version_major = __raw_i915_read16(dev_priv, vgtif_reg(version_major));
73
-	if (version_major < VGT_VERSION_MAJOR) {
74
-		DRM_INFO("VGT interface version mismatch!\n");
80
+	shared_area = pci_iomap_range(pdev, 0, VGT_PVINFO_PAGE, VGT_PVINFO_SIZE);
81
+	if (!shared_area) {
82
+		drm_err(&dev_priv->drm,
83
+			"failed to map MMIO bar to check for VGT\n");
7584 		return;
7685 	}
7786 
78
-	dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps));
87
+	magic = readq(shared_area + vgtif_offset(magic));
88
+	if (magic != VGT_MAGIC)
89
+		goto out;
90
+
91
+	version_major = readw(shared_area + vgtif_offset(version_major));
92
+	if (version_major < VGT_VERSION_MAJOR) {
93
+		drm_info(&dev_priv->drm, "VGT interface version mismatch!\n");
94
+		goto out;
95
+	}
96
+
97
+	dev_priv->vgpu.caps = readl(shared_area + vgtif_offset(vgt_caps));
7998 
8099 	dev_priv->vgpu.active = true;
81
-	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
100
+	mutex_init(&dev_priv->vgpu.lock);
101
+	drm_info(&dev_priv->drm, "Virtual GPU for Intel GVT-g detected.\n");
102
+
103
+out:
104
+	pci_iounmap(pdev, shared_area);
82105 }
83106 
84
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
107
+void intel_vgpu_register(struct drm_i915_private *i915)
85108 {
86
-	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
109
+	/*
110
+	 * Notify a valid surface after modesetting, when running inside a VM.
111
+	 */
112
+	if (intel_vgpu_active(i915))
113
+		intel_uncore_write(&i915->uncore, vgtif_reg(display_ready),
114
+				   VGT_DRV_DISPLAY_READY);
115
+}
116
+
117
+bool intel_vgpu_active(struct drm_i915_private *dev_priv)
118
+{
119
+	return dev_priv->vgpu.active;
120
+}
121
+
122
+bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv)
123
+{
124
+	return dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT;
125
+}
126
+
127
+bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
128
+{
129
+	return dev_priv->vgpu.caps & VGT_CAPS_HWSP_EMULATION;
130
+}
131
+
132
+bool intel_vgpu_has_huge_gtt(struct drm_i915_private *dev_priv)
133
+{
134
+	return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT;
87135 }
88136 
89137 struct _balloon_info_ {
....@@ -100,13 +148,15 @@
100148 static void vgt_deballoon_space(struct i915_ggtt *ggtt,
101149 				struct drm_mm_node *node)
102150 {
151
+	struct drm_i915_private *dev_priv = ggtt->vm.i915;
103152 	if (!drm_mm_node_allocated(node))
104153 		return;
105154 
106
-	DRM_DEBUG_DRIVER("deballoon space: range [0x%llx - 0x%llx] %llu KiB.\n",
107
-			 node->start,
108
-			 node->start + node->size,
109
-			 node->size / 1024);
155
+	drm_dbg(&dev_priv->drm,
156
+		"deballoon space: range [0x%llx - 0x%llx] %llu KiB.\n",
157
+		node->start,
158
+		node->start + node->size,
159
+		node->size / 1024);
110160 
111161 	ggtt->vm.reserved -= node->size;
112162 	drm_mm_remove_node(node);
....@@ -114,35 +164,38 @@
114164 
115165 /**
116166  * intel_vgt_deballoon - deballoon reserved graphics address trunks
117
- * @dev_priv: i915 device private data
167
+ * @ggtt: the global GGTT from which we reserved earlier
118168  *
119169  * This function is called to deallocate the ballooned-out graphic memory, when
120170  * driver is unloaded or when ballooning fails.
121171  */
122
-void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
172
+void intel_vgt_deballoon(struct i915_ggtt *ggtt)
123173 {
174
+	struct drm_i915_private *dev_priv = ggtt->vm.i915;
124175 	int i;
125176 
126
-	if (!intel_vgpu_active(dev_priv))
177
+	if (!intel_vgpu_active(ggtt->vm.i915))
127178 		return;
128179 
129
-	DRM_DEBUG("VGT deballoon.\n");
180
+	drm_dbg(&dev_priv->drm, "VGT deballoon.\n");
130181 
131182 	for (i = 0; i < 4; i++)
132
-		vgt_deballoon_space(&dev_priv->ggtt, &bl_info.space[i]);
183
+		vgt_deballoon_space(ggtt, &bl_info.space[i]);
133184 }
134185 
135186 static int vgt_balloon_space(struct i915_ggtt *ggtt,
136187 			     struct drm_mm_node *node,
137188 			     unsigned long start, unsigned long end)
138189 {
190
+	struct drm_i915_private *dev_priv = ggtt->vm.i915;
139191 	unsigned long size = end - start;
140192 	int ret;
141193 
142194 	if (start >= end)
143195 		return -EINVAL;
144196 
145
-	DRM_INFO("balloon space: range [ 0x%lx - 0x%lx ] %lu KiB.\n",
197
+	drm_info(&dev_priv->drm,
198
+		 "balloon space: range [ 0x%lx - 0x%lx ] %lu KiB.\n",
146199 		 start, end, size / 1024);
147200 	ret = i915_gem_gtt_reserve(&ggtt->vm, node,
148201 				   size, start, I915_COLOR_UNEVICTABLE,
....@@ -155,7 +208,7 @@
155208 
156209 /**
157210  * intel_vgt_balloon - balloon out reserved graphics address trunks
158
- * @dev_priv: i915 device private data
211
+ * @ggtt: the global GGTT from which to reserve
159212  *
160213  * This function is called at the initialization stage, to balloon out the
161214  * graphic address space allocated to other vGPUs, by marking these spaces as
....@@ -197,36 +250,43 @@
197250  * Returns:
198251  * zero on success, non-zero if configuration invalid or ballooning failed
199252  */
200
-int intel_vgt_balloon(struct drm_i915_private *dev_priv)
253
+int intel_vgt_balloon(struct i915_ggtt *ggtt)
201254 {
202
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
255
+	struct drm_i915_private *dev_priv = ggtt->vm.i915;
256
+	struct intel_uncore *uncore = &dev_priv->uncore;
203257 	unsigned long ggtt_end = ggtt->vm.total;
204258 
205259 	unsigned long mappable_base, mappable_size, mappable_end;
206260 	unsigned long unmappable_base, unmappable_size, unmappable_end;
207261 	int ret;
208262 
209
-	if (!intel_vgpu_active(dev_priv))
263
+	if (!intel_vgpu_active(ggtt->vm.i915))
210264 		return 0;
211265 
212
-	mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
213
-	mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
214
-	unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
215
-	unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
266
+	mappable_base =
267
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.base));
268
+	mappable_size =
269
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.size));
270
+	unmappable_base =
271
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.base));
272
+	unmappable_size =
273
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.size));
216274 
217275 	mappable_end = mappable_base + mappable_size;
218276 	unmappable_end = unmappable_base + unmappable_size;
219277 
220
-	DRM_INFO("VGT ballooning configuration:\n");
221
-	DRM_INFO("Mappable graphic memory: base 0x%lx size %ldKiB\n",
278
+	drm_info(&dev_priv->drm, "VGT ballooning configuration:\n");
279
+	drm_info(&dev_priv->drm,
280
+		 "Mappable graphic memory: base 0x%lx size %ldKiB\n",
222281 		 mappable_base, mappable_size / 1024);
223
-	DRM_INFO("Unmappable graphic memory: base 0x%lx size %ldKiB\n",
282
+	drm_info(&dev_priv->drm,
283
+		 "Unmappable graphic memory: base 0x%lx size %ldKiB\n",
224284 		 unmappable_base, unmappable_size / 1024);
225285 
226286 	if (mappable_end > ggtt->mappable_end ||
227287 	    unmappable_base < ggtt->mappable_end ||
228288 	    unmappable_end > ggtt_end) {
229
-		DRM_ERROR("Invalid ballooning configuration!\n");
289
+		drm_err(&dev_priv->drm, "Invalid ballooning configuration!\n");
230290 		return -EINVAL;
231291 	}
232292 
....@@ -263,7 +323,7 @@
263323 			goto err_below_mappable;
264324 	}
265325 
266
-	DRM_INFO("VGT balloon successfully\n");
326
+	drm_info(&dev_priv->drm, "VGT balloon successfully\n");
267327 	return 0;
268328 
269329 err_below_mappable:
....@@ -273,6 +333,6 @@
273333 err_upon_mappable:
274334 	vgt_deballoon_space(ggtt, &bl_info.space[2]);
275335 err:
276
-	DRM_ERROR("VGT balloon fail\n");
336
+	drm_err(&dev_priv->drm, "VGT balloon fail\n");
277337 	return ret;
278338 }