~hc/RK356X_SDK_RELEASE.git

..	..	@@ -25,14 +25,17 @@
25	25	#ifndef _I915_REG_H_
26	26	#define _I915_REG_H_
27	27
	28	+#include <linux/bitfield.h>
	29	+#include <linux/bits.h>
	30	+
28	31	/**
29	32	* DOC: The i915 register macro definition style guide
30	33	*
31	34	* Follow the style described here for new macros, and while changing existing
32	35	* macros. Do not mass change existing definitions just to update the style.
33	36	*
34		- * Layout
35		- * ~~~~~~
	37	+ * File Layout
	38	+ * ~~~~~~~~~~~
36	39	*
37	40	* Keep helper macros near the top. For example, _PIPE() and friends.
38	41	*
..	..	@@ -59,15 +62,13 @@
59	62	* significant to least significant bit. Indent the register content macros
60	63	* using two extra spaces between ``#define`` and the macro name.
61	64	*
62		- * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field
63		- * contents so that they are already shifted in place, and can be directly
64		- * OR'd. For convenience, function-like macros may be used to define bit fields,
65		- * but do note that the macros may be needed to read as well as write the
66		- * register contents.
	65	+ * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
	66	+ * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
	67	+ * shifted in place, so they can be directly OR'd together. For convenience,
	68	+ * function-like macros may be used to define bit fields, but do note that the
	69	+ * macros may be needed to read as well as write the register contents.
67	70	*
68		- * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in
69		- * the future, but this is the prevailing style. Do not add ``_BIT`` suffix
70		- * to the name.
	71	+ * Define bits using ``REG_BIT(N)``. Do not add ``_BIT`` suffix to the name.
71	72	*
72	73	* Group the register and its contents together without blank lines, separate
73	74	* from other registers and their contents with one blank line.
..	..	@@ -105,26 +106,87 @@
105	106	* #define _FOO_A 0xf000
106	107	* #define _FOO_B 0xf001
107	108	* #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
108		- * #define FOO_ENABLE (1 << 31)
109		- * #define FOO_MODE_MASK (0xf << 16)
110		- * #define FOO_MODE_SHIFT 16
111		- * #define FOO_MODE_BAR (0 << 16)
112		- * #define FOO_MODE_BAZ (1 << 16)
113		- * #define FOO_MODE_QUX_SNB (2 << 16)
	109	+ * #define FOO_ENABLE REG_BIT(31)
	110	+ * #define FOO_MODE_MASK REG_GENMASK(19, 16)
	111	+ * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
	112	+ * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
	113	+ * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
114	114	*
115	115	* #define BAR _MMIO(0xb000)
116	116	* #define GEN8_BAR _MMIO(0xb888)
117	117	*/
118	118
	119	+/**
	120	+ * REG_BIT() - Prepare a u32 bit value
	121	+ * @__n: 0-based bit number
	122	+ *
	123	+ * Local wrapper for BIT() to force u32, with compile time checks.
	124	+ *
	125	+ * @return: Value with bit @__n set.
	126	+ */
	127	+#define REG_BIT(__n) \
	128	+ ((u32)(BIT(__n) + \
	129	+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
	130	+ ((__n) < 0 \|\| (__n) > 31))))
	131	+
	132	+/**
	133	+ * REG_GENMASK() - Prepare a continuous u32 bitmask
	134	+ * @__high: 0-based high bit
	135	+ * @__low: 0-based low bit
	136	+ *
	137	+ * Local wrapper for GENMASK() to force u32, with compile time checks.
	138	+ *
	139	+ * @return: Continuous bitmask from @__high to @__low, inclusive.
	140	+ */
	141	+#define REG_GENMASK(__high, __low) \
	142	+ ((u32)(GENMASK(__high, __low) + \
	143	+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
	144	+ __is_constexpr(__low) && \
	145	+ ((__low) < 0 \|\| (__high) > 31 \|\| (__low) > (__high)))))
	146	+
	147	+/*
	148	+ * Local integer constant expression version of is_power_of_2().
	149	+ */
	150	+#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
	151	+
	152	+/**
	153	+ * REG_FIELD_PREP() - Prepare a u32 bitfield value
	154	+ * @__mask: shifted mask defining the field's length and position
	155	+ * @__val: value to put in the field
	156	+ *
	157	+ * Local copy of FIELD_PREP() to generate an integer constant expression, force
	158	+ * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
	159	+ *
	160	+ * @return: @__val masked and shifted into the field defined by @__mask.
	161	+ */
	162	+#define REG_FIELD_PREP(__mask, __val) \
	163	+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
	164	+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
	165	+ BUILD_BUG_ON_ZERO((__mask) == 0 \|\| (__mask) > U32_MAX) + \
	166	+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
	167	+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
	168	+
	169	+/**
	170	+ * REG_FIELD_GET() - Extract a u32 bitfield value
	171	+ * @__mask: shifted mask defining the field's length and position
	172	+ * @__val: value to extract the bitfield value from
	173	+ *
	174	+ * Local wrapper for FIELD_GET() to force u32 and for consistency with
	175	+ * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
	176	+ *
	177	+ * @return: Masked and shifted value of the field defined by @__mask in @__val.
	178	+ */
	179	+#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
	180	+
119	181	typedef struct {
120		- uint32_t reg;
	182	+ u32 reg;
121	183	} i915_reg_t;
122	184
123	185	#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
124	186
125	187	#define INVALID_MMIO_REG _MMIO(0)
126	188
127		-static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
	189	+static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
128	190	{
129	191	return reg.reg;
130	192	}
..	..	@@ -138,6 +200,12 @@
138	200	{
139	201	return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
140	202	}
	203	+
	204	+#define VLV_DISPLAY_BASE 0x180000
	205	+#define VLV_MIPI_BASE VLV_DISPLAY_BASE
	206	+#define BXT_MIPI_BASE 0x60000
	207	+
	208	+#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset)
141	209
142	210	/*
143	211	* Given the first two numbers __a and __b of arbitrarily many evenly spaced
..	..	@@ -157,20 +225,39 @@
157	225	/*
158	226	* Named helper wrappers around _PICK_EVEN() and _PICK().
159	227	*/
160		-#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
161		-#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
162		-#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
163		-#define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
164		-#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
165		-#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
166		-#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
167		-#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
168		-#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
169		-#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
170		-#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
171		-#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
172		-#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
173		-#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
	228	+#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
	229	+#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
	230	+#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
	231	+#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
	232	+#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
	233	+
	234	+#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
	235	+#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
	236	+#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
	237	+#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
	238	+#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
	239	+
	240	+#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
	241	+
	242	+#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
	243	+#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
	244	+#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
	245	+#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c))
	246	+
	247	+/*
	248	+ * Device info offset array based helpers for groups of registers with unevenly
	249	+ * spaced base offsets.
	250	+ */
	251	+#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
	252	+ INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
	253	+ DISPLAY_MMIO_BASE(dev_priv))
	254	+#define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
	255	+ INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
	256	+ DISPLAY_MMIO_BASE(dev_priv))
	257	+#define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg))
	258	+#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
	259	+ INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
	260	+ DISPLAY_MMIO_BASE(dev_priv))
174	261
175	262	#define __MASKED_FIELD(mask, value) ((mask) << 16 \| (value))
176	263	#define _MASKED_FIELD(mask, value) ({ \
..	..	@@ -184,29 +271,6 @@
184	271	__MASKED_FIELD(mask, value); })
185	272	#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
186	273	#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
187		-
188		-/* Engine ID */
189		-
190		-#define RCS_HW 0
191		-#define VCS_HW 1
192		-#define BCS_HW 2
193		-#define VECS_HW 3
194		-#define VCS2_HW 4
195		-#define VCS3_HW 6
196		-#define VCS4_HW 7
197		-#define VECS2_HW 12
198		-
199		-/* Engine class */
200		-
201		-#define RENDER_CLASS 0
202		-#define VIDEO_DECODE_CLASS 1
203		-#define VIDEO_ENHANCEMENT_CLASS 2
204		-#define COPY_ENGINE_CLASS 3
205		-#define OTHER_CLASS 4
206		-#define MAX_ENGINE_CLASS 4
207		-
208		-#define OTHER_GTPM_INSTANCE 1
209		-#define MAX_ENGINE_INSTANCE 3
210	274
211	275	/* PCI config space */
212	276
..	..	@@ -330,20 +394,43 @@
330	394	#define GEN11_GRDOM_MEDIA4 (1 << 8)
331	395	#define GEN11_GRDOM_VECS (1 << 13)
332	396	#define GEN11_GRDOM_VECS2 (1 << 14)
	397	+#define GEN11_GRDOM_SFC0 (1 << 17)
	398	+#define GEN11_GRDOM_SFC1 (1 << 18)
333	399
334		-#define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base + 0x228)
335		-#define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base + 0x518)
336		-#define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base + 0x220)
	400	+#define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1))
	401	+#define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance))
	402	+
	403	+#define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C)
	404	+#define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0)
	405	+#define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890)
	406	+#define GEN11_VCS_SFC_USAGE_BIT (1 << 0)
	407	+#define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1)
	408	+
	409	+#define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C)
	410	+#define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0)
	411	+#define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018)
	412	+#define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0)
	413	+#define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
	414	+#define GEN11_VECS_SFC_USAGE_BIT (1 << 0)
	415	+
	416	+#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
	417	+#define GEN12_SFC_DONE_MAX 4
	418	+
	419	+#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
	420	+#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
	421	+#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
337	422	#define PP_DIR_DCLV_2G 0xffffffff
338	423
339		-#define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4)
340		-#define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8)
	424	+#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
	425	+#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
341	426
342	427	#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
343	428	#define GEN8_RPCS_ENABLE (1 << 31)
344	429	#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
345	430	#define GEN8_RPCS_S_CNT_SHIFT 15
346	431	#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
	432	+#define GEN11_RPCS_S_CNT_SHIFT 12
	433	+#define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT)
347	434	#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
348	435	#define GEN8_RPCS_SS_CNT_SHIFT 8
349	436	#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
..	..	@@ -463,7 +550,9 @@
463	550	#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
464	551	#define MI_PREDICATE_SRC1 _MMIO(0x2408)
465	552	#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
466		-
	553	+#define MI_PREDICATE_DATA _MMIO(0x2410)
	554	+#define MI_PREDICATE_RESULT _MMIO(0x2418)
	555	+#define MI_PREDICATE_RESULT_1 _MMIO(0x241c)
467	556	#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
468	557	#define LOWER_SLICE_ENABLED (1 << 0)
469	558	#define LOWER_SLICE_DISABLED (0 << 0)
..	..	@@ -472,6 +561,8 @@
472	561	* Registers used only by the command parser
473	562	*/
474	563	#define BCS_SWCTRL _MMIO(0x22200)
	564	+#define BCS_SRC_Y REG_BIT(0)
	565	+#define BCS_DST_Y REG_BIT(1)
475	566
476	567	/* There are 16 GPR registers */
477	568	#define BCS_GPR(n) _MMIO(0x22600 + (n) * 8)
..	..	@@ -585,6 +676,8 @@
585	676	#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
586	677
587	678	#define GEN8_OASTATUS _MMIO(0x2b08)
	679	+#define GEN8_OASTATUS_TAIL_POINTER_WRAP (1 << 17)
	680	+#define GEN8_OASTATUS_HEAD_POINTER_WRAP (1 << 16)
588	681	#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
589	682	#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
590	683	#define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1)
..	..	@@ -603,6 +696,47 @@
603	696	#define OABUFFER_SIZE_4M (5 << 3)
604	697	#define OABUFFER_SIZE_8M (6 << 3)
605	698	#define OABUFFER_SIZE_16M (7 << 3)
	699	+
	700	+#define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
	701	+
	702	+/* Gen12 OAR unit */
	703	+#define GEN12_OAR_OACONTROL _MMIO(0x2960)
	704	+#define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1
	705	+#define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0)
	706	+
	707	+#define GEN12_OACTXCONTROL _MMIO(0x2360)
	708	+#define GEN12_OAR_OASTATUS _MMIO(0x2968)
	709	+
	710	+/* Gen12 OAG unit */
	711	+#define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)
	712	+#define GEN12_OAG_OAHEADPTR_MASK 0xffffffc0
	713	+#define GEN12_OAG_OATAILPTR _MMIO(0xdb04)
	714	+#define GEN12_OAG_OATAILPTR_MASK 0xffffffc0
	715	+
	716	+#define GEN12_OAG_OABUFFER _MMIO(0xdb08)
	717	+#define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK (0x7)
	718	+#define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3)
	719	+#define GEN12_OAG_OABUFFER_MEMORY_SELECT (1 << 0) /* 0: PPGTT, 1: GGTT */
	720	+
	721	+#define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)
	722	+#define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2
	723	+#define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE (1 << 1)
	724	+#define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME (1 << 0)
	725	+
	726	+#define GEN12_OAG_OACONTROL _MMIO(0xdaf4)
	727	+#define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2
	728	+#define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE (1 << 0)
	729	+
	730	+#define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)
	731	+#define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
	732	+#define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
	733	+#define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
	734	+#define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
	735	+
	736	+#define GEN12_OAG_OASTATUS _MMIO(0xdafc)
	737	+#define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
	738	+#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)
	739	+#define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0)
606	740
607	741	/*
608	742	* Flexible, Aggregate EU Counter Registers.
..	..	@@ -736,7 +870,7 @@
736	870
737	871	#define OAREPORTTRIG1 _MMIO(0x2740)
738	872	#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
739		-#define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
	873	+#define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
740	874
741	875	#define OAREPORTTRIG2 _MMIO(0x2744)
742	876	#define OAREPORTTRIG2_INVERT_A_0 (1 << 0)
..	..	@@ -789,7 +923,7 @@
789	923
790	924	#define OAREPORTTRIG5 _MMIO(0x2750)
791	925	#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
792		-#define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
	926	+#define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
793	927
794	928	#define OAREPORTTRIG6 _MMIO(0x2754)
795	929	#define OAREPORTTRIG6_INVERT_A_0 (1 << 0)
..	..	@@ -840,6 +974,26 @@
840	974	#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
841	975	#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
842	976
	977	+/* Same layout as OASTARTTRIGX */
	978	+#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
	979	+#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
	980	+#define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908)
	981	+#define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c)
	982	+#define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910)
	983	+#define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914)
	984	+#define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918)
	985	+#define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c)
	986	+
	987	+/* Same layout as OAREPORTTRIGX */
	988	+#define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920)
	989	+#define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924)
	990	+#define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928)
	991	+#define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c)
	992	+#define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930)
	993	+#define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934)
	994	+#define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938)
	995	+#define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c)
	996	+
843	997	/* CECX_0 */
844	998	#define OACEC_COMPARE_LESS_OR_EQUAL 6
845	999	#define OACEC_COMPARE_NOT_EQUAL 5
..	..	@@ -855,6 +1009,10 @@
855	1009	#define OACEC_SELECT_NOA (0 << 19)
856	1010	#define OACEC_SELECT_PREV (1 << 19)
857	1011	#define OACEC_SELECT_BOOLEAN (2 << 19)
	1012	+
	1013	+/* 11-bit array 0: pass-through, 1: negated */
	1014	+#define GEN12_OASCEC_NEGATE_MASK 0x7ff
	1015	+#define GEN12_OASCEC_NEGATE_SHIFT 21
858	1016
859	1017	/* CECX_1 */
860	1018	#define OACEC_MASK_MASK 0xffff
..	..	@@ -877,6 +1035,42 @@
877	1035	#define OACEC6_1 _MMIO(0x27a4)
878	1036	#define OACEC7_0 _MMIO(0x27a8)
879	1037	#define OACEC7_1 _MMIO(0x27ac)
	1038	+
	1039	+/* Same layout as CECX_Y */
	1040	+#define GEN12_OAG_CEC0_0 _MMIO(0xd940)
	1041	+#define GEN12_OAG_CEC0_1 _MMIO(0xd944)
	1042	+#define GEN12_OAG_CEC1_0 _MMIO(0xd948)
	1043	+#define GEN12_OAG_CEC1_1 _MMIO(0xd94c)
	1044	+#define GEN12_OAG_CEC2_0 _MMIO(0xd950)
	1045	+#define GEN12_OAG_CEC2_1 _MMIO(0xd954)
	1046	+#define GEN12_OAG_CEC3_0 _MMIO(0xd958)
	1047	+#define GEN12_OAG_CEC3_1 _MMIO(0xd95c)
	1048	+#define GEN12_OAG_CEC4_0 _MMIO(0xd960)
	1049	+#define GEN12_OAG_CEC4_1 _MMIO(0xd964)
	1050	+#define GEN12_OAG_CEC5_0 _MMIO(0xd968)
	1051	+#define GEN12_OAG_CEC5_1 _MMIO(0xd96c)
	1052	+#define GEN12_OAG_CEC6_0 _MMIO(0xd970)
	1053	+#define GEN12_OAG_CEC6_1 _MMIO(0xd974)
	1054	+#define GEN12_OAG_CEC7_0 _MMIO(0xd978)
	1055	+#define GEN12_OAG_CEC7_1 _MMIO(0xd97c)
	1056	+
	1057	+/* Same layout as CECX_Y + negate 11-bit array */
	1058	+#define GEN12_OAG_SCEC0_0 _MMIO(0xdc00)
	1059	+#define GEN12_OAG_SCEC0_1 _MMIO(0xdc04)
	1060	+#define GEN12_OAG_SCEC1_0 _MMIO(0xdc08)
	1061	+#define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c)
	1062	+#define GEN12_OAG_SCEC2_0 _MMIO(0xdc10)
	1063	+#define GEN12_OAG_SCEC2_1 _MMIO(0xdc14)
	1064	+#define GEN12_OAG_SCEC3_0 _MMIO(0xdc18)
	1065	+#define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c)
	1066	+#define GEN12_OAG_SCEC4_0 _MMIO(0xdc20)
	1067	+#define GEN12_OAG_SCEC4_1 _MMIO(0xdc24)
	1068	+#define GEN12_OAG_SCEC5_0 _MMIO(0xdc28)
	1069	+#define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c)
	1070	+#define GEN12_OAG_SCEC6_0 _MMIO(0xdc30)
	1071	+#define GEN12_OAG_SCEC6_1 _MMIO(0xdc34)
	1072	+#define GEN12_OAG_SCEC7_0 _MMIO(0xdc38)
	1073	+#define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c)
880	1074
881	1075	/* OA perf counters */
882	1076	#define OA_PERFCNT1_LO _MMIO(0x91B8)
..	..	@@ -958,11 +1152,16 @@
958	1152	#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
959	1153	#define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
960	1154
	1155	+#define GEN12_OAA_DBG_REG _MMIO(0xdc44)
	1156	+#define GEN12_OAG_OA_PESS _MMIO(0x2b2c)
	1157	+#define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40)
	1158	+
961	1159	#define GDT_CHICKEN_BITS _MMIO(0x9840)
962	1160	#define GT_NOA_ENABLE 0x00000080
963	1161
964	1162	#define NOA_DATA _MMIO(0x986C)
965	1163	#define NOA_WRITE _MMIO(0x9888)
	1164	+#define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
966	1165
967	1166	#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
968	1167	#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
..	..	@@ -1007,7 +1206,32 @@
1007	1206	/* See configdb bunit SB addr map */
1008	1207	#define BUNIT_REG_BISOC 0x11
1009	1208
1010		-#define PUNIT_REG_DSPFREQ 0x36
	1209	+/* PUNIT_REG_SSPM0 /
	1210	+#define _SSPM0_SSC(val) ((val) << 0)
	1211	+#define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
	1212	+#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
	1213	+#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
	1214	+#define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
	1215	+#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
	1216	+#define _SSPM0_SSS(val) ((val) << 24)
	1217	+#define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
	1218	+#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
	1219	+#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
	1220	+#define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
	1221	+#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
	1222	+
	1223	+/* PUNIT_REG_SSPM1 /
	1224	+#define SSPM1_FREQSTAT_SHIFT 24
	1225	+#define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
	1226	+#define SSPM1_FREQGUAR_SHIFT 8
	1227	+#define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
	1228	+#define SSPM1_FREQ_SHIFT 0
	1229	+#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
	1230	+
	1231	+#define PUNIT_REG_VEDSSPM0 0x32
	1232	+#define PUNIT_REG_VEDSSPM1 0x33
	1233	+
	1234	+#define PUNIT_REG_DSPSSPM 0x36
1011	1235	#define DSPFREQSTAT_SHIFT_CHV 24
1012	1236	#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
1013	1237	#define DSPFREQGUAR_SHIFT_CHV 8
..	..	@@ -1032,129 +1256,28 @@
1032	1256	#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
1033	1257	#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
1034	1258
1035		-/*
1036		- * i915_power_well_id:
1037		- *
1038		- * Platform specific IDs used to look up power wells and - except for custom
1039		- * power wells - to define request/status register flag bit positions. As such
1040		- * the set of IDs on a given platform must be unique and except for custom
1041		- * power wells their value must stay fixed.
1042		- */
1043		-enum i915_power_well_id {
1044		- /*
1045		- * I830
1046		- * - custom power well
1047		- */
1048		- I830_DISP_PW_PIPES = 0,
1049		-
1050		- /*
1051		- * VLV/CHV
1052		- * - PUNIT_REG_PWRGT_CTRL (bit: id*2),
1053		- * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8)
1054		- */
1055		- PUNIT_POWER_WELL_RENDER = 0,
1056		- PUNIT_POWER_WELL_MEDIA = 1,
1057		- PUNIT_POWER_WELL_DISP2D = 3,
1058		- PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
1059		- PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
1060		- PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
1061		- PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
1062		- PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
1063		- PUNIT_POWER_WELL_DPIO_RX0 = 10,
1064		- PUNIT_POWER_WELL_DPIO_RX1 = 11,
1065		- PUNIT_POWER_WELL_DPIO_CMN_D = 12,
1066		- /* - custom power well */
1067		- CHV_DISP_PW_PIPE_A, /* 13 */
1068		-
1069		- /*
1070		- * HSW/BDW
1071		- * - _HSW_PWR_WELL_CTL1-4 (status bit: id2, req bit: id2+1)
1072		- */
1073		- HSW_DISP_PW_GLOBAL = 15,
1074		-
1075		- /*
1076		- * GEN9+
1077		- * - _HSW_PWR_WELL_CTL1-4 (status bit: id2, req bit: id2+1)
1078		- */
1079		- SKL_DISP_PW_MISC_IO = 0,
1080		- SKL_DISP_PW_DDI_A_E,
1081		- GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
1082		- CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
1083		- SKL_DISP_PW_DDI_B,
1084		- SKL_DISP_PW_DDI_C,
1085		- SKL_DISP_PW_DDI_D,
1086		- CNL_DISP_PW_DDI_F = 6,
1087		-
1088		- GLK_DISP_PW_AUX_A = 8,
1089		- GLK_DISP_PW_AUX_B,
1090		- GLK_DISP_PW_AUX_C,
1091		- CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
1092		- CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
1093		- CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
1094		- CNL_DISP_PW_AUX_D,
1095		- CNL_DISP_PW_AUX_F,
1096		-
1097		- SKL_DISP_PW_1 = 14,
1098		- SKL_DISP_PW_2,
1099		-
1100		- /* - custom power wells */
1101		- BXT_DPIO_CMN_A,
1102		- BXT_DPIO_CMN_BC,
1103		- GLK_DPIO_CMN_C, /* 18 */
1104		-
1105		- /*
1106		- * GEN11+
1107		- * - _HSW_PWR_WELL_CTL1-4
1108		- * (status bit: (id&15)2, req bit:(id&15)2+1)
1109		- */
1110		- ICL_DISP_PW_1 = 0,
1111		- ICL_DISP_PW_2,
1112		- ICL_DISP_PW_3,
1113		- ICL_DISP_PW_4,
1114		-
1115		- /*
1116		- * - _HSW_PWR_WELL_CTL_AUX1/2/4
1117		- * (status bit: (id&15)2, req bit:(id&15)2+1)
1118		- */
1119		- ICL_DISP_PW_AUX_A = 16,
1120		- ICL_DISP_PW_AUX_B,
1121		- ICL_DISP_PW_AUX_C,
1122		- ICL_DISP_PW_AUX_D,
1123		- ICL_DISP_PW_AUX_E,
1124		- ICL_DISP_PW_AUX_F,
1125		-
1126		- ICL_DISP_PW_AUX_TBT1 = 24,
1127		- ICL_DISP_PW_AUX_TBT2,
1128		- ICL_DISP_PW_AUX_TBT3,
1129		- ICL_DISP_PW_AUX_TBT4,
1130		-
1131		- /*
1132		- * - _HSW_PWR_WELL_CTL_DDI1/2/4
1133		- * (status bit: (id&15)2, req bit:(id&15)2+1)
1134		- */
1135		- ICL_DISP_PW_DDI_A = 32,
1136		- ICL_DISP_PW_DDI_B,
1137		- ICL_DISP_PW_DDI_C,
1138		- ICL_DISP_PW_DDI_D,
1139		- ICL_DISP_PW_DDI_E,
1140		- ICL_DISP_PW_DDI_F, /* 37 */
1141		-
1142		- /*
1143		- * Multiple platforms.
1144		- * Must start following the highest ID of any platform.
1145		- * - custom power wells
1146		- */
1147		- SKL_DISP_PW_DC_OFF = 38,
1148		- I915_DISP_PW_ALWAYS_ON,
1149		-};
	1259	+#define PUNIT_REG_ISPSSPM0 0x39
	1260	+#define PUNIT_REG_ISPSSPM1 0x3a
1150	1261
1151	1262	#define PUNIT_REG_PWRGT_CTRL 0x60
1152	1263	#define PUNIT_REG_PWRGT_STATUS 0x61
1153		-#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
1154		-#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
1155		-#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
1156		-#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
1157		-#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
	1264	+#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
	1265	+#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
	1266	+#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
	1267	+#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
	1268	+#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
	1269	+
	1270	+#define PUNIT_PWGT_IDX_RENDER 0
	1271	+#define PUNIT_PWGT_IDX_MEDIA 1
	1272	+#define PUNIT_PWGT_IDX_DISP2D 3
	1273	+#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
	1274	+#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
	1275	+#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
	1276	+#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
	1277	+#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
	1278	+#define PUNIT_PWGT_IDX_DPIO_RX0 10
	1279	+#define PUNIT_PWGT_IDX_DPIO_RX1 11
	1280	+#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
1158	1281
1159	1282	#define PUNIT_REG_GPU_LFM 0xd3
1160	1283	#define PUNIT_REG_GPU_FREQ_REQ 0xd4
..	..	@@ -1261,7 +1384,6 @@
1261	1384	#define DPIO_CMNRST (1 << 0)
1262	1385
1263	1386	#define DPIO_PHY(pipe) ((pipe) >> 1)
1264		-#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
1265	1387
1266	1388	/*
1267	1389	* Per pipe/PLL DPIO regs
..	..	@@ -1718,35 +1840,6 @@
1718	1840	#define PHY_RESERVED (1 << 7)
1719	1841	#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1720	1842
1721		-#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1722		-#define CL_POWER_DOWN_ENABLE (1 << 4)
1723		-#define SUS_CLOCK_CONFIG (3 << 0)
1724		-
1725		-#define _ICL_PORT_CL_DW5_A 0x162014
1726		-#define _ICL_PORT_CL_DW5_B 0x6C014
1727		-#define ICL_PORT_CL_DW5(port) _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
1728		- _ICL_PORT_CL_DW5_B)
1729		-
1730		-#define _CNL_PORT_CL_DW10_A 0x162028
1731		-#define _ICL_PORT_CL_DW10_B 0x6c028
1732		-#define ICL_PORT_CL_DW10(port) _MMIO_PORT(port, \
1733		- _CNL_PORT_CL_DW10_A, \
1734		- _ICL_PORT_CL_DW10_B)
1735		-#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
1736		-#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
1737		-#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
1738		-#define PWR_UP_ALL_LANES (0x0 << 4)
1739		-#define PWR_DOWN_LN_3_2_1 (0xe << 4)
1740		-#define PWR_DOWN_LN_3_2 (0xc << 4)
1741		-#define PWR_DOWN_LN_3 (0x8 << 4)
1742		-#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
1743		-#define PWR_DOWN_LN_1_0 (0x3 << 4)
1744		-#define PWR_DOWN_LN_1 (0x2 << 4)
1745		-#define PWR_DOWN_LN_3_1 (0xa << 4)
1746		-#define PWR_DOWN_LN_3_1_0 (0xb << 4)
1747		-#define PWR_DOWN_LN_MASK (0xf << 4)
1748		-#define PWR_DOWN_LN_SHIFT 4
1749		-
1750	1843	#define _PORT_CL1CM_DW9_A 0x162024
1751	1844	#define _PORT_CL1CM_DW9_BC 0x6C024
1752	1845	#define IREF0RC_OFFSET_SHIFT 8
..	..	@@ -1758,13 +1851,6 @@
1758	1851	#define IREF1RC_OFFSET_SHIFT 8
1759	1852	#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1760	1853	#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1761		-
1762		-#define _ICL_PORT_CL_DW12_A 0x162030
1763		-#define _ICL_PORT_CL_DW12_B 0x6C030
1764		-#define ICL_LANE_ENABLE_AUX (1 << 0)
1765		-#define ICL_PORT_CL_DW12(port) _MMIO_PORT((port), \
1766		- _ICL_PORT_CL_DW12_A, \
1767		- _ICL_PORT_CL_DW12_B)
1768	1854
1769	1855	#define _PORT_CL1CM_DW28_A 0x162070
1770	1856	#define _PORT_CL1CM_DW28_BC 0x6C070
..	..	@@ -1778,6 +1864,82 @@
1778	1864	#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1779	1865	#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1780	1866
	1867	+/*
	1868	+ * CNL/ICL Port/COMBO-PHY Registers
	1869	+ */
	1870	+#define _ICL_COMBOPHY_A 0x162000
	1871	+#define _ICL_COMBOPHY_B 0x6C000
	1872	+#define _EHL_COMBOPHY_C 0x160000
	1873	+#define _RKL_COMBOPHY_D 0x161000
	1874	+#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
	1875	+ _ICL_COMBOPHY_B, \
	1876	+ _EHL_COMBOPHY_C, \
	1877	+ _RKL_COMBOPHY_D)
	1878	+
	1879	+/* CNL/ICL Port CL_DW registers */
	1880	+#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
	1881	+ 4 * (dw))
	1882	+
	1883	+#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
	1884	+#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
	1885	+#define CL_POWER_DOWN_ENABLE (1 << 4)
	1886	+#define SUS_CLOCK_CONFIG (3 << 0)
	1887	+
	1888	+#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
	1889	+#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
	1890	+#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
	1891	+#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
	1892	+#define PWR_UP_ALL_LANES (0x0 << 4)
	1893	+#define PWR_DOWN_LN_3_2_1 (0xe << 4)
	1894	+#define PWR_DOWN_LN_3_2 (0xc << 4)
	1895	+#define PWR_DOWN_LN_3 (0x8 << 4)
	1896	+#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
	1897	+#define PWR_DOWN_LN_1_0 (0x3 << 4)
	1898	+#define PWR_DOWN_LN_3_1 (0xa << 4)
	1899	+#define PWR_DOWN_LN_3_1_0 (0xb << 4)
	1900	+#define PWR_DOWN_LN_MASK (0xf << 4)
	1901	+#define PWR_DOWN_LN_SHIFT 4
	1902	+#define EDP4K2K_MODE_OVRD_EN (1 << 3)
	1903	+#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
	1904	+
	1905	+#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
	1906	+#define ICL_LANE_ENABLE_AUX (1 << 0)
	1907	+
	1908	+/* CNL/ICL Port COMP_DW registers */
	1909	+#define _ICL_PORT_COMP 0x100
	1910	+#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
	1911	+ _ICL_PORT_COMP + 4 * (dw))
	1912	+
	1913	+#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
	1914	+#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
	1915	+#define COMP_INIT (1 << 31)
	1916	+
	1917	+#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
	1918	+#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
	1919	+
	1920	+#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
	1921	+#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
	1922	+#define PROCESS_INFO_DOT_0 (0 << 26)
	1923	+#define PROCESS_INFO_DOT_1 (1 << 26)
	1924	+#define PROCESS_INFO_DOT_4 (2 << 26)
	1925	+#define PROCESS_INFO_MASK (7 << 26)
	1926	+#define PROCESS_INFO_SHIFT 26
	1927	+#define VOLTAGE_INFO_0_85V (0 << 24)
	1928	+#define VOLTAGE_INFO_0_95V (1 << 24)
	1929	+#define VOLTAGE_INFO_1_05V (2 << 24)
	1930	+#define VOLTAGE_INFO_MASK (3 << 24)
	1931	+#define VOLTAGE_INFO_SHIFT 24
	1932	+
	1933	+#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
	1934	+#define IREFGEN (1 << 24)
	1935	+
	1936	+#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
	1937	+#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
	1938	+
	1939	+#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
	1940	+#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
	1941	+
	1942	+/* CNL/ICL Port PCS registers */
1781	1943	#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
1782	1944	#define _CNL_PORT_PCS_DW1_GRP_B 0x162384
1783	1945	#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
..	..	@@ -1788,15 +1950,14 @@
1788	1950	#define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
1789	1951	#define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
1790	1952	#define _CNL_PORT_PCS_DW1_LN0_F 0x162804
1791		-#define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \
	1953	+#define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \
1792	1954	_CNL_PORT_PCS_DW1_GRP_AE, \
1793	1955	_CNL_PORT_PCS_DW1_GRP_B, \
1794	1956	_CNL_PORT_PCS_DW1_GRP_C, \
1795	1957	_CNL_PORT_PCS_DW1_GRP_D, \
1796	1958	_CNL_PORT_PCS_DW1_GRP_AE, \
1797	1959	_CNL_PORT_PCS_DW1_GRP_F))
1798		-
1799		-#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \
	1960	+#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \
1800	1961	_CNL_PORT_PCS_DW1_LN0_AE, \
1801	1962	_CNL_PORT_PCS_DW1_LN0_B, \
1802	1963	_CNL_PORT_PCS_DW1_LN0_C, \
..	..	@@ -1804,24 +1965,25 @@
1804	1965	_CNL_PORT_PCS_DW1_LN0_AE, \
1805	1966	_CNL_PORT_PCS_DW1_LN0_F))
1806	1967
1807		-#define _ICL_PORT_PCS_DW1_GRP_A 0x162604
1808		-#define _ICL_PORT_PCS_DW1_GRP_B 0x6C604
1809		-#define _ICL_PORT_PCS_DW1_LN0_A 0x162804
1810		-#define _ICL_PORT_PCS_DW1_LN0_B 0x6C804
1811		-#define _ICL_PORT_PCS_DW1_AUX_A 0x162304
1812		-#define _ICL_PORT_PCS_DW1_AUX_B 0x6c304
1813		-#define ICL_PORT_PCS_DW1_GRP(port) _MMIO_PORT(port,\
1814		- _ICL_PORT_PCS_DW1_GRP_A, \
1815		- _ICL_PORT_PCS_DW1_GRP_B)
1816		-#define ICL_PORT_PCS_DW1_LN0(port) _MMIO_PORT(port, \
1817		- _ICL_PORT_PCS_DW1_LN0_A, \
1818		- _ICL_PORT_PCS_DW1_LN0_B)
1819		-#define ICL_PORT_PCS_DW1_AUX(port) _MMIO_PORT(port, \
1820		- _ICL_PORT_PCS_DW1_AUX_A, \
1821		- _ICL_PORT_PCS_DW1_AUX_B)
	1968	+#define _ICL_PORT_PCS_AUX 0x300
	1969	+#define _ICL_PORT_PCS_GRP 0x600
	1970	+#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
	1971	+#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
	1972	+ _ICL_PORT_PCS_AUX + 4 * (dw))
	1973	+#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
	1974	+ _ICL_PORT_PCS_GRP + 4 * (dw))
	1975	+#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
	1976	+ _ICL_PORT_PCS_LN(ln) + 4 * (dw))
	1977	+#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
	1978	+#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
	1979	+#define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
	1980	+#define DCC_MODE_SELECT_MASK (0x3 << 20)
	1981	+#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20)
1822	1982	#define COMMON_KEEPER_EN (1 << 26)
	1983	+#define LATENCY_OPTIM_MASK (0x3 << 2)
	1984	+#define LATENCY_OPTIM_VAL(x) ((x) << 2)
1823	1985
1824		-/* CNL Port TX registers */
	1986	+/* CNL/ICL Port TX registers */
1825	1987	#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
1826	1988	#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
1827	1989	#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
..	..	@@ -1832,7 +1994,7 @@
1832	1994	#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
1833	1995	#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
1834	1996	#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
1835		-#define _CNL_PORT_TX_DW_GRP(port, dw) (_PICK((port), \
	1997	+#define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \
1836	1998	_CNL_PORT_TX_AE_GRP_OFFSET, \
1837	1999	_CNL_PORT_TX_B_GRP_OFFSET, \
1838	2000	_CNL_PORT_TX_B_GRP_OFFSET, \
..	..	@@ -1840,7 +2002,7 @@
1840	2002	_CNL_PORT_TX_AE_GRP_OFFSET, \
1841	2003	_CNL_PORT_TX_F_GRP_OFFSET) + \
1842	2004	4 * (dw))
1843		-#define _CNL_PORT_TX_DW_LN0(port, dw) (_PICK((port), \
	2005	+#define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \
1844	2006	_CNL_PORT_TX_AE_LN0_OFFSET, \
1845	2007	_CNL_PORT_TX_B_LN0_OFFSET, \
1846	2008	_CNL_PORT_TX_B_LN0_OFFSET, \
..	..	@@ -1849,23 +2011,22 @@
1849	2011	_CNL_PORT_TX_F_LN0_OFFSET) + \
1850	2012	4 * (dw))
1851	2013
1852		-#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
1853		-#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
1854		-#define _ICL_PORT_TX_DW2_GRP_A 0x162688
1855		-#define _ICL_PORT_TX_DW2_GRP_B 0x6C688
1856		-#define _ICL_PORT_TX_DW2_LN0_A 0x162888
1857		-#define _ICL_PORT_TX_DW2_LN0_B 0x6C888
1858		-#define _ICL_PORT_TX_DW2_AUX_A 0x162388
1859		-#define _ICL_PORT_TX_DW2_AUX_B 0x6c388
1860		-#define ICL_PORT_TX_DW2_GRP(port) _MMIO_PORT(port, \
1861		- _ICL_PORT_TX_DW2_GRP_A, \
1862		- _ICL_PORT_TX_DW2_GRP_B)
1863		-#define ICL_PORT_TX_DW2_LN0(port) _MMIO_PORT(port, \
1864		- _ICL_PORT_TX_DW2_LN0_A, \
1865		- _ICL_PORT_TX_DW2_LN0_B)
1866		-#define ICL_PORT_TX_DW2_AUX(port) _MMIO_PORT(port, \
1867		- _ICL_PORT_TX_DW2_AUX_A, \
1868		- _ICL_PORT_TX_DW2_AUX_B)
	2014	+#define _ICL_PORT_TX_AUX 0x380
	2015	+#define _ICL_PORT_TX_GRP 0x680
	2016	+#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
	2017	+
	2018	+#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
	2019	+ _ICL_PORT_TX_AUX + 4 * (dw))
	2020	+#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
	2021	+ _ICL_PORT_TX_GRP + 4 * (dw))
	2022	+#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
	2023	+ _ICL_PORT_TX_LN(ln) + 4 * (dw))
	2024	+
	2025	+#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
	2026	+#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
	2027	+#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
	2028	+#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
	2029	+#define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
1869	2030	#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
1870	2031	#define SWING_SEL_UPPER_MASK (1 << 15)
1871	2032	#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
..	..	@@ -1877,29 +2038,15 @@
1877	2038
1878	2039	#define _CNL_PORT_TX_DW4_LN0_AE 0x162450
1879	2040	#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
1880		-#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4))
1881		-#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4))
1882		-#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
	2041	+#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
	2042	+#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
	2043	+#define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
1883	2044	((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
1884	2045	_CNL_PORT_TX_DW4_LN0_AE)))
1885		-#define _ICL_PORT_TX_DW4_GRP_A 0x162690
1886		-#define _ICL_PORT_TX_DW4_GRP_B 0x6C690
1887		-#define _ICL_PORT_TX_DW4_LN0_A 0x162890
1888		-#define _ICL_PORT_TX_DW4_LN1_A 0x162990
1889		-#define _ICL_PORT_TX_DW4_LN0_B 0x6C890
1890		-#define _ICL_PORT_TX_DW4_AUX_A 0x162390
1891		-#define _ICL_PORT_TX_DW4_AUX_B 0x6c390
1892		-#define ICL_PORT_TX_DW4_GRP(port) _MMIO_PORT(port, \
1893		- _ICL_PORT_TX_DW4_GRP_A, \
1894		- _ICL_PORT_TX_DW4_GRP_B)
1895		-#define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_PORT(port, \
1896		- _ICL_PORT_TX_DW4_LN0_A, \
1897		- _ICL_PORT_TX_DW4_LN0_B) + \
1898		- ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
1899		- _ICL_PORT_TX_DW4_LN0_A)))
1900		-#define ICL_PORT_TX_DW4_AUX(port) _MMIO_PORT(port, \
1901		- _ICL_PORT_TX_DW4_AUX_A, \
1902		- _ICL_PORT_TX_DW4_AUX_B)
	2046	+#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
	2047	+#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
	2048	+#define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
	2049	+#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
1903	2050	#define LOADGEN_SELECT (1 << 31)
1904	2051	#define POST_CURSOR_1(x) ((x) << 12)
1905	2052	#define POST_CURSOR_1_MASK (0x3F << 12)
..	..	@@ -1908,23 +2055,11 @@
1908	2055	#define CURSOR_COEFF(x) ((x) << 0)
1909	2056	#define CURSOR_COEFF_MASK (0x3F << 0)
1910	2057
1911		-#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 5))
1912		-#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 5))
1913		-#define _ICL_PORT_TX_DW5_GRP_A 0x162694
1914		-#define _ICL_PORT_TX_DW5_GRP_B 0x6C694
1915		-#define _ICL_PORT_TX_DW5_LN0_A 0x162894
1916		-#define _ICL_PORT_TX_DW5_LN0_B 0x6C894
1917		-#define _ICL_PORT_TX_DW5_AUX_A 0x162394
1918		-#define _ICL_PORT_TX_DW5_AUX_B 0x6c394
1919		-#define ICL_PORT_TX_DW5_GRP(port) _MMIO_PORT(port, \
1920		- _ICL_PORT_TX_DW5_GRP_A, \
1921		- _ICL_PORT_TX_DW5_GRP_B)
1922		-#define ICL_PORT_TX_DW5_LN0(port) _MMIO_PORT(port, \
1923		- _ICL_PORT_TX_DW5_LN0_A, \
1924		- _ICL_PORT_TX_DW5_LN0_B)
1925		-#define ICL_PORT_TX_DW5_AUX(port) _MMIO_PORT(port, \
1926		- _ICL_PORT_TX_DW5_AUX_A, \
1927		- _ICL_PORT_TX_DW5_AUX_B)
	2058	+#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
	2059	+#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
	2060	+#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
	2061	+#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
	2062	+#define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
1928	2063	#define TX_TRAINING_EN (1 << 31)
1929	2064	#define TAP2_DISABLE (1 << 30)
1930	2065	#define TAP3_DISABLE (1 << 29)
..	..	@@ -1933,126 +2068,200 @@
1933	2068	#define RTERM_SELECT(x) ((x) << 3)
1934	2069	#define RTERM_SELECT_MASK (0x7 << 3)
1935	2070
1936		-#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
1937		-#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
	2071	+#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
	2072	+#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
	2073	+#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
	2074	+#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
	2075	+#define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
	2076	+#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
1938	2077	#define N_SCALAR(x) ((x) << 24)
1939	2078	#define N_SCALAR_MASK (0x7F << 24)
1940	2079
1941		-#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
1942		- _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
	2080	+#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
	2081	+#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
	2082	+#define ICL_PORT_TX_DW8_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(8, 0, phy))
	2083	+#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
	2084	+#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
	2085	+#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
1943	2086
1944		-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
1945		-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
1946		-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
1947		-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
1948		-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
1949		-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
1950		-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
1951		-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
1952		-#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
1953		- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
1954		- _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
1955		- _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1)
	2087	+#define _ICL_DPHY_CHKN_REG 0x194
	2088	+#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
	2089	+#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
1956	2090
1957		-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
1958		-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
1959		-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
1960		-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
1961		-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
1962		-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
1963		-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
1964		-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
1965		-#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
1966		- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
1967		- _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
1968		- _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1)
1969		-#define CRI_USE_FS32 (1 << 5)
	2091	+#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
	2092	+ _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
1970	2093
1971		-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
1972		-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
1973		-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
1974		-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
1975		-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
1976		-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
1977		-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
1978		-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
1979		-#define ICL_PORT_MG_TX1_PISO_READLOAD(port, ln) \
1980		- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
1981		- _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
1982		- _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1)
	2094	+#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
	2095	+#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
	2096	+#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
	2097	+#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
	2098	+#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
	2099	+#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
	2100	+#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
	2101	+#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
	2102	+#define MG_TX1_LINK_PARAMS(ln, tc_port) \
	2103	+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
	2104	+ MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
	2105	+ MG_TX_LINK_PARAMS_TX1LN1_PORT1)
1983	2106
1984		-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
1985		-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
1986		-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
1987		-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
1988		-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
1989		-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
1990		-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
1991		-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
1992		-#define ICL_PORT_MG_TX2_PISO_READLOAD(port, ln) \
1993		- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
1994		- _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
1995		- _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1)
1996		-#define CRI_CALCINIT (1 << 1)
	2107	+#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
	2108	+#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
	2109	+#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
	2110	+#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
	2111	+#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
	2112	+#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
	2113	+#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
	2114	+#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
	2115	+#define MG_TX2_LINK_PARAMS(ln, tc_port) \
	2116	+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
	2117	+ MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
	2118	+ MG_TX_LINK_PARAMS_TX2LN1_PORT1)
	2119	+#define CRI_USE_FS32 (1 << 5)
1997	2120
1998		-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
1999		-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
2000		-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
2001		-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
2002		-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
2003		-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
2004		-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
2005		-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
2006		-#define ICL_PORT_MG_TX1_SWINGCTRL(port, ln) \
2007		- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1, \
2008		- _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2, \
2009		- _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1)
	2121	+#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
	2122	+#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
	2123	+#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
	2124	+#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
	2125	+#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
	2126	+#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
	2127	+#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
	2128	+#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
	2129	+#define MG_TX1_PISO_READLOAD(ln, tc_port) \
	2130	+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
	2131	+ MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
	2132	+ MG_TX_PISO_READLOAD_TX1LN1_PORT1)
2010	2133
2011		-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
2012		-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
2013		-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
2014		-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
2015		-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
2016		-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
2017		-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
2018		-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
2019		-#define ICL_PORT_MG_TX2_SWINGCTRL(port, ln) \
2020		- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1, \
2021		- _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2, \
2022		- _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1)
2023		-#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
2024		-#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
	2134	+#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
	2135	+#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
	2136	+#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
	2137	+#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
	2138	+#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
	2139	+#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
	2140	+#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
	2141	+#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
	2142	+#define MG_TX2_PISO_READLOAD(ln, tc_port) \
	2143	+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
	2144	+ MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
	2145	+ MG_TX_PISO_READLOAD_TX2LN1_PORT1)
	2146	+#define CRI_CALCINIT (1 << 1)
2025	2147
2026		-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1 0x168144
2027		-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1 0x168544
2028		-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2 0x169144
2029		-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT2 0x169544
2030		-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT3 0x16A144
2031		-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT3 0x16A544
2032		-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT4 0x16B144
2033		-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT4 0x16B544
2034		-#define ICL_PORT_MG_TX1_DRVCTRL(port, ln) \
2035		- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1, \
2036		- _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2, \
2037		- _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1)
	2148	+#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
	2149	+#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
	2150	+#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
	2151	+#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
	2152	+#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
	2153	+#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
	2154	+#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
	2155	+#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
	2156	+#define MG_TX1_SWINGCTRL(ln, tc_port) \
	2157	+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
	2158	+ MG_TX_SWINGCTRL_TX1LN0_PORT2, \
	2159	+ MG_TX_SWINGCTRL_TX1LN1_PORT1)
2038	2160
2039		-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
2040		-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
2041		-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
2042		-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
2043		-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
2044		-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
2045		-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
2046		-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
2047		-#define ICL_PORT_MG_TX2_DRVCTRL(port, ln) \
2048		- _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1, \
2049		- _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2, \
2050		- _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1)
2051		-#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
2052		-#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
2053		-#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
2054		-#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
2055		-#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
	2161	+#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
	2162	+#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
	2163	+#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
	2164	+#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
	2165	+#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
	2166	+#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
	2167	+#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
	2168	+#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
	2169	+#define MG_TX2_SWINGCTRL(ln, tc_port) \
	2170	+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
	2171	+ MG_TX_SWINGCTRL_TX2LN0_PORT2, \
	2172	+ MG_TX_SWINGCTRL_TX2LN1_PORT1)
	2173	+#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
	2174	+#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
	2175	+
	2176	+#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
	2177	+#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
	2178	+#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
	2179	+#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
	2180	+#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
	2181	+#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
	2182	+#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
	2183	+#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
	2184	+#define MG_TX1_DRVCTRL(ln, tc_port) \
	2185	+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
	2186	+ MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
	2187	+ MG_TX_DRVCTRL_TX1LN1_TXPORT1)
	2188	+
	2189	+#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
	2190	+#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
	2191	+#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
	2192	+#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
	2193	+#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
	2194	+#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
	2195	+#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
	2196	+#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
	2197	+#define MG_TX2_DRVCTRL(ln, tc_port) \
	2198	+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
	2199	+ MG_TX_DRVCTRL_TX2LN0_PORT2, \
	2200	+ MG_TX_DRVCTRL_TX2LN1_PORT1)
	2201	+#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
	2202	+#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
	2203	+#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
	2204	+#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
	2205	+#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
	2206	+#define CRI_LOADGEN_SEL(x) ((x) << 12)
	2207	+#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
	2208	+
	2209	+#define MG_CLKHUB_LN0_PORT1 0x16839C
	2210	+#define MG_CLKHUB_LN1_PORT1 0x16879C
	2211	+#define MG_CLKHUB_LN0_PORT2 0x16939C
	2212	+#define MG_CLKHUB_LN1_PORT2 0x16979C
	2213	+#define MG_CLKHUB_LN0_PORT3 0x16A39C
	2214	+#define MG_CLKHUB_LN1_PORT3 0x16A79C
	2215	+#define MG_CLKHUB_LN0_PORT4 0x16B39C
	2216	+#define MG_CLKHUB_LN1_PORT4 0x16B79C
	2217	+#define MG_CLKHUB(ln, tc_port) \
	2218	+ MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
	2219	+ MG_CLKHUB_LN0_PORT2, \
	2220	+ MG_CLKHUB_LN1_PORT1)
	2221	+#define CFG_LOW_RATE_LKREN_EN (1 << 11)
	2222	+
	2223	+#define MG_TX_DCC_TX1LN0_PORT1 0x168110
	2224	+#define MG_TX_DCC_TX1LN1_PORT1 0x168510
	2225	+#define MG_TX_DCC_TX1LN0_PORT2 0x169110
	2226	+#define MG_TX_DCC_TX1LN1_PORT2 0x169510
	2227	+#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
	2228	+#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
	2229	+#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
	2230	+#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
	2231	+#define MG_TX1_DCC(ln, tc_port) \
	2232	+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
	2233	+ MG_TX_DCC_TX1LN0_PORT2, \
	2234	+ MG_TX_DCC_TX1LN1_PORT1)
	2235	+#define MG_TX_DCC_TX2LN0_PORT1 0x168090
	2236	+#define MG_TX_DCC_TX2LN1_PORT1 0x168490
	2237	+#define MG_TX_DCC_TX2LN0_PORT2 0x169090
	2238	+#define MG_TX_DCC_TX2LN1_PORT2 0x169490
	2239	+#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
	2240	+#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
	2241	+#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
	2242	+#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
	2243	+#define MG_TX2_DCC(ln, tc_port) \
	2244	+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
	2245	+ MG_TX_DCC_TX2LN0_PORT2, \
	2246	+ MG_TX_DCC_TX2LN1_PORT1)
	2247	+#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
	2248	+#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
	2249	+#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
	2250	+
	2251	+#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
	2252	+#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
	2253	+#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
	2254	+#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
	2255	+#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
	2256	+#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
	2257	+#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
	2258	+#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
	2259	+#define MG_DP_MODE(ln, tc_port) \
	2260	+ MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
	2261	+ MG_DP_MODE_LN0_ACU_PORT2, \
	2262	+ MG_DP_MODE_LN1_ACU_PORT1)
	2263	+#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
	2264	+#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
2056	2265
2057	2266	/* The spec defines this only for BXT PHY0, but lets assume that this
2058	2267	* would exist for PHY1 too if it had a second channel.
..	..	@@ -2062,53 +2271,20 @@
2062	2271	#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2063	2272	#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
2064	2273
2065		-#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
2066		-#define COMP_INIT (1 << 31)
2067		-#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
2068		-#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
2069		-#define PROCESS_INFO_DOT_0 (0 << 26)
2070		-#define PROCESS_INFO_DOT_1 (1 << 26)
2071		-#define PROCESS_INFO_DOT_4 (2 << 26)
2072		-#define PROCESS_INFO_MASK (7 << 26)
2073		-#define PROCESS_INFO_SHIFT 26
2074		-#define VOLTAGE_INFO_0_85V (0 << 24)
2075		-#define VOLTAGE_INFO_0_95V (1 << 24)
2076		-#define VOLTAGE_INFO_1_05V (2 << 24)
2077		-#define VOLTAGE_INFO_MASK (3 << 24)
2078		-#define VOLTAGE_INFO_SHIFT 24
2079		-#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
2080		-#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
2081		-
2082		-#define _ICL_PORT_COMP_DW0_A 0x162100
2083		-#define _ICL_PORT_COMP_DW0_B 0x6C100
2084		-#define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
2085		- _ICL_PORT_COMP_DW0_B)
2086		-#define _ICL_PORT_COMP_DW1_A 0x162104
2087		-#define _ICL_PORT_COMP_DW1_B 0x6C104
2088		-#define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
2089		- _ICL_PORT_COMP_DW1_B)
2090		-#define _ICL_PORT_COMP_DW3_A 0x16210C
2091		-#define _ICL_PORT_COMP_DW3_B 0x6C10C
2092		-#define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
2093		- _ICL_PORT_COMP_DW3_B)
2094		-#define _ICL_PORT_COMP_DW9_A 0x162124
2095		-#define _ICL_PORT_COMP_DW9_B 0x6C124
2096		-#define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
2097		- _ICL_PORT_COMP_DW9_B)
2098		-#define _ICL_PORT_COMP_DW10_A 0x162128
2099		-#define _ICL_PORT_COMP_DW10_B 0x6C128
2100		-#define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
2101		- _ICL_PORT_COMP_DW10_A, \
2102		- _ICL_PORT_COMP_DW10_B)
	2274	+#define FIA1_BASE 0x163000
	2275	+#define FIA2_BASE 0x16E000
	2276	+#define FIA3_BASE 0x16F000
	2277	+#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
	2278	+#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
2103	2279
2104	2280	/* ICL PHY DFLEX registers */
2105		-#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
2106		-#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
2107		-#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
2108		-#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
2109		-#define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
2110		-#define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port)))
2111		-#define DFLEXDPMLE1_DPMLETC_ML3_0(tc_port) (15 << (4 * (tc_port)))
	2281	+#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
	2282	+#define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))
	2283	+#define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))
	2284	+#define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))
	2285	+#define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))
	2286	+#define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))
	2287	+#define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))
2112	2288
2113	2289	/* BXT PHY Ref registers */
2114	2290	#define _PORT_REF_DW3_A 0x16218C
..	..	@@ -2355,8 +2531,10 @@
2355	2531	#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
2356	2532	#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
2357	2533	#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
2358		-#define RESET_CTL_REQUEST_RESET (1 << 0)
2359		-#define RESET_CTL_READY_TO_RESET (1 << 1)
	2534	+#define RESET_CTL_CAT_ERROR REG_BIT(2)
	2535	+#define RESET_CTL_READY_TO_RESET REG_BIT(1)
	2536	+#define RESET_CTL_REQUEST_RESET REG_BIT(0)
	2537	+
2360	2538	#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
2361	2539
2362	2540	#define HSW_GTT_CACHE_EN _MMIO(0x4024)
..	..	@@ -2380,16 +2558,27 @@
2380	2558	#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
2381	2559	#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
2382	2560	#define GEN8_RING_FAULT_REG _MMIO(0x4094)
	2561	+#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
2383	2562	#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
2384	2563	#define RING_FAULT_GTTSEL_MASK (1 << 11)
2385	2564	#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
2386	2565	#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2387	2566	#define RING_FAULT_VALID (1 << 0)
2388	2567	#define DONE_REG _MMIO(0x40b0)
	2568	+#define GEN12_GAM_DONE _MMIO(0xcf68)
2389	2569	#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
2390	2570	#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
2391	2571	#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
	2572	+#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
2392	2573	#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
	2574	+#define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208)
	2575	+#define GEN12_VD0_AUX_NV _MMIO(0x4218)
	2576	+#define GEN12_VD1_AUX_NV _MMIO(0x4228)
	2577	+#define GEN12_VD2_AUX_NV _MMIO(0x4298)
	2578	+#define GEN12_VD3_AUX_NV _MMIO(0x42A8)
	2579	+#define GEN12_VE0_AUX_NV _MMIO(0x4238)
	2580	+#define GEN12_VE1_AUX_NV _MMIO(0x42B8)
	2581	+#define AUX_INV REG_BIT(0)
2393	2582	#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
2394	2583	#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
2395	2584	#define RING_ACTHD(base) _MMIO((base) + 0x74)
..	..	@@ -2415,7 +2604,25 @@
2415	2604	#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
2416	2605	#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
2417	2606
	2607	+/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
	2608	+#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
	2609	+#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
	2610	+
2418	2611	#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
	2612	+#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
	2613	+#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
	2614	+#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
	2615	+#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
	2616	+#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
	2617	+#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
	2618	+#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
	2619	+#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
	2620	+#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
	2621	+#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
	2622	+#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
	2623	+#define RING_FORCE_TO_NONPRIV_MASK_VALID \
	2624	+ (RING_FORCE_TO_NONPRIV_RANGE_MASK \
	2625	+ \| RING_FORCE_TO_NONPRIV_ACCESS_MASK)
2419	2626	#define RING_MAX_NONPRIV_SLOTS 12
2420	2627
2421	2628	#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
..	..	@@ -2425,6 +2632,7 @@
2425	2632
2426	2633	#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2427	2634	#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
	2635	+#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
2428	2636
2429	2637	#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
2430	2638	#define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31)
..	..	@@ -2450,6 +2658,8 @@
2450	2658	#define IPEIR_I965 _MMIO(0x2064)
2451	2659	#define IPEHR_I965 _MMIO(0x2068)
2452	2660	#define GEN7_SC_INSTDONE _MMIO(0x7100)
	2661	+#define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104)
	2662	+#define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)
2453	2663	#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
2454	2664	#define GEN7_ROW_INSTDONE _MMIO(0xe164)
2455	2665	#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
..	..	@@ -2463,6 +2673,9 @@
2463	2673	#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
2464	2674	#define RING_IPEIR(base) _MMIO((base) + 0x64)
2465	2675	#define RING_IPEHR(base) _MMIO((base) + 0x68)
	2676	+#define RING_EIR(base) _MMIO((base) + 0xb0)
	2677	+#define RING_EMR(base) _MMIO((base) + 0xb4)
	2678	+#define RING_ESR(base) _MMIO((base) + 0xb8)
2466	2679	/*
2467	2680	* On GEN4, only the render ring INSTDONE exists and has a different
2468	2681	* layout than the GEN7+ version.
..	..	@@ -2474,6 +2687,7 @@
2474	2687	#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
2475	2688	#define RING_INSTPM(base) _MMIO((base) + 0xc0)
2476	2689	#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
	2690	+#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
2477	2691	#define INSTPS _MMIO(0x2070) /* 965+ only */
2478	2692	#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2479	2693	#define ACTHD_I965 _MMIO(0x2074)
..	..	@@ -2482,12 +2696,12 @@
2482	2696	#define HWS_START_ADDRESS_SHIFT 4
2483	2697	#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
2484	2698	#define PWRCTX_EN (1 << 0)
2485		-#define IPEIR _MMIO(0x2088)
2486		-#define IPEHR _MMIO(0x208c)
	2699	+#define IPEIR(base) _MMIO((base) + 0x88)
	2700	+#define IPEHR(base) _MMIO((base) + 0x8c)
2487	2701	#define GEN2_INSTDONE _MMIO(0x2090)
2488	2702	#define NOPID _MMIO(0x2094)
2489	2703	#define HWSTAM _MMIO(0x2098)
2490		-#define DMA_FADD_I8XX _MMIO(0x20d0)
	2704	+#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
2491	2705	#define RING_BBSTATE(base) _MMIO((base) + 0x110)
2492	2706	#define RING_BB_PPGTT (1 << 5)
2493	2707	#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
..	..	@@ -2515,8 +2729,17 @@
2515	2729
2516	2730	#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
2517	2731	#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
	2732	+#define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
	2733	+#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
2518	2734	#define FAULT_VA_HIGH_BITS (0xf << 0)
2519	2735	#define FAULT_GTT_SEL (1 << 4)
	2736	+
	2737	+#define GEN12_GFX_TLB_INV_CR _MMIO(0xced8)
	2738	+#define GEN12_VD_TLB_INV_CR _MMIO(0xcedc)
	2739	+#define GEN12_VE_TLB_INV_CR _MMIO(0xcee0)
	2740	+#define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4)
	2741	+
	2742	+#define GEN12_AUX_ERR_DBG _MMIO(0x43f4)
2520	2743
2521	2744	#define FPGA_DBG _MMIO(0x42300)
2522	2745	#define FPGA_DBG_RM_NOCLAIM (1 << 31)
..	..	@@ -2591,6 +2814,7 @@
2591	2814	/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2592	2815	#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2593	2816	#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
	2817	+#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
2594	2818
2595	2819	/* WaClearTdlStateAckDirtyBits */
2596	2820	#define GEN8_STATE_ACK _MMIO(0x20F0)
..	..	@@ -2606,7 +2830,7 @@
2606	2830
2607	2831	#define GFX_MODE _MMIO(0x2520)
2608	2832	#define GFX_MODE_GEN7 _MMIO(0x229c)
2609		-#define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base + 0x29c)
	2833	+#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
2610	2834	#define GFX_RUN_LIST_ENABLE (1 << 15)
2611	2835	#define GFX_INTERRUPT_STEERING (1 << 14)
2612	2836	#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
..	..	@@ -2623,17 +2847,15 @@
2623	2847
2624	2848	#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
2625	2849
2626		-#define VLV_DISPLAY_BASE 0x180000
2627		-#define VLV_MIPI_BASE VLV_DISPLAY_BASE
2628		-#define BXT_MIPI_BASE 0x60000
2629		-
2630	2850	#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
2631	2851	#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
2632	2852	#define SCPD0 _MMIO(0x209c) /* 915+ only */
2633		-#define IER _MMIO(0x20a0)
2634		-#define IIR _MMIO(0x20a4)
2635		-#define IMR _MMIO(0x20a8)
2636		-#define ISR _MMIO(0x20ac)
	2853	+#define SCPD_FBC_IGNORE_3D (1 << 6)
	2854	+#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
	2855	+#define GEN2_IER _MMIO(0x20a0)
	2856	+#define GEN2_IIR _MMIO(0x20a4)
	2857	+#define GEN2_IMR _MMIO(0x20a8)
	2858	+#define GEN2_ISR _MMIO(0x20ac)
2637	2859	#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
2638	2860	#define GINT_DIS (1 << 22)
2639	2861	#define GCFG_DIS (1 << 8)
..	..	@@ -2664,7 +2886,7 @@
2664	2886	#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
2665	2887	#define INSTPM_TLB_INVALIDATE (1 << 9)
2666	2888	#define INSTPM_SYNC_FLUSH (1 << 5)
2667		-#define ACTHD _MMIO(0x20c8)
	2889	+#define ACTHD(base) _MMIO((base) + 0xc8)
2668	2890	#define MEM_MODE _MMIO(0x20cc)
2669	2891	#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
2670	2892	#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
..	..	@@ -2681,7 +2903,12 @@
2681	2903	#define LM_FIFO_WATERMARK 0x0000001F
2682	2904	#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
2683	2905
2684		-#define MBUS_ABOX_CTL _MMIO(0x45038)
	2906	+#define _MBUS_ABOX0_CTL 0x45038
	2907	+#define _MBUS_ABOX1_CTL 0x45048
	2908	+#define _MBUS_ABOX2_CTL 0x4504C
	2909	+#define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \
	2910	+ _MBUS_ABOX1_CTL, \
	2911	+ _MBUS_ABOX2_CTL))
2685	2912	#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
2686	2913	#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
2687	2914	#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
..	..	@@ -2705,6 +2932,12 @@
2705	2932	#define MBUS_UBOX_CTL _MMIO(0x4503C)
2706	2933	#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
2707	2934	#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
	2935	+
	2936	+#define HDPORT_STATE _MMIO(0x45050)
	2937	+#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12)
	2938	+#define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2)
	2939	+#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1)
	2940	+#define HDPORT_ENABLED REG_BIT(0)
2708	2941
2709	2942	/* Make render/texture TLB fetches lower priorty than associated data
2710	2943	* fetches. This is not turned on by default
..	..	@@ -2785,6 +3018,7 @@
2785	3018	#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
2786	3019	#define GFX_FLSH_CNTL_EN (1 << 0)
2787	3020	#define ECOSKPD _MMIO(0x21d0)
	3021	+#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
2788	3022	#define ECO_GATING_CX_ONLY (1 << 3)
2789	3023	#define ECO_FLIP_DONE (1 << 0)
2790	3024
..	..	@@ -2802,11 +3036,15 @@
2802	3036
2803	3037	#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
2804	3038	#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
	3039	+#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
2805	3040	#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
2806	3041	#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
2807	3042
2808	3043	#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
2809	3044	#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
	3045	+
	3046	+#define GEN10_CACHE_MODE_SS _MMIO(0xe420)
	3047	+#define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
2810	3048
2811	3049	/* Fuse readout registers for GT */
2812	3050	#define HSW_PAVP_FUSE1 _MMIO(0x911C)
..	..	@@ -2867,7 +3105,7 @@
2867	3105	#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
2868	3106	#define GEN11_GT_VDBOX_DISABLE_MASK 0xff
2869	3107	#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
2870		-#define GEN11_GT_VEBOX_DISABLE_MASK (0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
	3108	+#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
2871	3109
2872	3110	#define GEN11_EU_DISABLE _MMIO(0x9134)
2873	3111	#define GEN11_EU_DIS_MASK 0xFF
..	..	@@ -2876,6 +3114,8 @@
2876	3114	#define GEN11_GT_S_ENA_MASK 0xFF
2877	3115
2878	3116	#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
	3117	+
	3118	+#define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
2879	3119
2880	3120	#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
2881	3121	#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
..	..	@@ -2900,10 +3140,11 @@
2900	3140	#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
2901	3141	#define GT_BSD_USER_INTERRUPT (1 << 12)
2902	3142	#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
	3143	+#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */
2903	3144	#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
2904	3145	#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
2905	3146	#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
2906		-#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
	3147	+#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
2907	3148	#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
2908	3149	#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
2909	3150	#define GT_RENDER_USER_INTERRUPT (1 << 0)
..	..	@@ -2975,6 +3216,7 @@
2975	3216	#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
2976	3217	#define GEN7_FF_SCHED_MASK 0x0077070
2977	3218	#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
	3219	+#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
2978	3220	#define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
2979	3221	#define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
2980	3222	#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
..	..	@@ -2996,13 +3238,17 @@
2996	3238	#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
2997	3239	#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
2998	3240	#define FBC_CONTROL _MMIO(0x3208)
2999		-#define FBC_CTL_EN (1 << 31)
3000		-#define FBC_CTL_PERIODIC (1 << 30)
3001		-#define FBC_CTL_INTERVAL_SHIFT (16)
3002		-#define FBC_CTL_UNCOMPRESSIBLE (1 << 14)
3003		-#define FBC_CTL_C3_IDLE (1 << 13)
3004		-#define FBC_CTL_STRIDE_SHIFT (5)
3005		-#define FBC_CTL_FENCENO_SHIFT (0)
	3241	+#define FBC_CTL_EN REG_BIT(31)
	3242	+#define FBC_CTL_PERIODIC REG_BIT(30)
	3243	+#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
	3244	+#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
	3245	+#define FBC_CTL_STOP_ON_MOD REG_BIT(15)
	3246	+#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
	3247	+#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm */
	3248	+#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
	3249	+#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
	3250	+#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
	3251	+#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
3006	3252	#define FBC_COMMAND _MMIO(0x320c)
3007	3253	#define FBC_CMD_COMPRESS (1 << 0)
3008	3254	#define FBC_STATUS _MMIO(0x3210)
..	..	@@ -3070,6 +3316,7 @@
3070	3316	#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
3071	3317	#define ILK_DPFC_CHICKEN _MMIO(0x43224)
3072	3318	#define ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
	3319	+#define ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL (1 << 14)
3073	3320	#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23)
3074	3321	#define ILK_FBC_RT_BASE _MMIO(0x2128)
3075	3322	#define ILK_FBC_RT_VALID (1 << 0)
..	..	@@ -3091,6 +3338,7 @@
3091	3338
3092	3339	/* Framebuffer compression for Ivybridge */
3093	3340	#define IVB_FBC_RT_BASE _MMIO(0x7020)
	3341	+#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
3094	3342
3095	3343	#define IPS_CTL _MMIO(0x43408)
3096	3344	#define IPS_ENABLE (1 << 31)
..	..	@@ -3102,18 +3350,9 @@
3102	3350	/*
3103	3351	* GPIO regs
3104	3352	*/
3105		-#define GPIOA _MMIO(0x5010)
3106		-#define GPIOB _MMIO(0x5014)
3107		-#define GPIOC _MMIO(0x5018)
3108		-#define GPIOD _MMIO(0x501c)
3109		-#define GPIOE _MMIO(0x5020)
3110		-#define GPIOF _MMIO(0x5024)
3111		-#define GPIOG _MMIO(0x5028)
3112		-#define GPIOH _MMIO(0x502c)
3113		-#define GPIOJ _MMIO(0x5034)
3114		-#define GPIOK _MMIO(0x5038)
3115		-#define GPIOL _MMIO(0x503C)
3116		-#define GPIOM _MMIO(0x5040)
	3353	+#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
	3354	+ 4 * (gpio))
	3355	+
3117	3356	# define GPIO_CLOCK_DIR_MASK (1 << 0)
3118	3357	# define GPIO_CLOCK_DIR_IN (0 << 1)
3119	3358	# define GPIO_CLOCK_DIR_OUT (1 << 1)
..	..	@@ -3137,25 +3376,7 @@
3137	3376	#define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */
3138	3377	#define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
3139	3378	#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
3140		-#define GMBUS_PIN_DISABLED 0
3141		-#define GMBUS_PIN_SSC 1
3142		-#define GMBUS_PIN_VGADDC 2
3143		-#define GMBUS_PIN_PANEL 3
3144		-#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
3145		-#define GMBUS_PIN_DPC 4 /* HDMIC */
3146		-#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
3147		-#define GMBUS_PIN_DPD 6 /* HDMID */
3148		-#define GMBUS_PIN_RESERVED 7 /* 7 reserved */
3149		-#define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
3150		-#define GMBUS_PIN_2_BXT 2
3151		-#define GMBUS_PIN_3_BXT 3
3152		-#define GMBUS_PIN_4_CNP 4
3153		-#define GMBUS_PIN_9_TC1_ICP 9
3154		-#define GMBUS_PIN_10_TC2_ICP 10
3155		-#define GMBUS_PIN_11_TC3_ICP 11
3156		-#define GMBUS_PIN_12_TC4_ICP 12
3157	3379
3158		-#define GMBUS_NUM_PINS 13 /* including 0 */
3159	3380	#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3160	3381	#define GMBUS_SW_CLR_INT (1 << 31)
3161	3382	#define GMBUS_SW_RDY (1 << 30)
..	..	@@ -3192,9 +3413,9 @@
3192	3413	/*
3193	3414	* Clock control & power management
3194	3415	*/
3195		-#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
3196		-#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
3197		-#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
	3416	+#define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
	3417	+#define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
	3418	+#define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
3198	3419	#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3199	3420
3200	3421	#define VGA0 _MMIO(0x6000)
..	..	@@ -3291,9 +3512,9 @@
3291	3512	#define SDVO_MULTIPLIER_SHIFT_HIRES 4
3292	3513	#define SDVO_MULTIPLIER_SHIFT_VGA 0
3293	3514
3294		-#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
3295		-#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
3296		-#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
	3515	+#define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
	3516	+#define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
	3517	+#define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
3297	3518	#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3298	3519
3299	3520	/*
..	..	@@ -3365,7 +3586,7 @@
3365	3586	#define DSTATE_PLL_D3_OFF (1 << 3)
3366	3587	#define DSTATE_GFX_CLOCK_GATING (1 << 1)
3367	3588	#define DSTATE_DOT_CLOCK_GATING (1 << 0)
3368		-#define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
	3589	+#define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
3369	3590	# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
3370	3591	# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
3371	3592	# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
..	..	@@ -3502,11 +3723,16 @@
3502	3723	/*
3503	3724	* Palette regs
3504	3725	*/
3505		-#define PALETTE_A_OFFSET 0xa000
3506		-#define PALETTE_B_OFFSET 0xa800
3507		-#define CHV_PALETTE_C_OFFSET 0xc000
3508		-#define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \
3509		- dev_priv->info.display_mmio_offset + (i) * 4)
	3726	+#define _PALETTE_A 0xa000
	3727	+#define _PALETTE_B 0xa800
	3728	+#define _CHV_PALETTE_C 0xc000
	3729	+#define PALETTE_RED_MASK REG_GENMASK(23, 16)
	3730	+#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
	3731	+#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
	3732	+#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
	3733	+ _PICK((pipe), _PALETTE_A, \
	3734	+ _PALETTE_B, _CHV_PALETTE_C) + \
	3735	+ (i) * 4)
3510	3736
3511	3737	/* MCH MMIO space */
3512	3738
..	..	@@ -3579,23 +3805,18 @@
3579	3805	#define MCH_SSKPD_WM0_MASK 0x3f
3580	3806	#define MCH_SSKPD_WM0_VAL 0xc
3581	3807
3582		-#define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
3583		-
3584	3808	/* Clocking configuration register */
3585	3809	#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3586		-#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
	3810	+#define CLKCFG_FSB_400 (0 << 0) /* hrawclk 100 */
	3811	+#define CLKCFG_FSB_400_ALT (5 << 0) /* hrawclk 100 */
3587	3812	#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
3588	3813	#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
3589	3814	#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
3590	3815	#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
3591	3816	#define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */
3592	3817	#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
3593		-/*
3594		- * Note that on at least on ELK the below value is reported for both
3595		- * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet
3596		- * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.
3597		- */
3598	3818	#define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */
	3819	+#define CLKCFG_FSB_1600_ALT (6 << 0) /* hrawclk 400 */
3599	3820	#define CLKCFG_FSB_MASK (7 << 0)
3600	3821	#define CLKCFG_MEM_533 (1 << 4)
3601	3822	#define CLKCFG_MEM_667 (2 << 4)
..	..	@@ -3839,36 +4060,12 @@
3839	4060	#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
3840	4061	#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
3841	4062	#define BXT_RP_STATE_CAP _MMIO(0x138170)
3842		-
3843		-/*
3844		- * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
3845		- * 8300) freezing up around GPU hangs. Looks as if even
3846		- * scheduling/timer interrupts start misbehaving if the RPS
3847		- * EI/thresholds are "bad", leading to a very sluggish or even
3848		- * frozen machine.
3849		- */
3850		-#define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
3851		-#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
3852		-#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
3853		-#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
3854		- (IS_GEN9_LP(dev_priv) ? \
3855		- INTERVAL_0_833_US(us) : \
3856		- INTERVAL_1_33_US(us)) : \
3857		- INTERVAL_1_28_US(us))
3858		-
3859		-#define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100)
3860		-#define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
3861		-#define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
3862		-#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
3863		- (IS_GEN9_LP(dev_priv) ? \
3864		- INTERVAL_0_833_TO_US(interval) : \
3865		- INTERVAL_1_33_TO_US(interval)) : \
3866		- INTERVAL_1_28_TO_US(interval))
	4063	+#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
3867	4064
3868	4065	/*
3869	4066	* Logical Context regs
3870	4067	*/
3871		-#define CCID _MMIO(0x2180)
	4068	+#define CCID(base) _MMIO((base) + 0x180)
3872	4069	#define CCID_EN BIT(0)
3873	4070	#define CCID_EXTENDED_STATE_RESTORE BIT(2)
3874	4071	#define CCID_EXTENDED_STATE_SAVE BIT(3)
..	..	@@ -3960,6 +4157,9 @@
3960	4157	#define PWM2_GATING_DIS (1 << 14)
3961	4158	#define PWM1_GATING_DIS (1 << 13)
3962	4159
	4160	+#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
	4161	+#define TGL_VRH_GATING_DIS REG_BIT(31)
	4162	+
3963	4163	#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
3964	4164	#define BXT_GMBUS_GATING_DIS (1 << 14)
3965	4165
..	..	@@ -3983,12 +4183,23 @@
3983	4183	#define SARBUNIT_CLKGATE_DIS (1 << 5)
3984	4184	#define RCCUNIT_CLKGATE_DIS (1 << 7)
3985	4185	#define MSCUNIT_CLKGATE_DIS (1 << 10)
	4186	+#define L3_CLKGATE_DIS REG_BIT(16)
	4187	+#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
3986	4188
3987	4189	#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
3988	4190	#define GWUNIT_CLKGATE_DIS (1 << 16)
3989	4191
	4192	+#define SUBSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x9528)
	4193	+#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
	4194	+
3990	4195	#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
3991		-#define VFUNIT_CLKGATE_DIS (1 << 20)
	4196	+#define VFUNIT_CLKGATE_DIS REG_BIT(20)
	4197	+#define HSUNIT_CLKGATE_DIS REG_BIT(8)
	4198	+#define VSUNIT_CLKGATE_DIS REG_BIT(3)
	4199	+
	4200	+#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
	4201	+#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
	4202	+#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
3992	4203
3993	4204	#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
3994	4205	#define CGPSF_CLKGATE_DIS (1 << 3)
..	..	@@ -4000,6 +4211,15 @@
4000	4211	/* Pipe A CRC regs */
4001	4212	#define _PIPE_CRC_CTL_A 0x60050
4002	4213	#define PIPE_CRC_ENABLE (1 << 31)
	4214	+/* skl+ source selection */
	4215	+#define PIPE_CRC_SOURCE_PLANE_1_SKL (0 << 28)
	4216	+#define PIPE_CRC_SOURCE_PLANE_2_SKL (2 << 28)
	4217	+#define PIPE_CRC_SOURCE_DMUX_SKL (4 << 28)
	4218	+#define PIPE_CRC_SOURCE_PLANE_3_SKL (6 << 28)
	4219	+#define PIPE_CRC_SOURCE_PLANE_4_SKL (7 << 28)
	4220	+#define PIPE_CRC_SOURCE_PLANE_5_SKL (5 << 28)
	4221	+#define PIPE_CRC_SOURCE_PLANE_6_SKL (3 << 28)
	4222	+#define PIPE_CRC_SOURCE_PLANE_7_SKL (1 << 28)
4003	4223	/* ivb+ source selection */
4004	4224	#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
4005	4225	#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
..	..	@@ -4071,6 +4291,7 @@
4071	4291	#define _VTOTAL_A 0x6000c
4072	4292	#define _VBLANK_A 0x60010
4073	4293	#define _VSYNC_A 0x60014
	4294	+#define _EXITLINE_A 0x60018
4074	4295	#define _PIPEASRC 0x6001c
4075	4296	#define _BCLRPAT_A 0x60020
4076	4297	#define _VSYNCSHIFT_A 0x60028
..	..	@@ -4088,15 +4309,28 @@
4088	4309	#define _VSYNCSHIFT_B 0x61028
4089	4310	#define _PIPE_MULT_B 0x6102c
4090	4311
	4312	+/* DSI 0 timing regs */
	4313	+#define _HTOTAL_DSI0 0x6b000
	4314	+#define _HSYNC_DSI0 0x6b008
	4315	+#define _VTOTAL_DSI0 0x6b00c
	4316	+#define _VSYNC_DSI0 0x6b014
	4317	+#define _VSYNCSHIFT_DSI0 0x6b028
	4318	+
	4319	+/* DSI 1 timing regs */
	4320	+#define _HTOTAL_DSI1 0x6b800
	4321	+#define _HSYNC_DSI1 0x6b808
	4322	+#define _VTOTAL_DSI1 0x6b80c
	4323	+#define _VSYNC_DSI1 0x6b814
	4324	+#define _VSYNCSHIFT_DSI1 0x6b828
	4325	+
4091	4326	#define TRANSCODER_A_OFFSET 0x60000
4092	4327	#define TRANSCODER_B_OFFSET 0x61000
4093	4328	#define TRANSCODER_C_OFFSET 0x62000
4094	4329	#define CHV_TRANSCODER_C_OFFSET 0x63000
	4330	+#define TRANSCODER_D_OFFSET 0x63000
4095	4331	#define TRANSCODER_EDP_OFFSET 0x6f000
4096		-
4097		-#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
4098		- dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
4099		- dev_priv->info.display_mmio_offset)
	4332	+#define TRANSCODER_DSI0_OFFSET 0x6b000
	4333	+#define TRANSCODER_DSI1_OFFSET 0x6b800
4100	4334
4101	4335	#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
4102	4336	#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
..	..	@@ -4109,46 +4343,112 @@
4109	4343	#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
4110	4344	#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
4111	4345
4112		-/* VLV eDP PSR registers */
4113		-#define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
4114		-#define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
4115		-#define VLV_EDP_PSR_ENABLE (1 << 0)
4116		-#define VLV_EDP_PSR_RESET (1 << 1)
4117		-#define VLV_EDP_PSR_MODE_MASK (7 << 2)
4118		-#define VLV_EDP_PSR_MODE_HW_TIMER (1 << 3)
4119		-#define VLV_EDP_PSR_MODE_SW_TIMER (1 << 2)
4120		-#define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1 << 7)
4121		-#define VLV_EDP_PSR_ACTIVE_ENTRY (1 << 8)
4122		-#define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1 << 9)
4123		-#define VLV_EDP_PSR_DBL_FRAME (1 << 10)
4124		-#define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff << 16)
4125		-#define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
4126		-#define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
	4346	+#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A)
	4347	+#define EXITLINE_ENABLE REG_BIT(31)
	4348	+#define EXITLINE_MASK REG_GENMASK(12, 0)
	4349	+#define EXITLINE_SHIFT 0
4127	4350
4128		-#define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
4129		-#define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
4130		-#define VLV_EDP_PSR_SDP_FREQ_MASK (3 << 30)
4131		-#define VLV_EDP_PSR_SDP_FREQ_ONCE (1 << 31)
4132		-#define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1 << 30)
4133		-#define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
	4351	+/* VRR registers */
	4352	+#define _TRANS_VRR_CTL_A 0x60420
	4353	+#define _TRANS_VRR_CTL_B 0x61420
	4354	+#define _TRANS_VRR_CTL_C 0x62420
	4355	+#define _TRANS_VRR_CTL_D 0x63420
	4356	+#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
	4357	+#define VRR_CTL_VRR_ENABLE REG_BIT(31)
	4358	+#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
	4359	+#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
	4360	+#define VRR_CTL_LINE_COUNT_MASK REG_GENMASK(10, 3)
	4361	+#define VRR_CTL_SW_FULLLINE_COUNT REG_BIT(0)
4134	4362
4135		-#define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
4136		-#define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
4137		-#define VLV_EDP_PSR_LAST_STATE_MASK (7 << 3)
4138		-#define VLV_EDP_PSR_CURR_STATE_MASK 7
4139		-#define VLV_EDP_PSR_DISABLED (0 << 0)
4140		-#define VLV_EDP_PSR_INACTIVE (1 << 0)
4141		-#define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2 << 0)
4142		-#define VLV_EDP_PSR_ACTIVE_NORFB_UP (3 << 0)
4143		-#define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4 << 0)
4144		-#define VLV_EDP_PSR_EXIT (5 << 0)
4145		-#define VLV_EDP_PSR_IN_TRANS (1 << 7)
4146		-#define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
	4363	+#define _TRANS_VRR_VMAX_A 0x60424
	4364	+#define _TRANS_VRR_VMAX_B 0x61424
	4365	+#define _TRANS_VRR_VMAX_C 0x62424
	4366	+#define _TRANS_VRR_VMAX_D 0x63424
	4367	+#define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A)
	4368	+#define VRR_VMAX_MASK REG_GENMASK(19, 0)
4147	4369
4148		-/* HSW+ eDP PSR registers */
4149		-#define HSW_EDP_PSR_BASE 0x64800
4150		-#define BDW_EDP_PSR_BASE 0x6f800
4151		-#define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
	4370	+#define _TRANS_VRR_VMIN_A 0x60434
	4371	+#define _TRANS_VRR_VMIN_B 0x61434
	4372	+#define _TRANS_VRR_VMIN_C 0x62434
	4373	+#define _TRANS_VRR_VMIN_D 0x63434
	4374	+#define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A)
	4375	+#define VRR_VMIN_MASK REG_GENMASK(15, 0)
	4376	+
	4377	+#define _TRANS_VRR_VMAXSHIFT_A 0x60428
	4378	+#define _TRANS_VRR_VMAXSHIFT_B 0x61428
	4379	+#define _TRANS_VRR_VMAXSHIFT_C 0x62428
	4380	+#define _TRANS_VRR_VMAXSHIFT_D 0x63428
	4381	+#define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \
	4382	+ _TRANS_VRR_VMAXSHIFT_A)
	4383	+#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
	4384	+#define VRR_VMAXSHIFT_DEC REG_BIT(16)
	4385	+#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
	4386	+
	4387	+#define _TRANS_VRR_STATUS_A 0x6042C
	4388	+#define _TRANS_VRR_STATUS_B 0x6142C
	4389	+#define _TRANS_VRR_STATUS_C 0x6242C
	4390	+#define _TRANS_VRR_STATUS_D 0x6342C
	4391	+#define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A)
	4392	+#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
	4393	+#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
	4394	+#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
	4395	+#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
	4396	+#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
	4397	+#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
	4398	+#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
	4399	+#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
	4400	+#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
	4401	+#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
	4402	+#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
	4403	+#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
	4404	+#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
	4405	+#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
	4406	+
	4407	+#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
	4408	+#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
	4409	+#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
	4410	+#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
	4411	+#define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \
	4412	+ _TRANS_VRR_VTOTAL_PREV_A)
	4413	+#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
	4414	+#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
	4415	+#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
	4416	+#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
	4417	+
	4418	+#define _TRANS_VRR_FLIPLINE_A 0x60438
	4419	+#define _TRANS_VRR_FLIPLINE_B 0x61438
	4420	+#define _TRANS_VRR_FLIPLINE_C 0x62438
	4421	+#define _TRANS_VRR_FLIPLINE_D 0x63438
	4422	+#define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \
	4423	+ _TRANS_VRR_FLIPLINE_A)
	4424	+#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
	4425	+
	4426	+#define _TRANS_VRR_STATUS2_A 0x6043C
	4427	+#define _TRANS_VRR_STATUS2_B 0x6143C
	4428	+#define _TRANS_VRR_STATUS2_C 0x6243C
	4429	+#define _TRANS_VRR_STATUS2_D 0x6343C
	4430	+#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
	4431	+#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
	4432	+
	4433	+#define _TRANS_PUSH_A 0x60A70
	4434	+#define _TRANS_PUSH_B 0x61A70
	4435	+#define _TRANS_PUSH_C 0x62A70
	4436	+#define _TRANS_PUSH_D 0x63A70
	4437	+#define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A)
	4438	+#define TRANS_PUSH_EN REG_BIT(31)
	4439	+#define TRANS_PUSH_SEND REG_BIT(30)
	4440	+
	4441	+/*
	4442	+ * HSW+ eDP PSR registers
	4443	+ *
	4444	+ * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
	4445	+ * instance of it
	4446	+ */
	4447	+#define _HSW_EDP_PSR_BASE 0x64800
	4448	+#define _SRD_CTL_A 0x60800
	4449	+#define _SRD_CTL_EDP 0x6f800
	4450	+#define _PSR_ADJ(tran, reg) (_TRANS2(tran, reg) - dev_priv->hsw_psr_mmio_adjust)
	4451	+#define EDP_PSR_CTL(tran) _MMIO(_PSR_ADJ(tran, _SRD_CTL_A))
4152	4452	#define EDP_PSR_ENABLE (1 << 31)
4153	4453	#define BDW_PSR_SINGLE_FRAME (1 << 30)
4154	4454	#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
..	..	@@ -4167,29 +4467,47 @@
4167	4467	#define EDP_PSR_TP2_TP3_TIME_100us (1 << 8)
4168	4468	#define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8)
4169	4469	#define EDP_PSR_TP2_TP3_TIME_0us (3 << 8)
	4470	+#define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */
4170	4471	#define EDP_PSR_TP1_TIME_500us (0 << 4)
4171	4472	#define EDP_PSR_TP1_TIME_100us (1 << 4)
4172	4473	#define EDP_PSR_TP1_TIME_2500us (2 << 4)
4173	4474	#define EDP_PSR_TP1_TIME_0us (3 << 4)
4174	4475	#define EDP_PSR_IDLE_FRAME_SHIFT 0
4175	4476
4176		-/* Bspec claims those aren't shifted but stay at 0x64800 */
	4477	+/*
	4478	+ * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
	4479	+ * to transcoder and bits defined for each one as if using no shift (i.e. as if
	4480	+ * it was for TRANSCODER_EDP)
	4481	+ */
4177	4482	#define EDP_PSR_IMR _MMIO(0x64834)
4178	4483	#define EDP_PSR_IIR _MMIO(0x64838)
4179		-#define EDP_PSR_ERROR(trans) (1 << (((trans) * 8 + 10) & 31))
4180		-#define EDP_PSR_POST_EXIT(trans) (1 << (((trans) * 8 + 9) & 31))
4181		-#define EDP_PSR_PRE_ENTRY(trans) (1 << (((trans) * 8 + 8) & 31))
	4484	+#define _PSR_IMR_A 0x60814
	4485	+#define _PSR_IIR_A 0x60818
	4486	+#define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A)
	4487	+#define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A)
	4488	+#define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
	4489	+ 0 : ((trans) - TRANSCODER_A + 1) * 8)
	4490	+#define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans))
	4491	+#define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans))
	4492	+#define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans))
	4493	+#define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans))
4182	4494
4183		-#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
	4495	+#define _SRD_AUX_CTL_A 0x60810
	4496	+#define _SRD_AUX_CTL_EDP 0x6f810
	4497	+#define EDP_PSR_AUX_CTL(tran) _MMIO(_PSR_ADJ(tran, _SRD_AUX_CTL_A))
4184	4498	#define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
4185	4499	#define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
4186	4500	#define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
4187	4501	#define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11)
4188	4502	#define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
4189	4503
4190		-#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
	4504	+#define _SRD_AUX_DATA_A 0x60814
	4505	+#define _SRD_AUX_DATA_EDP 0x6f814
	4506	+#define EDP_PSR_AUX_DATA(tran, i) _MMIO(_PSR_ADJ(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
4191	4507
4192		-#define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)
	4508	+#define _SRD_STATUS_A 0x60840
	4509	+#define _SRD_STATUS_EDP 0x6f840
	4510	+#define EDP_PSR_STATUS(tran) _MMIO(_PSR_ADJ(tran, _SRD_STATUS_A))
4193	4511	#define EDP_PSR_STATUS_STATE_MASK (7 << 29)
4194	4512	#define EDP_PSR_STATUS_STATE_SHIFT 29
4195	4513	#define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
..	..	@@ -4214,41 +4532,62 @@
4214	4532	#define EDP_PSR_STATUS_SENDING_TP1 (1 << 4)
4215	4533	#define EDP_PSR_STATUS_IDLE_MASK 0xf
4216	4534
4217		-#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
	4535	+#define _SRD_PERF_CNT_A 0x60844
	4536	+#define _SRD_PERF_CNT_EDP 0x6f844
	4537	+#define EDP_PSR_PERF_CNT(tran) _MMIO(_PSR_ADJ(tran, _SRD_PERF_CNT_A))
4218	4538	#define EDP_PSR_PERF_CNT_MASK 0xffffff
4219	4539
4220		-#define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */
	4540	+/* PSR_MASK on SKL+ */
	4541	+#define _SRD_DEBUG_A 0x60860
	4542	+#define _SRD_DEBUG_EDP 0x6f860
	4543	+#define EDP_PSR_DEBUG(tran) _MMIO(_PSR_ADJ(tran, _SRD_DEBUG_A))
4221	4544	#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
4222	4545	#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
4223	4546	#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
4224	4547	#define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
4225		-#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16)
	4548	+#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
4226	4549	#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
4227	4550
4228		-#define EDP_PSR2_CTL _MMIO(0x6f900)
4229		-#define EDP_PSR2_ENABLE (1 << 31)
4230		-#define EDP_SU_TRACK_ENABLE (1 << 30)
4231		-#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
4232		-#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */
4233		-#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
4234		-#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
4235		-#define EDP_PSR2_TP2_TIME_500us (0 << 8)
4236		-#define EDP_PSR2_TP2_TIME_100us (1 << 8)
4237		-#define EDP_PSR2_TP2_TIME_2500us (2 << 8)
4238		-#define EDP_PSR2_TP2_TIME_50us (3 << 8)
4239		-#define EDP_PSR2_TP2_TIME_MASK (3 << 8)
4240		-#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4241		-#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
4242		-#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
4243		-#define EDP_PSR2_IDLE_FRAME_MASK 0xf
4244		-#define EDP_PSR2_IDLE_FRAME_SHIFT 0
	4551	+#define _PSR2_CTL_A 0x60900
	4552	+#define _PSR2_CTL_EDP 0x6f900
	4553	+#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
	4554	+#define EDP_PSR2_ENABLE (1 << 31)
	4555	+#define EDP_SU_TRACK_ENABLE (1 << 30)
	4556	+#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
	4557	+#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
	4558	+#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
	4559	+#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */
	4560	+#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
	4561	+#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
	4562	+#define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8
	4563	+#define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
	4564	+#define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13)
	4565	+#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5
	4566	+#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13)
	4567	+#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13)
	4568	+#define EDP_PSR2_FAST_WAKE_MAX_LINES 8
	4569	+#define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
	4570	+#define EDP_PSR2_FAST_WAKE_MASK (3 << 11)
	4571	+#define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5
	4572	+#define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10)
	4573	+#define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10)
	4574	+#define EDP_PSR2_TP2_TIME_500us (0 << 8)
	4575	+#define EDP_PSR2_TP2_TIME_100us (1 << 8)
	4576	+#define EDP_PSR2_TP2_TIME_2500us (2 << 8)
	4577	+#define EDP_PSR2_TP2_TIME_50us (3 << 8)
	4578	+#define EDP_PSR2_TP2_TIME_MASK (3 << 8)
	4579	+#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
	4580	+#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
	4581	+#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
	4582	+#define EDP_PSR2_IDLE_FRAME_MASK 0xf
	4583	+#define EDP_PSR2_IDLE_FRAME_SHIFT 0
4245	4584
4246	4585	#define _PSR_EVENT_TRANS_A 0x60848
4247	4586	#define _PSR_EVENT_TRANS_B 0x61848
4248	4587	#define _PSR_EVENT_TRANS_C 0x62848
4249	4588	#define _PSR_EVENT_TRANS_D 0x63848
4250		-#define _PSR_EVENT_TRANS_EDP 0x6F848
4251		-#define PSR_EVENT(trans) _MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A)
	4589	+#define _PSR_EVENT_TRANS_EDP 0x6f848
	4590	+#define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A)
4252	4591	#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
4253	4592	#define PSR_EVENT_PSR2_DISABLED (1 << 16)
4254	4593	#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
..	..	@@ -4259,16 +4598,38 @@
4259	4598	#define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
4260	4599	#define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
4261	4600	#define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
4262		-#define PSR_EVENT_REGISTER_UPDATE (1 << 5)
	4601	+#define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */
4263	4602	#define PSR_EVENT_HDCP_ENABLE (1 << 4)
4264	4603	#define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
4265	4604	#define PSR_EVENT_VBI_ENABLE (1 << 2)
4266	4605	#define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
4267	4606	#define PSR_EVENT_PSR_DISABLE (1 << 0)
4268	4607
4269		-#define EDP_PSR2_STATUS _MMIO(0x6f940)
	4608	+#define _PSR2_STATUS_A 0x60940
	4609	+#define _PSR2_STATUS_EDP 0x6f940
	4610	+#define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A)
4270	4611	#define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
4271	4612	#define EDP_PSR2_STATUS_STATE_SHIFT 28
	4613	+
	4614	+#define _PSR2_SU_STATUS_A 0x60914
	4615	+#define _PSR2_SU_STATUS_EDP 0x6f914
	4616	+#define _PSR2_SU_STATUS(tran, index) _MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4)
	4617	+#define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3))
	4618	+#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
	4619	+#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
	4620	+#define PSR2_SU_STATUS_FRAMES 8
	4621	+
	4622	+#define _PSR2_MAN_TRK_CTL_A 0x60910
	4623	+#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
	4624	+#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
	4625	+#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
	4626	+#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
	4627	+#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
	4628	+#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)
	4629	+#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
	4630	+#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
	4631	+#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
	4632	+#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
4272	4633
4273	4634	/* VGA port control */
4274	4635	#define ADPA _MMIO(0x61100)
..	..	@@ -4320,7 +4681,7 @@
4320	4681
4321	4682
4322	4683	/* Hotplug control (945+ only) */
4323		-#define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
	4684	+#define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
4324	4685	#define PORTB_HOTPLUG_INT_EN (1 << 29)
4325	4686	#define PORTC_HOTPLUG_INT_EN (1 << 28)
4326	4687	#define PORTD_HOTPLUG_INT_EN (1 << 27)
..	..	@@ -4350,7 +4711,7 @@
4350	4711	#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
4351	4712	#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
4352	4713
4353		-#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
	4714	+#define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
4354	4715	/*
4355	4716	* HDMI/DP bits are g4x+
4356	4717	*
..	..	@@ -4432,7 +4793,7 @@
4432	4793
4433	4794	#define PORT_DFT_I9XX _MMIO(0x61150)
4434	4795	#define DC_BALANCE_RESET (1 << 25)
4435		-#define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
	4796	+#define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
4436	4797	#define DC_BALANCE_RESET_VLV (1 << 31)
4437	4798	#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) \| (0x3 << 0))
4438	4799	#define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
..	..	@@ -4473,7 +4834,7 @@
4473	4834	#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
4474	4835	#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
4475	4836	#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
4476		-#define SDVO_AUDIO_ENABLE (1 << 6)
	4837	+#define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */
4477	4838	/* VSYNC/HSYNC bits new with 965, default is to be set */
4478	4839	#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
4479	4840	#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
..	..	@@ -4591,19 +4952,22 @@
4591	4952	* (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
4592	4953	* of the infoframe structure specified by CEA-861. */
4593	4954	#define VIDEO_DIP_DATA_SIZE 32
	4955	+#define VIDEO_DIP_GMP_DATA_SIZE 36
4594	4956	#define VIDEO_DIP_VSC_DATA_SIZE 36
	4957	+#define VIDEO_DIP_PPS_DATA_SIZE 132
4595	4958	#define VIDEO_DIP_CTL _MMIO(0x61170)
4596	4959	/* Pre HSW: */
4597	4960	#define VIDEO_DIP_ENABLE (1 << 31)
4598	4961	#define VIDEO_DIP_PORT(port) ((port) << 29)
4599	4962	#define VIDEO_DIP_PORT_MASK (3 << 29)
4600		-#define VIDEO_DIP_ENABLE_GCP (1 << 25)
	4963	+#define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
4601	4964	#define VIDEO_DIP_ENABLE_AVI (1 << 21)
4602	4965	#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
4603		-#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
	4966	+#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
4604	4967	#define VIDEO_DIP_ENABLE_SPD (8 << 21)
4605	4968	#define VIDEO_DIP_SELECT_AVI (0 << 19)
4606	4969	#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
	4970	+#define VIDEO_DIP_SELECT_GAMUT (2 << 19)
4607	4971	#define VIDEO_DIP_SELECT_SPD (3 << 19)
4608	4972	#define VIDEO_DIP_SELECT_MASK (3 << 19)
4609	4973	#define VIDEO_DIP_FREQ_ONCE (0 << 16)
..	..	@@ -4611,22 +4975,21 @@
4611	4975	#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
4612	4976	#define VIDEO_DIP_FREQ_MASK (3 << 16)
4613	4977	/* HSW and later: */
	4978	+#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
	4979	+#define PSR_VSC_BIT_7_SET (1 << 27)
	4980	+#define VSC_SELECT_MASK (0x3 << 25)
	4981	+#define VSC_SELECT_SHIFT 25
	4982	+#define VSC_DIP_HW_HEA_DATA (0 << 25)
	4983	+#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
	4984	+#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
	4985	+#define VSC_DIP_SW_HEA_DATA (3 << 25)
	4986	+#define VDIP_ENABLE_PPS (1 << 24)
4614	4987	#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
4615	4988	#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
4616	4989	#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
4617	4990	#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
4618	4991	#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
4619	4992	#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
4620		-
4621		-#define DRM_DIP_ENABLE (1 << 28)
4622		-#define PSR_VSC_BIT_7_SET (1 << 27)
4623		-#define VSC_SELECT_MASK (0x3 << 26)
4624		-#define VSC_SELECT_SHIFT 26
4625		-#define VSC_DIP_HW_HEA_DATA (0 << 26)
4626		-#define VSC_DIP_HW_HEA_SW_DATA (1 << 26)
4627		-#define VSC_DIP_HW_DATA_SW_HEA (2 << 26)
4628		-#define VSC_DIP_SW_HEA_DATA (3 << 26)
4629		-#define VDIP_ENABLE_PPS (1 << 24)
4630	4993
4631	4994	/* Panel power sequencing */
4632	4995	#define PPS_BASE 0x61200
..	..	@@ -4639,7 +5002,7 @@
4639	5002
4640	5003	#define _PP_STATUS 0x61200
4641	5004	#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
4642		-#define PP_ON (1 << 31)
	5005	+#define PP_ON REG_BIT(31)
4643	5006	/*
4644	5007	* Indicates that all dependencies of the panel are on:
4645	5008	*
..	..	@@ -4647,69 +5010,60 @@
4647	5010	* - pipe enabled
4648	5011	* - LVDS/DVOB/DVOC on
4649	5012	*/
4650		-#define PP_READY (1 << 30)
4651		-#define PP_SEQUENCE_NONE (0 << 28)
4652		-#define PP_SEQUENCE_POWER_UP (1 << 28)
4653		-#define PP_SEQUENCE_POWER_DOWN (2 << 28)
4654		-#define PP_SEQUENCE_MASK (3 << 28)
4655		-#define PP_SEQUENCE_SHIFT 28
4656		-#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
4657		-#define PP_SEQUENCE_STATE_MASK 0x0000000f
4658		-#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
4659		-#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
4660		-#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
4661		-#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
4662		-#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
4663		-#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
4664		-#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
4665		-#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
4666		-#define PP_SEQUENCE_STATE_RESET (0xf << 0)
	5013	+#define PP_READY REG_BIT(30)
	5014	+#define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
	5015	+#define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
	5016	+#define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
	5017	+#define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
	5018	+#define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
	5019	+#define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
	5020	+#define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
	5021	+#define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
	5022	+#define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
	5023	+#define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
	5024	+#define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
	5025	+#define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
	5026	+#define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
	5027	+#define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
	5028	+#define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
4667	5029
4668	5030	#define _PP_CONTROL 0x61204
4669	5031	#define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
4670		-#define PANEL_UNLOCK_REGS (0xabcd << 16)
4671		-#define PANEL_UNLOCK_MASK (0xffff << 16)
4672		-#define BXT_POWER_CYCLE_DELAY_MASK 0x1f0
4673		-#define BXT_POWER_CYCLE_DELAY_SHIFT 4
4674		-#define EDP_FORCE_VDD (1 << 3)
4675		-#define EDP_BLC_ENABLE (1 << 2)
4676		-#define PANEL_POWER_RESET (1 << 1)
4677		-#define PANEL_POWER_OFF (0 << 0)
4678		-#define PANEL_POWER_ON (1 << 0)
	5032	+#define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
	5033	+#define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
	5034	+#define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
	5035	+#define EDP_FORCE_VDD REG_BIT(3)
	5036	+#define EDP_BLC_ENABLE REG_BIT(2)
	5037	+#define PANEL_POWER_RESET REG_BIT(1)
	5038	+#define PANEL_POWER_ON REG_BIT(0)
4679	5039
4680	5040	#define _PP_ON_DELAYS 0x61208
4681	5041	#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
4682		-#define PANEL_PORT_SELECT_SHIFT 30
4683		-#define PANEL_PORT_SELECT_MASK (3 << 30)
4684		-#define PANEL_PORT_SELECT_LVDS (0 << 30)
4685		-#define PANEL_PORT_SELECT_DPA (1 << 30)
4686		-#define PANEL_PORT_SELECT_DPC (2 << 30)
4687		-#define PANEL_PORT_SELECT_DPD (3 << 30)
4688		-#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
4689		-#define PANEL_POWER_UP_DELAY_MASK 0x1fff0000
4690		-#define PANEL_POWER_UP_DELAY_SHIFT 16
4691		-#define PANEL_LIGHT_ON_DELAY_MASK 0x1fff
4692		-#define PANEL_LIGHT_ON_DELAY_SHIFT 0
	5042	+#define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
	5043	+#define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
	5044	+#define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
	5045	+#define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
	5046	+#define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
	5047	+#define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
	5048	+#define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
	5049	+#define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
4693	5050
4694	5051	#define _PP_OFF_DELAYS 0x6120C
4695	5052	#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
4696		-#define PANEL_POWER_DOWN_DELAY_MASK 0x1fff0000
4697		-#define PANEL_POWER_DOWN_DELAY_SHIFT 16
4698		-#define PANEL_LIGHT_OFF_DELAY_MASK 0x1fff
4699		-#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
	5053	+#define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16)
	5054	+#define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0)
4700	5055
4701	5056	#define _PP_DIVISOR 0x61210
4702	5057	#define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
4703		-#define PP_REFERENCE_DIVIDER_MASK 0xffffff00
4704		-#define PP_REFERENCE_DIVIDER_SHIFT 8
4705		-#define PANEL_POWER_CYCLE_DELAY_MASK 0x1f
4706		-#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
	5058	+#define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8)
	5059	+#define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0)
4707	5060
4708	5061	/* Panel fitting */
4709		-#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
	5062	+#define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
4710	5063	#define PFIT_ENABLE (1 << 31)
4711	5064	#define PFIT_PIPE_MASK (3 << 29)
4712	5065	#define PFIT_PIPE_SHIFT 29
	5066	+#define PFIT_PIPE(pipe) ((pipe) << 29)
4713	5067	#define VERT_INTERP_DISABLE (0 << 10)
4714	5068	#define VERT_INTERP_BILINEAR (1 << 10)
4715	5069	#define VERT_INTERP_MASK (3 << 10)
..	..	@@ -4724,7 +5078,7 @@
4724	5078	#define PFIT_SCALING_PROGRAMMED (1 << 26)
4725	5079	#define PFIT_SCALING_PILLAR (2 << 26)
4726	5080	#define PFIT_SCALING_LETTER (3 << 26)
4727		-#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
	5081	+#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
4728	5082	/* Pre-965 */
4729	5083	#define PFIT_VERT_SCALE_SHIFT 20
4730	5084	#define PFIT_VERT_SCALE_MASK 0xfff00000
..	..	@@ -4736,25 +5090,25 @@
4736	5090	#define PFIT_HORIZ_SCALE_SHIFT_965 0
4737	5091	#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
4738	5092
4739		-#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
	5093	+#define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
4740	5094
4741		-#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
4742		-#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
	5095	+#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
	5096	+#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
4743	5097	#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
4744	5098	_VLV_BLC_PWM_CTL2_B)
4745	5099
4746		-#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
4747		-#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
	5100	+#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
	5101	+#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
4748	5102	#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
4749	5103	_VLV_BLC_PWM_CTL_B)
4750	5104
4751		-#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
4752		-#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
	5105	+#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
	5106	+#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
4753	5107	#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
4754	5108	_VLV_BLC_HIST_CTL_B)
4755	5109
4756	5110	/* Backlight control */
4757		-#define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
	5111	+#define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
4758	5112	#define BLM_PWM_ENABLE (1 << 31)
4759	5113	#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
4760	5114	#define BLM_PIPE_SELECT (1 << 29)
..	..	@@ -4777,7 +5131,7 @@
4777	5131	#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
4778	5132	#define BLM_PHASE_IN_INCR_SHIFT (0)
4779	5133	#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
4780		-#define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
	5134	+#define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
4781	5135	/*
4782	5136	* This is the most significant 15 bits of the number of backlight cycles in a
4783	5137	* complete cycle of the modulated backlight control.
..	..	@@ -4799,7 +5153,7 @@
4799	5153	#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
4800	5154	#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
4801	5155
4802		-#define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
	5156	+#define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
4803	5157	#define BLM_HISTOGRAM_ENABLE (1 << 31)
4804	5158
4805	5159	/* New registers for PCH-split platforms. Safe where new bits show up, the
..	..	@@ -4817,14 +5171,20 @@
4817	5171	#define BLM_PCH_POLARITY (1 << 29)
4818	5172	#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
4819	5173
4820		-#define UTIL_PIN_CTL _MMIO(0x48400)
4821		-#define UTIL_PIN_ENABLE (1 << 31)
4822		-
4823		-#define UTIL_PIN_PIPE(x) ((x) << 29)
4824		-#define UTIL_PIN_PIPE_MASK (3 << 29)
4825		-#define UTIL_PIN_MODE_PWM (1 << 24)
4826		-#define UTIL_PIN_MODE_MASK (0xf << 24)
4827		-#define UTIL_PIN_POLARITY (1 << 22)
	5174	+#define UTIL_PIN_CTL _MMIO(0x48400)
	5175	+#define UTIL_PIN_ENABLE (1 << 31)
	5176	+#define UTIL_PIN_PIPE_MASK (3 << 29)
	5177	+#define UTIL_PIN_PIPE(x) ((x) << 29)
	5178	+#define UTIL_PIN_MODE_MASK (0xf << 24)
	5179	+#define UTIL_PIN_MODE_DATA (0 << 24)
	5180	+#define UTIL_PIN_MODE_PWM (1 << 24)
	5181	+#define UTIL_PIN_MODE_VBLANK (4 << 24)
	5182	+#define UTIL_PIN_MODE_VSYNC (5 << 24)
	5183	+#define UTIL_PIN_MODE_EYE_LEVEL (8 << 24)
	5184	+#define UTIL_PIN_OUTPUT_DATA (1 << 23)
	5185	+#define UTIL_PIN_POLARITY (1 << 22)
	5186	+#define UTIL_PIN_DIRECTION_INPUT (1 << 19)
	5187	+#define UTIL_PIN_INPUT_DATA (1 << 16)
4828	5188
4829	5189	/* BXT backlight register definition. */
4830	5190	#define _BXT_BLC_PWM_CTL1 0xC8250
..	..	@@ -4874,6 +5234,7 @@
4874	5234	# define TV_OVERSAMPLE_NONE (2 << 18)
4875	5235	/* Selects 8x oversampling */
4876	5236	# define TV_OVERSAMPLE_8X (3 << 18)
	5237	+# define TV_OVERSAMPLE_MASK (3 << 18)
4877	5238	/* Selects progressive mode rather than interlaced */
4878	5239	# define TV_PROGRESSIVE (1 << 17)
4879	5240	/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
..	..	@@ -5423,47 +5784,11 @@
5423	5784	* is 20 bytes in each direction, hence the 5 fixed
5424	5785	* data registers
5425	5786	*/
5426		-#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
5427		-#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
5428		-#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
5429		-#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
5430		-#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
5431		-#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
	5787	+#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
	5788	+#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
5432	5789
5433		-#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
5434		-#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
5435		-#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
5436		-#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
5437		-#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
5438		-#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
5439		-
5440		-#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
5441		-#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
5442		-#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
5443		-#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
5444		-#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
5445		-#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
5446		-
5447		-#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
5448		-#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
5449		-#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
5450		-#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
5451		-#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
5452		-#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
5453		-
5454		-#define _DPE_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64410)
5455		-#define _DPE_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64414)
5456		-#define _DPE_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64418)
5457		-#define _DPE_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6441c)
5458		-#define _DPE_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64420)
5459		-#define _DPE_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64424)
5460		-
5461		-#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
5462		-#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
5463		-#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
5464		-#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
5465		-#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
5466		-#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
	5790	+#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
	5791	+#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
5467	5792
5468	5793	#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5469	5794	#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
..	..	@@ -5492,6 +5817,7 @@
5492	5817	#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
5493	5818	#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
5494	5819	#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
	5820	+#define DP_AUX_CH_CTL_TBT_IO (1 << 11)
5495	5821	#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5496	5822	#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5497	5823	#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
..	..	@@ -5560,13 +5886,20 @@
5560	5886	#define PIPECONF_DOUBLE_WIDE (1 << 30)
5561	5887	#define I965_PIPECONF_ACTIVE (1 << 30)
5562	5888	#define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
5563		-#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
	5889	+#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */
	5890	+#define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3 */
5564	5891	#define PIPECONF_SINGLE_WIDE 0
5565	5892	#define PIPECONF_PIPE_UNLOCKED 0
5566	5893	#define PIPECONF_PIPE_LOCKED (1 << 25)
5567		-#define PIPECONF_PALETTE 0
5568		-#define PIPECONF_GAMMA (1 << 24)
5569	5894	#define PIPECONF_FORCE_BORDER (1 << 25)
	5895	+#define PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */
	5896	+#define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */
	5897	+#define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */
	5898	+#define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */
	5899	+#define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */
	5900	+#define PIPECONF_GAMMA_MODE_SPLIT (3 << 24) /* ivb */
	5901	+#define PIPECONF_GAMMA_MODE(x) ((x) << 24) /* pass in GAMMA_MODE_MODE_* */
	5902	+#define PIPECONF_GAMMA_MODE_SHIFT 24
5570	5903	#define PIPECONF_INTERLACE_MASK (7 << 21)
5571	5904	#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
5572	5905	/* Note that pre-gen3 does not support interlaced display directly. Panel
..	..	@@ -5588,6 +5921,11 @@
5588	5921	#define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
5589	5922	#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
5590	5923	#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
	5924	+#define PIPECONF_OUTPUT_COLORSPACE_MASK (3 << 11) /* ilk-ivb */
	5925	+#define PIPECONF_OUTPUT_COLORSPACE_RGB (0 << 11) /* ilk-ivb */
	5926	+#define PIPECONF_OUTPUT_COLORSPACE_YUV601 (1 << 11) /* ilk-ivb */
	5927	+#define PIPECONF_OUTPUT_COLORSPACE_YUV709 (2 << 11) /* ilk-ivb */
	5928	+#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW (1 << 11) /* hsw only */
5591	5929	#define PIPECONF_BPC_MASK (0x7 << 5)
5592	5930	#define PIPECONF_8BPC (0 << 5)
5593	5931	#define PIPECONF_10BPC (1 << 5)
..	..	@@ -5653,6 +5991,7 @@
5653	5991	#define PIPE_A_OFFSET 0x70000
5654	5992	#define PIPE_B_OFFSET 0x71000
5655	5993	#define PIPE_C_OFFSET 0x72000
	5994	+#define PIPE_D_OFFSET 0x73000
5656	5995	#define CHV_PIPE_C_OFFSET 0x74000
5657	5996	/*
5658	5997	* There's actually no pipe EDP. Some pipe registers have
..	..	@@ -5662,9 +6001,9 @@
5662	6001	*/
5663	6002	#define PIPE_EDP_OFFSET 0x7f000
5664	6003
5665		-#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
5666		- dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
5667		- dev_priv->info.display_mmio_offset)
	6004	+/* ICL DSI 0 and 1 */
	6005	+#define PIPE_DSI0_OFFSET 0x7b000
	6006	+#define PIPE_DSI1_OFFSET 0x7b800
5668	6007
5669	6008	#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
5670	6009	#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
..	..	@@ -5672,11 +6011,17 @@
5672	6011	#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
5673	6012	#define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
5674	6013
	6014	+#define _PIPEAGCMAX 0x70010
	6015	+#define _PIPEBGCMAX 0x71010
	6016	+#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
	6017	+
5675	6018	#define _PIPE_MISC_A 0x70030
5676	6019	#define _PIPE_MISC_B 0x71030
5677		-#define PIPEMISC_YUV420_ENABLE (1 << 27)
5678		-#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
	6020	+#define PIPEMISC_YUV420_ENABLE (1 << 27) /* glk+ */
	6021	+#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
	6022	+#define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */
5679	6023	#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
	6024	+#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
5680	6025	#define PIPEMISC_DITHER_BPC_MASK (7 << 5)
5681	6026	#define PIPEMISC_DITHER_8_BPC (0 << 5)
5682	6027	#define PIPEMISC_DITHER_10_BPC (1 << 5)
..	..	@@ -5686,6 +6031,12 @@
5686	6031	#define PIPEMISC_DITHER_TYPE_MASK (3 << 2)
5687	6032	#define PIPEMISC_DITHER_TYPE_SP (0 << 2)
5688	6033	#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
	6034	+
	6035	+/* Skylake+ pipe bottom (background) color */
	6036	+#define _SKL_BOTTOM_COLOR_A 0x70034
	6037	+#define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31)
	6038	+#define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30)
	6039	+#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
5689	6040
5690	6041	#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
5691	6042	#define PIPEB_LINE_COMPARE_INT_EN (1 << 29)
..	..	@@ -5738,7 +6089,7 @@
5738	6089	#define DPINVGTT_STATUS_MASK 0xff
5739	6090	#define DPINVGTT_STATUS_MASK_CHV 0xfff
5740	6091
5741		-#define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
	6092	+#define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
5742	6093	#define DSPARB_CSTART_MASK (0x7f << 7)
5743	6094	#define DSPARB_CSTART_SHIFT 7
5744	6095	#define DSPARB_BSTART_MASK (0x7f)
..	..	@@ -5773,7 +6124,7 @@
5773	6124	#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
5774	6125
5775	6126	/* pnv/gen4/g4x/vlv/chv */
5776		-#define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
	6127	+#define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
5777	6128	#define DSPFW_SR_SHIFT 23
5778	6129	#define DSPFW_SR_MASK (0x1ff << 23)
5779	6130	#define DSPFW_CURSORB_SHIFT 16
..	..	@@ -5784,7 +6135,7 @@
5784	6135	#define DSPFW_PLANEA_SHIFT 0
5785	6136	#define DSPFW_PLANEA_MASK (0x7f << 0)
5786	6137	#define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
5787		-#define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
	6138	+#define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
5788	6139	#define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
5789	6140	#define DSPFW_FBC_SR_SHIFT 28
5790	6141	#define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
..	..	@@ -5800,7 +6151,7 @@
5800	6151	#define DSPFW_SPRITEA_SHIFT 0
5801	6152	#define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
5802	6153	#define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
5803		-#define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
	6154	+#define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
5804	6155	#define DSPFW_HPLL_SR_EN (1 << 31)
5805	6156	#define PINEVIEW_SELF_REFRESH_EN (1 << 30)
5806	6157	#define DSPFW_CURSOR_SR_SHIFT 24
..	..	@@ -5966,9 +6317,10 @@
5966	6317	#define _CUR_WM_TRANS_A_0 0x70168
5967	6318	#define _CUR_WM_TRANS_B_0 0x71168
5968	6319	#define PLANE_WM_EN (1 << 31)
	6320	+#define PLANE_WM_IGNORE_LINES (1 << 30)
5969	6321	#define PLANE_WM_LINES_SHIFT 14
5970	6322	#define PLANE_WM_LINES_MASK 0x1f
5971		-#define PLANE_WM_BLOCKS_MASK 0x3ff
	6323	+#define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */
5972	6324
5973	6325	#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
5974	6326	#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
..	..	@@ -6092,7 +6444,7 @@
6092	6444	#define MCURSOR_PIPE_SELECT_SHIFT 28
6093	6445	#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
6094	6446	#define MCURSOR_GAMMA_ENABLE (1 << 26)
6095		-#define MCURSOR_PIPE_CSC_ENABLE (1 << 24)
	6447	+#define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
6096	6448	#define MCURSOR_ROTATE_180 (1 << 15)
6097	6449	#define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
6098	6450	#define _CURABASE 0x70084
..	..	@@ -6113,10 +6465,6 @@
6113	6465	#define _CURBBASE_IVB 0x71084
6114	6466	#define _CURBPOS_IVB 0x71088
6115	6467
6116		-#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
6117		- dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
6118		- dev_priv->info.display_mmio_offset)
6119		-
6120	6468	#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6121	6469	#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6122	6470	#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
..	..	@@ -6128,6 +6476,7 @@
6128	6476	#define CHV_CURSOR_C_OFFSET 0x700e0
6129	6477	#define IVB_CURSOR_B_OFFSET 0x71080
6130	6478	#define IVB_CURSOR_C_OFFSET 0x72080
	6479	+#define TGL_CURSOR_D_OFFSET 0x73080
6131	6480
6132	6481	/* Display A control */
6133	6482	#define _DSPACNTR 0x70180
..	..	@@ -6146,12 +6495,13 @@
6146	6495	#define DISPPLANE_RGBX101010 (0x8 << 26)
6147	6496	#define DISPPLANE_RGBA101010 (0x9 << 26)
6148	6497	#define DISPPLANE_BGRX101010 (0xa << 26)
	6498	+#define DISPPLANE_BGRA101010 (0xb << 26)
6149	6499	#define DISPPLANE_RGBX161616 (0xc << 26)
6150	6500	#define DISPPLANE_RGBX888 (0xe << 26)
6151	6501	#define DISPPLANE_RGBA888 (0xf << 26)
6152	6502	#define DISPPLANE_STEREO_ENABLE (1 << 25)
6153	6503	#define DISPPLANE_STEREO_DISABLE 0
6154		-#define DISPPLANE_PIPE_CSC_ENABLE (1 << 24)
	6504	+#define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
6155	6505	#define DISPPLANE_SEL_PIPE_SHIFT 24
6156	6506	#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
6157	6507	#define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
..	..	@@ -6174,6 +6524,7 @@
6174	6524	#define _DSPATILEOFF 0x701A4 /* 965+ only */
6175	6525	#define _DSPAOFFSET 0x701A4 /* HSW */
6176	6526	#define _DSPASURFLIVE 0x701AC
	6527	+#define _DSPAGAMC 0x701E0
6177	6528
6178	6529	#define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
6179	6530	#define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
..	..	@@ -6185,6 +6536,7 @@
6185	6536	#define DSPLINOFF(plane) DSPADDR(plane)
6186	6537	#define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
6187	6538	#define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
	6539	+#define DSPGAMC(plane, i) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
6188	6540
6189	6541	/* CHV pipe B blender and primary plane */
6190	6542	#define _CHV_BLEND_A 0x60a00
..	..	@@ -6220,35 +6572,39 @@
6220	6572	* [10:1f] all
6221	6573	* [30:32] all
6222	6574	*/
6223		-#define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
6224		-#define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
6225		-#define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
	6575	+#define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
	6576	+#define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
	6577	+#define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
6226	6578	#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
6227	6579
6228	6580	/* Pipe B */
6229		-#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
6230		-#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
6231		-#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
	6581	+#define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
	6582	+#define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
	6583	+#define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
6232	6584	#define _PIPEBFRAMEHIGH 0x71040
6233	6585	#define _PIPEBFRAMEPIXEL 0x71044
6234		-#define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
6235		-#define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
	6586	+#define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
	6587	+#define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
6236	6588
6237	6589
6238	6590	/* Display B control */
6239		-#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
	6591	+#define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
6240	6592	#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
6241	6593	#define DISPPLANE_ALPHA_TRANS_DISABLE 0
6242	6594	#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
6243	6595	#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
6244		-#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
6245		-#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
6246		-#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
6247		-#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
6248		-#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
6249		-#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
6250		-#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
6251		-#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
	6596	+#define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
	6597	+#define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
	6598	+#define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
	6599	+#define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
	6600	+#define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
	6601	+#define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
	6602	+#define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
	6603	+#define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
	6604	+
	6605	+/* ICL DSI 0 and 1 */
	6606	+#define _PIPEDSI0CONF 0x7b008
	6607	+#define _PIPEDSI1CONF 0x7b808
6252	6608
6253	6609	/* Sprite A control */
6254	6610	#define _DVSACNTR 0x72180
..	..	@@ -6283,6 +6639,7 @@
6283	6639	#define _DVSAKEYMAXVAL 0x721a0
6284	6640	#define _DVSATILEOFF 0x721a4
6285	6641	#define _DVSASURFLIVE 0x721ac
	6642	+#define _DVSAGAMC_G4X 0x721e0 /* g4x */
6286	6643	#define _DVSASCALE 0x72204
6287	6644	#define DVS_SCALE_ENABLE (1 << 31)
6288	6645	#define DVS_FILTER_MASK (3 << 29)
..	..	@@ -6291,7 +6648,8 @@
6291	6648	#define DVS_FILTER_SOFTENING (2 << 29)
6292	6649	#define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6293	6650	#define DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
6294		-#define _DVSAGAMC 0x72300
	6651	+#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
	6652	+#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
6295	6653
6296	6654	#define _DVSBCNTR 0x73180
6297	6655	#define _DVSBLINOFF 0x73184
..	..	@@ -6304,8 +6662,10 @@
6304	6662	#define _DVSBKEYMAXVAL 0x731a0
6305	6663	#define _DVSBTILEOFF 0x731a4
6306	6664	#define _DVSBSURFLIVE 0x731ac
	6665	+#define _DVSBGAMC_G4X 0x731e0 /* g4x */
6307	6666	#define _DVSBSCALE 0x73204
6308		-#define _DVSBGAMC 0x73300
	6667	+#define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
	6668	+#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
6309	6669
6310	6670	#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6311	6671	#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
..	..	@@ -6319,6 +6679,9 @@
6319	6679	#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6320	6680	#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6321	6681	#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
	6682	+#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
	6683	+#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
	6684	+#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
6322	6685
6323	6686	#define _SPRA_CTL 0x70280
6324	6687	#define SPRITE_ENABLE (1 << 31)
..	..	@@ -6343,7 +6706,7 @@
6343	6706	#define SPRITE_YUV_ORDER_VYUY (3 << 16)
6344	6707	#define SPRITE_ROTATE_180 (1 << 15)
6345	6708	#define SPRITE_TRICKLE_FEED_DISABLE (1 << 14)
6346		-#define SPRITE_INT_GAMMA_ENABLE (1 << 13)
	6709	+#define SPRITE_INT_GAMMA_DISABLE (1 << 13)
6347	6710	#define SPRITE_TILED (1 << 10)
6348	6711	#define SPRITE_DEST_KEY (1 << 2)
6349	6712	#define _SPRA_LINOFF 0x70284
..	..	@@ -6366,6 +6729,8 @@
6366	6729	#define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6367	6730	#define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)
6368	6731	#define _SPRA_GAMC 0x70400
	6732	+#define _SPRA_GAMC16 0x70440
	6733	+#define _SPRA_GAMC17 0x7044c
6369	6734
6370	6735	#define _SPRB_CTL 0x71280
6371	6736	#define _SPRB_LINOFF 0x71284
..	..	@@ -6381,6 +6746,8 @@
6381	6746	#define _SPRB_SURFLIVE 0x712ac
6382	6747	#define _SPRB_SCALE 0x71304
6383	6748	#define _SPRB_GAMC 0x71400
	6749	+#define _SPRB_GAMC16 0x71440
	6750	+#define _SPRB_GAMC17 0x7144c
6384	6751
6385	6752	#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6386	6753	#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
..	..	@@ -6394,19 +6761,24 @@
6394	6761	#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6395	6762	#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6396	6763	#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6397		-#define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
	6764	+#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
	6765	+#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
	6766	+#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
6398	6767	#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
6399	6768
6400	6769	#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
6401	6770	#define SP_ENABLE (1 << 31)
6402	6771	#define SP_GAMMA_ENABLE (1 << 30)
6403	6772	#define SP_PIXFORMAT_MASK (0xf << 26)
6404		-#define SP_FORMAT_YUV422 (0 << 26)
6405		-#define SP_FORMAT_BGR565 (5 << 26)
6406		-#define SP_FORMAT_BGRX8888 (6 << 26)
6407		-#define SP_FORMAT_BGRA8888 (7 << 26)
6408		-#define SP_FORMAT_RGBX1010102 (8 << 26)
6409		-#define SP_FORMAT_RGBA1010102 (9 << 26)
	6773	+#define SP_FORMAT_YUV422 (0x0 << 26)
	6774	+#define SP_FORMAT_8BPP (0x2 << 26)
	6775	+#define SP_FORMAT_BGR565 (0x5 << 26)
	6776	+#define SP_FORMAT_BGRX8888 (0x6 << 26)
	6777	+#define SP_FORMAT_BGRA8888 (0x7 << 26)
	6778	+#define SP_FORMAT_RGBX1010102 (0x8 << 26)
	6779	+#define SP_FORMAT_RGBA1010102 (0x9 << 26)
	6780	+#define SP_FORMAT_BGRX1010102 (0xa << 26) /* CHV pipe B */
	6781	+#define SP_FORMAT_BGRA1010102 (0xb << 26) /* CHV pipe B */
6410	6782	#define SP_FORMAT_RGBX8888 (0xe << 26)
6411	6783	#define SP_FORMAT_RGBA8888 (0xf << 26)
6412	6784	#define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
..	..	@@ -6437,7 +6809,7 @@
6437	6809	#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
6438	6810	#define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */
6439	6811	#define SP_SH_COS(x) (x) /* u3.7 */
6440		-#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
	6812	+#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
6441	6813
6442	6814	#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
6443	6815	#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
..	..	@@ -6452,10 +6824,12 @@
6452	6824	#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
6453	6825	#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
6454	6826	#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
6455		-#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
	6827	+#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
6456	6828
	6829	+#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
	6830	+ _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6457	6831	#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6458		- _MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
	6832	+ _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
6459	6833
6460	6834	#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
6461	6835	#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
..	..	@@ -6470,7 +6844,7 @@
6470	6844	#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
6471	6845	#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
6472	6846	#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
6473		-#define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC)
	6847	+#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
6474	6848
6475	6849	/*
6476	6850	* CHV pipe B sprite CSC
..	..	@@ -6525,18 +6899,28 @@
6525	6899	#define PLANE_CTL_FORMAT_YUV422 (0 << 24)
6526	6900	#define PLANE_CTL_FORMAT_NV12 (1 << 24)
6527	6901	#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
	6902	+#define PLANE_CTL_FORMAT_P010 (3 << 24)
6528	6903	#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
	6904	+#define PLANE_CTL_FORMAT_P012 (5 << 24)
6529	6905	#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
6530		-#define PLANE_CTL_FORMAT_AYUV (8 << 24)
	6906	+#define PLANE_CTL_FORMAT_P016 (7 << 24)
	6907	+#define PLANE_CTL_FORMAT_XYUV (8 << 24)
6531	6908	#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
6532	6909	#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
6533	6910	#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
6534	6911	#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
	6912	+#define PLANE_CTL_FORMAT_Y210 (1 << 23)
	6913	+#define PLANE_CTL_FORMAT_Y212 (3 << 23)
	6914	+#define PLANE_CTL_FORMAT_Y216 (5 << 23)
	6915	+#define PLANE_CTL_FORMAT_Y410 (7 << 23)
	6916	+#define PLANE_CTL_FORMAT_Y412 (9 << 23)
	6917	+#define PLANE_CTL_FORMAT_Y416 (0xb << 23)
6535	6918	#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
6536	6919	#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
6537	6920	#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
6538	6921	#define PLANE_CTL_ORDER_BGRX (0 << 20)
6539	6922	#define PLANE_CTL_ORDER_RGBX (1 << 20)
	6923	+#define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
6540	6924	#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
6541	6925	#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
6542	6926	#define PLANE_CTL_YUV422_YUYV (0 << 16)
..	..	@@ -6545,6 +6929,7 @@
6545	6929	#define PLANE_CTL_YUV422_VYUY (3 << 16)
6546	6930	#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
6547	6931	#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
	6932	+#define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
6548	6933	#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
6549	6934	#define PLANE_CTL_TILED_MASK (0x7 << 10)
6550	6935	#define PLANE_CTL_TILED_LINEAR (0 << 10)
..	..	@@ -6552,6 +6937,7 @@
6552	6937	#define PLANE_CTL_TILED_Y (4 << 10)
6553	6938	#define PLANE_CTL_TILED_YF (5 << 10)
6554	6939	#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
	6940	+#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
6555	6941	#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
6556	6942	#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
6557	6943	#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
..	..	@@ -6580,20 +6966,38 @@
6580	6966	#define _PLANE_KEYVAL_2_A 0x70294
6581	6967	#define _PLANE_KEYMSK_1_A 0x70198
6582	6968	#define _PLANE_KEYMSK_2_A 0x70298
	6969	+#define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31)
6583	6970	#define _PLANE_KEYMAX_1_A 0x701a0
6584	6971	#define _PLANE_KEYMAX_2_A 0x702a0
	6972	+#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
6585	6973	#define _PLANE_AUX_DIST_1_A 0x701c0
6586	6974	#define _PLANE_AUX_DIST_2_A 0x702c0
6587	6975	#define _PLANE_AUX_OFFSET_1_A 0x701c4
6588	6976	#define _PLANE_AUX_OFFSET_2_A 0x702c4
	6977	+#define _PLANE_CUS_CTL_1_A 0x701c8
	6978	+#define _PLANE_CUS_CTL_2_A 0x702c8
	6979	+#define PLANE_CUS_ENABLE (1 << 31)
	6980	+#define PLANE_CUS_PLANE_4_RKL (0 << 30)
	6981	+#define PLANE_CUS_PLANE_5_RKL (1 << 30)
	6982	+#define PLANE_CUS_PLANE_6 (0 << 30)
	6983	+#define PLANE_CUS_PLANE_7 (1 << 30)
	6984	+#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
	6985	+#define PLANE_CUS_HPHASE_0 (0 << 16)
	6986	+#define PLANE_CUS_HPHASE_0_25 (1 << 16)
	6987	+#define PLANE_CUS_HPHASE_0_5 (2 << 16)
	6988	+#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
	6989	+#define PLANE_CUS_VPHASE_0 (0 << 12)
	6990	+#define PLANE_CUS_VPHASE_0_25 (1 << 12)
	6991	+#define PLANE_CUS_VPHASE_0_5 (2 << 12)
6589	6992	#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
6590	6993	#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
6591	6994	#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
6592	6995	#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
6593	6996	#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
	6997	+#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
6594	6998	#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
6595	6999	#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
6596		-#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
	7000	+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17)
6597	7001	#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
6598	7002	#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
6599	7003	#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
..	..	@@ -6607,6 +7011,55 @@
6607	7011	#define _PLANE_NV12_BUF_CFG_1_A 0x70278
6608	7012	#define _PLANE_NV12_BUF_CFG_2_A 0x70378
6609	7013
	7014	+/* Input CSC Register Definitions */
	7015	+#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
	7016	+#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
	7017	+
	7018	+#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
	7019	+#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
	7020	+
	7021	+#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
	7022	+ _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
	7023	+ _PLANE_INPUT_CSC_RY_GY_1_B)
	7024	+#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
	7025	+ _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
	7026	+ _PLANE_INPUT_CSC_RY_GY_2_B)
	7027	+
	7028	+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
	7029	+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
	7030	+ _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
	7031	+
	7032	+#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
	7033	+#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
	7034	+
	7035	+#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
	7036	+#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
	7037	+
	7038	+#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
	7039	+ _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
	7040	+ _PLANE_INPUT_CSC_PREOFF_HI_1_B)
	7041	+#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
	7042	+ _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
	7043	+ _PLANE_INPUT_CSC_PREOFF_HI_2_B)
	7044	+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
	7045	+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
	7046	+ _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
	7047	+
	7048	+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
	7049	+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
	7050	+
	7051	+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
	7052	+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
	7053	+
	7054	+#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
	7055	+ _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
	7056	+ _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
	7057	+#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
	7058	+ _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
	7059	+ _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
	7060	+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
	7061	+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
	7062	+ _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
6610	7063
6611	7064	#define _PLANE_CTL_1_B 0x71180
6612	7065	#define _PLANE_CTL_2_B 0x71280
..	..	@@ -6686,8 +7139,7 @@
6686	7139
6687	7140	#define _PLANE_BUF_CFG_1_B 0x7127c
6688	7141	#define _PLANE_BUF_CFG_2_B 0x7137c
6689		-#define SKL_DDB_ENTRY_MASK 0x3FF
6690		-#define ICL_DDB_ENTRY_MASK 0x7FF
	7142	+#define DDB_ENTRY_MASK 0x7FF /* skl+: 10 bits, icl+ 11 bits */
6691	7143	#define DDB_ENTRY_END_SHIFT 16
6692	7144	#define _PLANE_BUF_CFG_1(pipe) \
6693	7145	_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
..	..	@@ -6723,6 +7175,15 @@
6723	7175	#define PLANE_AUX_OFFSET(pipe, plane) \
6724	7176	_MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
6725	7177
	7178	+#define _PLANE_CUS_CTL_1_B 0x711c8
	7179	+#define _PLANE_CUS_CTL_2_B 0x712c8
	7180	+#define _PLANE_CUS_CTL_1(pipe) \
	7181	+ _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
	7182	+#define _PLANE_CUS_CTL_2(pipe) \
	7183	+ _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
	7184	+#define PLANE_CUS_CTL(pipe, plane) \
	7185	+ _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
	7186	+
6726	7187	#define _PLANE_COLOR_CTL_1_B 0x711CC
6727	7188	#define _PLANE_COLOR_CTL_2_B 0x712CC
6728	7189	#define _PLANE_COLOR_CTL_3_B 0x713CC
..	..	@@ -6733,7 +7194,52 @@
6733	7194	#define PLANE_COLOR_CTL(pipe, plane) \
6734	7195	_MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
6735	7196
6736		-#/* SKL new cursor registers */
	7197	+#define _SEL_FETCH_PLANE_BASE_1_A 0x70890
	7198	+#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0
	7199	+#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0
	7200	+#define _SEL_FETCH_PLANE_BASE_4_A 0x708F0
	7201	+#define _SEL_FETCH_PLANE_BASE_5_A 0x70920
	7202	+#define _SEL_FETCH_PLANE_BASE_6_A 0x70940
	7203	+#define _SEL_FETCH_PLANE_BASE_7_A 0x70960
	7204	+#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880
	7205	+#define _SEL_FETCH_PLANE_BASE_1_B 0x71890
	7206	+
	7207	+#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
	7208	+ _SEL_FETCH_PLANE_BASE_1_A, \
	7209	+ _SEL_FETCH_PLANE_BASE_2_A, \
	7210	+ _SEL_FETCH_PLANE_BASE_3_A, \
	7211	+ _SEL_FETCH_PLANE_BASE_4_A, \
	7212	+ _SEL_FETCH_PLANE_BASE_5_A, \
	7213	+ _SEL_FETCH_PLANE_BASE_6_A, \
	7214	+ _SEL_FETCH_PLANE_BASE_7_A, \
	7215	+ _SEL_FETCH_PLANE_BASE_CUR_A)
	7216	+#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B)
	7217	+#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
	7218	+ _SEL_FETCH_PLANE_BASE_1_A + \
	7219	+ _SEL_FETCH_PLANE_BASE_A(plane))
	7220	+
	7221	+#define _SEL_FETCH_PLANE_CTL_1_A 0x70890
	7222	+#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
	7223	+ _SEL_FETCH_PLANE_CTL_1_A - \
	7224	+ _SEL_FETCH_PLANE_BASE_1_A)
	7225	+#define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
	7226	+
	7227	+#define _SEL_FETCH_PLANE_POS_1_A 0x70894
	7228	+#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
	7229	+ _SEL_FETCH_PLANE_POS_1_A - \
	7230	+ _SEL_FETCH_PLANE_BASE_1_A)
	7231	+
	7232	+#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898
	7233	+#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
	7234	+ _SEL_FETCH_PLANE_SIZE_1_A - \
	7235	+ _SEL_FETCH_PLANE_BASE_1_A)
	7236	+
	7237	+#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C
	7238	+#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
	7239	+ _SEL_FETCH_PLANE_OFFSET_1_A - \
	7240	+ _SEL_FETCH_PLANE_BASE_1_A)
	7241	+
	7242	+/* SKL new cursor registers */
6737	7243	#define _CUR_BUF_CFG_A 0x7017c
6738	7244	#define _CUR_BUF_CFG_B 0x7117c
6739	7245	#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
..	..	@@ -6876,11 +7382,12 @@
6876	7382	#define _PS_2B_CTRL 0x68A80
6877	7383	#define _PS_1C_CTRL 0x69180
6878	7384	#define PS_SCALER_EN (1 << 31)
6879		-#define PS_SCALER_MODE_MASK (3 << 28)
6880		-#define PS_SCALER_MODE_DYN (0 << 28)
6881		-#define PS_SCALER_MODE_HQ (1 << 28)
	7385	+#define SKL_PS_SCALER_MODE_MASK (3 << 28)
	7386	+#define SKL_PS_SCALER_MODE_DYN (0 << 28)
	7387	+#define SKL_PS_SCALER_MODE_HQ (1 << 28)
6882	7388	#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
6883	7389	#define PS_SCALER_MODE_PLANAR (1 << 29)
	7390	+#define PS_SCALER_MODE_NORMAL (0 << 29)
6884	7391	#define PS_PLANE_SEL_MASK (7 << 25)
6885	7392	#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
6886	7393	#define PS_FILTER_MASK (3 << 23)
..	..	@@ -6897,6 +7404,8 @@
6897	7404	#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
6898	7405	#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
6899	7406	#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
	7407	+#define PS_PLANE_Y_SEL_MASK (7 << 5)
	7408	+#define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
6900	7409
6901	7410	#define _PS_PWR_GATE_1A 0x68160
6902	7411	#define _PS_PWR_GATE_2A 0x68260
..	..	@@ -6991,16 +7500,34 @@
6991	7500	/* legacy palette */
6992	7501	#define _LGC_PALETTE_A 0x4a000
6993	7502	#define _LGC_PALETTE_B 0x4a800
	7503	+#define LGC_PALETTE_RED_MASK REG_GENMASK(23, 16)
	7504	+#define LGC_PALETTE_GREEN_MASK REG_GENMASK(15, 8)
	7505	+#define LGC_PALETTE_BLUE_MASK REG_GENMASK(7, 0)
6994	7506	#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
	7507	+
	7508	+/* ilk/snb precision palette */
	7509	+#define _PREC_PALETTE_A 0x4b000
	7510	+#define _PREC_PALETTE_B 0x4c000
	7511	+#define PREC_PALETTE_RED_MASK REG_GENMASK(29, 20)
	7512	+#define PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10)
	7513	+#define PREC_PALETTE_BLUE_MASK REG_GENMASK(9, 0)
	7514	+#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
	7515	+
	7516	+#define _PREC_PIPEAGCMAX 0x4d000
	7517	+#define _PREC_PIPEBGCMAX 0x4d010
	7518	+#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4)
6995	7519
6996	7520	#define _GAMMA_MODE_A 0x4a480
6997	7521	#define _GAMMA_MODE_B 0x4ac80
6998	7522	#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
6999		-#define GAMMA_MODE_MODE_MASK (3 << 0)
7000		-#define GAMMA_MODE_MODE_8BIT (0 << 0)
7001		-#define GAMMA_MODE_MODE_10BIT (1 << 0)
7002		-#define GAMMA_MODE_MODE_12BIT (2 << 0)
7003		-#define GAMMA_MODE_MODE_SPLIT (3 << 0)
	7523	+#define PRE_CSC_GAMMA_ENABLE (1 << 31)
	7524	+#define POST_CSC_GAMMA_ENABLE (1 << 30)
	7525	+#define GAMMA_MODE_MODE_MASK (3 << 0)
	7526	+#define GAMMA_MODE_MODE_8BIT (0 << 0)
	7527	+#define GAMMA_MODE_MODE_10BIT (1 << 0)
	7528	+#define GAMMA_MODE_MODE_12BIT (2 << 0)
	7529	+#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
	7530	+#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
7004	7531
7005	7532	/* DMC/CSR */
7006	7533	#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
..	..	@@ -7016,6 +7543,11 @@
7016	7543	#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
7017	7544	#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
7018	7545	#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
	7546	+#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
	7547	+#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
	7548	+
	7549	+#define TGL_DMC_DEBUG3 _MMIO(0x101090)
	7550	+#define DG1_DMC_DEBUG3 _MMIO(0x13415c)
7019	7551
7020	7552	/* Display Internal Timeout Register */
7021	7553	#define RM_TIMEOUT _MMIO(0x42060)
..	..	@@ -7099,8 +7631,8 @@
7099	7631	#define GEN8_GT_VECS_IRQ (1 << 6)
7100	7632	#define GEN8_GT_GUC_IRQ (1 << 5)
7101	7633	#define GEN8_GT_PM_IRQ (1 << 4)
7102		-#define GEN8_GT_VCS2_IRQ (1 << 3)
7103		-#define GEN8_GT_VCS1_IRQ (1 << 2)
	7634	+#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
	7635	+#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
7104	7636	#define GEN8_GT_BCS_IRQ (1 << 1)
7105	7637	#define GEN8_GT_RCS_IRQ (1 << 0)
7106	7638
..	..	@@ -7109,20 +7641,10 @@
7109	7641	#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
7110	7642	#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
7111	7643
7112		-#define GEN9_GUC_TO_HOST_INT_EVENT (1 << 31)
7113		-#define GEN9_GUC_EXEC_ERROR_EVENT (1 << 30)
7114		-#define GEN9_GUC_DISPLAY_EVENT (1 << 29)
7115		-#define GEN9_GUC_SEMA_SIGNAL_EVENT (1 << 28)
7116		-#define GEN9_GUC_IOMMU_MSG_EVENT (1 << 27)
7117		-#define GEN9_GUC_DB_RING_EVENT (1 << 26)
7118		-#define GEN9_GUC_DMA_DONE_EVENT (1 << 25)
7119		-#define GEN9_GUC_FATAL_ERROR_EVENT (1 << 24)
7120		-#define GEN9_GUC_NOTIFICATION_EVENT (1 << 23)
7121		-
7122	7644	#define GEN8_RCS_IRQ_SHIFT 0
7123	7645	#define GEN8_BCS_IRQ_SHIFT 16
7124		-#define GEN8_VCS1_IRQ_SHIFT 0
7125		-#define GEN8_VCS2_IRQ_SHIFT 16
	7646	+#define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
	7647	+#define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
7126	7648	#define GEN8_VECS_IRQ_SHIFT 0
7127	7649	#define GEN8_WD_IRQ_SHIFT 16
7128	7650
..	..	@@ -7142,6 +7664,9 @@
7142	7664	#define GEN8_PIPE_VSYNC (1 << 1)
7143	7665	#define GEN8_PIPE_VBLANK (1 << 0)
7144	7666	#define GEN9_PIPE_CURSOR_FAULT (1 << 11)
	7667	+#define GEN11_PIPE_PLANE7_FAULT (1 << 22)
	7668	+#define GEN11_PIPE_PLANE6_FAULT (1 << 21)
	7669	+#define GEN11_PIPE_PLANE5_FAULT (1 << 20)
7145	7670	#define GEN9_PIPE_PLANE4_FAULT (1 << 10)
7146	7671	#define GEN9_PIPE_PLANE3_FAULT (1 << 9)
7147	7672	#define GEN9_PIPE_PLANE2_FAULT (1 << 8)
..	..	@@ -7161,16 +7686,28 @@
7161	7686	GEN9_PIPE_PLANE3_FAULT \| \
7162	7687	GEN9_PIPE_PLANE2_FAULT \| \
7163	7688	GEN9_PIPE_PLANE1_FAULT)
	7689	+#define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
	7690	+ (GEN9_DE_PIPE_IRQ_FAULT_ERRORS \| \
	7691	+ GEN11_PIPE_PLANE7_FAULT \| \
	7692	+ GEN11_PIPE_PLANE6_FAULT \| \
	7693	+ GEN11_PIPE_PLANE5_FAULT)
	7694	+#define RKL_DE_PIPE_IRQ_FAULT_ERRORS \
	7695	+ (GEN9_DE_PIPE_IRQ_FAULT_ERRORS \| \
	7696	+ GEN11_PIPE_PLANE5_FAULT)
7164	7697
7165	7698	#define GEN8_DE_PORT_ISR _MMIO(0x44440)
7166	7699	#define GEN8_DE_PORT_IMR _MMIO(0x44444)
7167	7700	#define GEN8_DE_PORT_IIR _MMIO(0x44448)
7168	7701	#define GEN8_DE_PORT_IER _MMIO(0x4444c)
	7702	+#define DSI1_NON_TE (1 << 31)
	7703	+#define DSI0_NON_TE (1 << 30)
7169	7704	#define ICL_AUX_CHANNEL_E (1 << 29)
7170	7705	#define CNL_AUX_CHANNEL_F (1 << 28)
7171	7706	#define GEN9_AUX_CHANNEL_D (1 << 27)
7172	7707	#define GEN9_AUX_CHANNEL_C (1 << 26)
7173	7708	#define GEN9_AUX_CHANNEL_B (1 << 25)
	7709	+#define DSI1_TE (1 << 24)
	7710	+#define DSI0_TE (1 << 23)
7174	7711	#define BXT_DE_PORT_HP_DDIC (1 << 5)
7175	7712	#define BXT_DE_PORT_HP_DDIB (1 << 4)
7176	7713	#define BXT_DE_PORT_HP_DDIA (1 << 3)
..	..	@@ -7180,6 +7717,15 @@
7180	7717	#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
7181	7718	#define BXT_DE_PORT_GMBUS (1 << 1)
7182	7719	#define GEN8_AUX_CHANNEL_A (1 << 0)
	7720	+#define TGL_DE_PORT_AUX_USBC6 (1 << 13)
	7721	+#define TGL_DE_PORT_AUX_USBC5 (1 << 12)
	7722	+#define TGL_DE_PORT_AUX_USBC4 (1 << 11)
	7723	+#define TGL_DE_PORT_AUX_USBC3 (1 << 10)
	7724	+#define TGL_DE_PORT_AUX_USBC2 (1 << 9)
	7725	+#define TGL_DE_PORT_AUX_USBC1 (1 << 8)
	7726	+#define TGL_DE_PORT_AUX_DDIC (1 << 2)
	7727	+#define TGL_DE_PORT_AUX_DDIB (1 << 1)
	7728	+#define TGL_DE_PORT_AUX_DDIA (1 << 0)
7183	7729
7184	7730	#define GEN8_DE_MISC_ISR _MMIO(0x44460)
7185	7731	#define GEN8_DE_MISC_IMR _MMIO(0x44464)
..	..	@@ -7208,6 +7754,10 @@
7208	7754	#define GEN11_GT_DW1_IRQ (1 << 1)
7209	7755	#define GEN11_GT_DW0_IRQ (1 << 0)
7210	7756
	7757	+#define DG1_MSTR_UNIT_INTR _MMIO(0x190008)
	7758	+#define DG1_MSTR_IRQ REG_BIT(31)
	7759	+#define DG1_MSTR_UNIT(u) REG_BIT(u)
	7760	+
7211	7761	#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
7212	7762	#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
7213	7763	#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
..	..	@@ -7223,22 +7773,20 @@
7223	7773	#define GEN11_DE_HPD_IMR _MMIO(0x44474)
7224	7774	#define GEN11_DE_HPD_IIR _MMIO(0x44478)
7225	7775	#define GEN11_DE_HPD_IER _MMIO(0x4447c)
7226		-#define GEN11_TC4_HOTPLUG (1 << 19)
7227		-#define GEN11_TC3_HOTPLUG (1 << 18)
7228		-#define GEN11_TC2_HOTPLUG (1 << 17)
7229		-#define GEN11_TC1_HOTPLUG (1 << 16)
7230		-#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLUG \| \
7231		- GEN11_TC3_HOTPLUG \| \
7232		- GEN11_TC2_HOTPLUG \| \
7233		- GEN11_TC1_HOTPLUG)
7234		-#define GEN11_TBT4_HOTPLUG (1 << 3)
7235		-#define GEN11_TBT3_HOTPLUG (1 << 2)
7236		-#define GEN11_TBT2_HOTPLUG (1 << 1)
7237		-#define GEN11_TBT1_HOTPLUG (1 << 0)
7238		-#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG \| \
7239		- GEN11_TBT3_HOTPLUG \| \
7240		- GEN11_TBT2_HOTPLUG \| \
7241		- GEN11_TBT1_HOTPLUG)
	7776	+#define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
	7777	+#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(PORT_TC6) \| \
	7778	+ GEN11_TC_HOTPLUG(PORT_TC5) \| \
	7779	+ GEN11_TC_HOTPLUG(PORT_TC4) \| \
	7780	+ GEN11_TC_HOTPLUG(PORT_TC3) \| \
	7781	+ GEN11_TC_HOTPLUG(PORT_TC2) \| \
	7782	+ GEN11_TC_HOTPLUG(PORT_TC1))
	7783	+#define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
	7784	+#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(PORT_TC6) \| \
	7785	+ GEN11_TBT_HOTPLUG(PORT_TC5) \| \
	7786	+ GEN11_TBT_HOTPLUG(PORT_TC4) \| \
	7787	+ GEN11_TBT_HOTPLUG(PORT_TC3) \| \
	7788	+ GEN11_TBT_HOTPLUG(PORT_TC2) \| \
	7789	+ GEN11_TBT_HOTPLUG(PORT_TC1))
7242	7790
7243	7791	#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
7244	7792	#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
..	..	@@ -7269,6 +7817,9 @@
7269	7817	#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
7270	7818	#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
7271	7819	#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
	7820	+/* irq instances for OTHER_CLASS */
	7821	+#define OTHER_GUC_INSTANCE 0
	7822	+#define OTHER_GTPM_INSTANCE 1
7272	7823
7273	7824	#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
7274	7825
..	..	@@ -7294,6 +7845,9 @@
7294	7845	#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
7295	7846	#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
7296	7847
	7848	+#define ENGINE1_MASK REG_GENMASK(31, 16)
	7849	+#define ENGINE0_MASK REG_GENMASK(15, 0)
	7850	+
7297	7851	#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
7298	7852	/* Required on all Ironlake and Sandybridge according to the B-Spec. */
7299	7853	#define ILK_ELPIN_409_SELECT (1 << 25)
..	..	@@ -7308,6 +7862,10 @@
7308	7862	#define ILK_eDP_A_DISABLE (1 << 24)
7309	7863	#define HSW_CDCLK_LIMIT (1 << 24)
7310	7864	#define ILK_DESKTOP (1 << 23)
	7865	+#define HSW_CPU_SSC_ENABLE (1 << 21)
	7866	+
	7867	+#define FUSE_STRAP3 _MMIO(0x42020)
	7868	+#define HSW_REF_CLK_SELECT (1 << 1)
7311	7869
7312	7870	#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
7313	7871	#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
..	..	@@ -7320,11 +7878,13 @@
7320	7878	# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
7321	7879	# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
7322	7880
7323		-#define CHICKEN_PAR1_1 _MMIO(0x42080)
	7881	+#define CHICKEN_PAR1_1 _MMIO(0x42080)
	7882	+#define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16)
7324	7883	#define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
7325		-#define DPA_MASK_VBLANK_SRD (1 << 15)
7326		-#define FORCE_ARB_IDLE_PLANES (1 << 14)
7327		-#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
	7884	+#define DPA_MASK_VBLANK_SRD (1 << 15)
	7885	+#define FORCE_ARB_IDLE_PLANES (1 << 14)
	7886	+#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
	7887	+#define IGNORE_PSR2_HW_TRACKING (1 << 1)
7328	7888
7329	7889	#define CHICKEN_PAR2_1 _MMIO(0x42090)
7330	7890	#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
..	..	@@ -7345,9 +7905,19 @@
7345	7905	#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
7346	7906	#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
7347	7907
7348		-#define CHICKEN_TRANS_A 0x420c0
7349		-#define CHICKEN_TRANS_B 0x420c4
7350		-#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
	7908	+#define _CHICKEN_TRANS_A 0x420c0
	7909	+#define _CHICKEN_TRANS_B 0x420c4
	7910	+#define _CHICKEN_TRANS_C 0x420c8
	7911	+#define _CHICKEN_TRANS_EDP 0x420cc
	7912	+#define _CHICKEN_TRANS_D 0x420d8
	7913	+#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
	7914	+ [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
	7915	+ [TRANSCODER_A] = _CHICKEN_TRANS_A, \
	7916	+ [TRANSCODER_B] = _CHICKEN_TRANS_B, \
	7917	+ [TRANSCODER_C] = _CHICKEN_TRANS_C, \
	7918	+ [TRANSCODER_D] = _CHICKEN_TRANS_D))
	7919	+#define HSW_FRAME_START_DELAY_MASK (3 << 27)
	7920	+#define HSW_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
7351	7921	#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
7352	7922	#define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
7353	7923	#define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
..	..	@@ -7363,31 +7933,59 @@
7363	7933	#define DISP_ARB_CTL2 _MMIO(0x45004)
7364	7934	#define DISP_DATA_PARTITION_5_6 (1 << 6)
7365	7935	#define DISP_IPC_ENABLE (1 << 3)
7366		-#define DBUF_CTL _MMIO(0x45008)
7367		-#define DBUF_CTL_S1 _MMIO(0x45008)
7368		-#define DBUF_CTL_S2 _MMIO(0x44FE8)
	7936	+#define _DBUF_CTL_S1 0x45008
	7937	+#define _DBUF_CTL_S2 0x44FE8
	7938	+#define DBUF_CTL_S(slice) _MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2))
7369	7939	#define DBUF_POWER_REQUEST (1 << 31)
7370	7940	#define DBUF_POWER_STATE (1 << 30)
7371	7941	#define GEN7_MSG_CTL _MMIO(0x45010)
7372	7942	#define WAIT_FOR_PCH_RESET_ACK (1 << 1)
7373	7943	#define WAIT_FOR_PCH_FLR_ACK (1 << 0)
	7944	+
	7945	+#define _BW_BUDDY0_CTL 0x45130
	7946	+#define _BW_BUDDY1_CTL 0x45140
	7947	+#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
	7948	+ _BW_BUDDY0_CTL, \
	7949	+ _BW_BUDDY1_CTL))
	7950	+#define BW_BUDDY_DISABLE REG_BIT(31)
	7951	+#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
	7952	+#define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
	7953	+
	7954	+#define _BW_BUDDY0_PAGE_MASK 0x45134
	7955	+#define _BW_BUDDY1_PAGE_MASK 0x45144
	7956	+#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
	7957	+ _BW_BUDDY0_PAGE_MASK, \
	7958	+ _BW_BUDDY1_PAGE_MASK))
	7959	+
7374	7960	#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
7375	7961	#define RESET_PCH_HANDSHAKE_ENABLE (1 << 4)
7376	7962
7377	7963	#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
7378	7964	#define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
	7965	+#define CNL_DELAY_PMRSP (1 << 22)
7379	7966	#define MASK_WAKEMEM (1 << 13)
7380	7967	#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
7381	7968
	7969	+#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
	7970	+#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
	7971	+#define DCPR_MASK_LPMODE REG_BIT(26)
	7972	+#define DCPR_SEND_RESP_IMM REG_BIT(25)
	7973	+#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
	7974	+
7382	7975	#define SKL_DFSM _MMIO(0x51000)
7383		-#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
7384		-#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
7385		-#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
7386		-#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
7387		-#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
7388		-#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
7389		-#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
7390		-#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
	7976	+#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
	7977	+#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
	7978	+#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
	7979	+#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
	7980	+#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
	7981	+#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
	7982	+#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
	7983	+#define ICL_DFSM_DMC_DISABLE (1 << 23)
	7984	+#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
	7985	+#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
	7986	+#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
	7987	+#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
	7988	+#define CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
7391	7989
7392	7990	#define SKL_DSSM _MMIO(0x51004)
7393	7991	#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
..	..	@@ -7404,7 +8002,10 @@
7404	8002	#define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10)
7405	8003
7406	8004	#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
	8005	+#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
7407	8006	#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
	8007	+#define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
	8008	+
7408	8009	#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
7409	8010	#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
7410	8011	#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) \| ((lo) << 1))
..	..	@@ -7415,7 +8016,7 @@
7415	8016
7416	8017	/* GEN7 chicken */
7417	8018	#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
7418		- #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) \| (1 << 26))
	8019	+ #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10)
7419	8020	#define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
7420	8021
7421	8022	#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
..	..	@@ -7424,8 +8025,12 @@
7424	8025	#define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
7425	8026	#define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
7426	8027
	8028	+#define GEN8_L3CNTLREG _MMIO(0x7034)
	8029	+ #define GEN8_ERRDETBCTRL (1 << 9)
	8030	+
7427	8031	#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
7428	8032	#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
	8033	+ #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9)
7429	8034
7430	8035	#define HIZ_CHICKEN _MMIO(0x7018)
7431	8036	# define CHV_HZ_8X8_MODE_IN_1X (1 << 15)
..	..	@@ -7436,6 +8041,10 @@
7436	8041
7437	8042	#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
7438	8043	#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
	8044	+
	8045	+#define GEN7_SARCHKMD _MMIO(0xB000)
	8046	+#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
	8047	+#define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
7439	8048
7440	8049	#define GEN7_L3SQCREG1 _MMIO(0xB010)
7441	8050	#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
..	..	@@ -7464,6 +8073,9 @@
7464	8073
7465	8074	#define GEN7_L3SQCREG4 _MMIO(0xb034)
7466	8075	#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27)
	8076	+
	8077	+#define GEN11_SCRATCH2 _MMIO(0xb140)
	8078	+#define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19)
7467	8079
7468	8080	#define GEN8_L3SQCREG4 _MMIO(0xb118)
7469	8081	#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
..	..	@@ -7501,14 +8113,23 @@
7501	8113	#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2)
7502	8114
7503	8115	/GEN11 chicken /
7504		-#define _PIPEA_CHICKEN 0x70038
7505		-#define _PIPEB_CHICKEN 0x71038
7506		-#define _PIPEC_CHICKEN 0x72038
7507		-#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
7508		-#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
7509		- _PIPEB_CHICKEN)
	8116	+#define _PIPEA_CHICKEN 0x70038
	8117	+#define _PIPEB_CHICKEN 0x71038
	8118	+#define _PIPEC_CHICKEN 0x72038
	8119	+#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
	8120	+ _PIPEB_CHICKEN)
	8121	+#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
	8122	+#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
	8123	+
	8124	+#define FF_MODE2 _MMIO(0x6604)
	8125	+#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
	8126	+#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
	8127	+#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
	8128	+#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
7510	8129
7511	8130	/* PCH */
	8131	+
	8132	+#define PCH_DISPLAY_BASE 0xc0000u
7512	8133
7513	8134	/* south display engine interrupt: IBX */
7514	8135	#define SDE_AUDIO_POWER_D (1 << 27)
..	..	@@ -7599,20 +8220,25 @@
7599	8220	SDE_FDI_RXB_CPT \| \
7600	8221	SDE_FDI_RXA_CPT)
7601	8222
7602		-/* south display engine interrupt: ICP */
7603		-#define SDE_TC4_HOTPLUG_ICP (1 << 27)
7604		-#define SDE_TC3_HOTPLUG_ICP (1 << 26)
7605		-#define SDE_TC2_HOTPLUG_ICP (1 << 25)
7606		-#define SDE_TC1_HOTPLUG_ICP (1 << 24)
	8223	+/* south display engine interrupt: ICP/TGP */
7607	8224	#define SDE_GMBUS_ICP (1 << 23)
7608		-#define SDE_DDIB_HOTPLUG_ICP (1 << 17)
7609		-#define SDE_DDIA_HOTPLUG_ICP (1 << 16)
7610		-#define SDE_DDI_MASK_ICP (SDE_DDIB_HOTPLUG_ICP \| \
7611		- SDE_DDIA_HOTPLUG_ICP)
7612		-#define SDE_TC_MASK_ICP (SDE_TC4_HOTPLUG_ICP \| \
7613		- SDE_TC3_HOTPLUG_ICP \| \
7614		- SDE_TC2_HOTPLUG_ICP \| \
7615		- SDE_TC1_HOTPLUG_ICP)
	8225	+#define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))
	8226	+#define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
	8227	+#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(PORT_B) \| \
	8228	+ SDE_DDI_HOTPLUG_ICP(PORT_A))
	8229	+#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(PORT_TC4) \| \
	8230	+ SDE_TC_HOTPLUG_ICP(PORT_TC3) \| \
	8231	+ SDE_TC_HOTPLUG_ICP(PORT_TC2) \| \
	8232	+ SDE_TC_HOTPLUG_ICP(PORT_TC1))
	8233	+#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(PORT_C) \| \
	8234	+ SDE_DDI_HOTPLUG_ICP(PORT_B) \| \
	8235	+ SDE_DDI_HOTPLUG_ICP(PORT_A))
	8236	+#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(PORT_TC6) \| \
	8237	+ SDE_TC_HOTPLUG_ICP(PORT_TC5) \| \
	8238	+ SDE_TC_HOTPLUG_ICP(PORT_TC4) \| \
	8239	+ SDE_TC_HOTPLUG_ICP(PORT_TC3) \| \
	8240	+ SDE_TC_HOTPLUG_ICP(PORT_TC2) \| \
	8241	+ SDE_TC_HOTPLUG_ICP(PORT_TC1))
7616	8242
7617	8243	#define SDEISR _MMIO(0xc4000)
7618	8244	#define SDEIMR _MMIO(0xc4004)
..	..	@@ -7679,22 +8305,20 @@
7679	8305	* SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
7680	8306	*/
7681	8307
7682		-#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
7683		-#define ICP_DDIB_HPD_ENABLE (1 << 7)
7684		-#define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
7685		-#define ICP_DDIB_HPD_NO_DETECT (0 << 4)
7686		-#define ICP_DDIB_HPD_SHORT_DETECT (1 << 4)
7687		-#define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
7688		-#define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
7689		-#define ICP_DDIA_HPD_ENABLE (1 << 3)
7690		-#define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
7691		-#define ICP_DDIA_HPD_NO_DETECT (0 << 0)
7692		-#define ICP_DDIA_HPD_SHORT_DETECT (1 << 0)
7693		-#define ICP_DDIA_HPD_LONG_DETECT (2 << 0)
7694		-#define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0)
	8308	+#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
	8309	+#define SHOTPLUG_CTL_DDI_HPD_ENABLE(port) (0x8 << (4 * (port)))
	8310	+#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port) (0x3 << (4 * (port)))
	8311	+#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port) (0x0 << (4 * (port)))
	8312	+#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port) (0x1 << (4 * (port)))
	8313	+#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port) (0x2 << (4 * (port)))
	8314	+#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port) (0x3 << (4 * (port)))
7695	8315
7696	8316	#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
7697	8317	#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
	8318	+
	8319	+#define SHPD_FILTER_CNT _MMIO(0xc4038)
	8320	+#define SHPD_FILTER_CNT_500_ADJ 0x001D9
	8321	+
7698	8322	/* Icelake DSC Rate Control Range Parameter Registers */
7699	8323	#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
7700	8324	#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
..	..	@@ -7802,19 +8426,18 @@
7802	8426	#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
7803	8427	#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
7804	8428
7805		-#define PCH_GPIOA _MMIO(0xc5010)
7806		-#define PCH_GPIOB _MMIO(0xc5014)
7807		-#define PCH_GPIOC _MMIO(0xc5018)
7808		-#define PCH_GPIOD _MMIO(0xc501c)
7809		-#define PCH_GPIOE _MMIO(0xc5020)
7810		-#define PCH_GPIOF _MMIO(0xc5024)
7811		-
7812		-#define PCH_GMBUS0 _MMIO(0xc5100)
7813		-#define PCH_GMBUS1 _MMIO(0xc5104)
7814		-#define PCH_GMBUS2 _MMIO(0xc5108)
7815		-#define PCH_GMBUS3 _MMIO(0xc510c)
7816		-#define PCH_GMBUS4 _MMIO(0xc5110)
7817		-#define PCH_GMBUS5 _MMIO(0xc5120)
	8429	+#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) \| \
	8430	+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
	8431	+#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) \| \
	8432	+ ICP_TC_HPD_ENABLE(PORT_TC3) \| \
	8433	+ ICP_TC_HPD_ENABLE(PORT_TC2) \| \
	8434	+ ICP_TC_HPD_ENABLE(PORT_TC1))
	8435	+#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) \| \
	8436	+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) \| \
	8437	+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
	8438	+#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) \| \
	8439	+ ICP_TC_HPD_ENABLE(PORT_TC5) \| \
	8440	+ ICP_TC_HPD_ENABLE_MASK)
7818	8441
7819	8442	#define _PCH_DPLL_A 0xc6014
7820	8443	#define _PCH_DPLL_B 0xc6018
..	..	@@ -7862,8 +8485,7 @@
7862	8485	#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
7863	8486	#define CNP_RAWCLK_DIV(div) ((div) << 16)
7864	8487	#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
7865		-#define CNP_RAWCLK_FRAC(frac) ((frac) << 26)
7866		-#define ICP_RAWCLK_DEN(den) ((den) << 26)
	8488	+#define CNP_RAWCLK_DEN(den) ((den) << 26)
7867	8489	#define ICP_RAWCLK_NUM(num) ((num) << 11)
7868	8490
7869	8491	#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
..	..	@@ -7954,6 +8576,7 @@
7954	8576	#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
7955	8577	#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
7956	8578	#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
	8579	+#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
7957	8580	#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
7958	8581	#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
7959	8582	#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
..	..	@@ -7967,6 +8590,7 @@
7967	8590	#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
7968	8591	#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
7969	8592	#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
	8593	+#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
7970	8594	#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
7971	8595	#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
7972	8596	#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
..	..	@@ -7986,11 +8610,13 @@
7986	8610	#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
7987	8611
7988	8612	#define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
	8613	+#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
7989	8614	#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
7990	8615	#define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
7991	8616	#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
7992		-#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
	8617	+#define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
7993	8618	#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
	8619	+#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
7994	8620	#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
7995	8621	#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
7996	8622
..	..	@@ -8043,10 +8669,8 @@
8043	8669	#define TRANS_STATE_MASK (1 << 30)
8044	8670	#define TRANS_STATE_DISABLE (0 << 30)
8045	8671	#define TRANS_STATE_ENABLE (1 << 30)
8046		-#define TRANS_FSYNC_DELAY_HB1 (0 << 27)
8047		-#define TRANS_FSYNC_DELAY_HB2 (1 << 27)
8048		-#define TRANS_FSYNC_DELAY_HB3 (2 << 27)
8049		-#define TRANS_FSYNC_DELAY_HB4 (3 << 27)
	8672	+#define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */
	8673	+#define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
8050	8674	#define TRANS_INTERLACE_MASK (7 << 21)
8051	8675	#define TRANS_PROGRESSIVE (0 << 21)
8052	8676	#define TRANS_INTERLACED (3 << 21)
..	..	@@ -8067,6 +8691,7 @@
8067	8691	#define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
8068	8692	#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
8069	8693	#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
	8694	+#define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
8070	8695	#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
8071	8696	#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
8072	8697
..	..	@@ -8078,6 +8703,7 @@
8078	8703	#define FDI_BC_BIFURCATION_SELECT (1 << 12)
8079	8704	#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
8080	8705	#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
	8706	+#define SBCLK_RUN_REFCLK_DIS (1 << 7)
8081	8707	#define SPT_PWM_GRANULARITY (1 << 0)
8082	8708	#define SOUTH_CHICKEN2 _MMIO(0xc2004)
8083	8709	#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
..	..	@@ -8095,6 +8721,7 @@
8095	8721	#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
8096	8722	#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
8097	8723	#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
	8724	+#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
8098	8725	#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
8099	8726	#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
8100	8727	#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
..	..	@@ -8497,8 +9124,11 @@
8497	9124	#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
8498	9125	#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
8499	9126	#define GEN9_PG_ENABLE _MMIO(0xA210)
8500		-#define GEN9_RENDER_PG_ENABLE (1 << 0)
8501		-#define GEN9_MEDIA_PG_ENABLE (1 << 1)
	9127	+#define GEN9_RENDER_PG_ENABLE REG_BIT(0)
	9128	+#define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
	9129	+#define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
	9130	+#define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n))
	9131	+#define VDN_MFX_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n))
8502	9132	#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
8503	9133	#define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
8504	9134	#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
..	..	@@ -8513,13 +9143,20 @@
8513	9143	#define GEN6_PMIER _MMIO(0x4402C)
8514	9144	#define GEN6_PM_MBOX_EVENT (1 << 25)
8515	9145	#define GEN6_PM_THERMAL_EVENT (1 << 24)
	9146	+
	9147	+/*
	9148	+ * For Gen11 these are in the upper word of the GPM_WGBOXPERF
	9149	+ * registers. Shifting is handled on accessing the imr and ier.
	9150	+ */
8516	9151	#define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6)
8517	9152	#define GEN6_PM_RP_UP_THRESHOLD (1 << 5)
8518	9153	#define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4)
8519	9154	#define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2)
8520	9155	#define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1)
8521		-#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD \| \
8522		- GEN6_PM_RP_DOWN_THRESHOLD \| \
	9156	+#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED \| \
	9157	+ GEN6_PM_RP_UP_THRESHOLD \| \
	9158	+ GEN6_PM_RP_DOWN_EI_EXPIRED \| \
	9159	+ GEN6_PM_RP_DOWN_THRESHOLD \| \
8523	9160	GEN6_PM_RP_DOWN_TIMEOUT)
8524	9161
8525	9162	#define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
..	..	@@ -8555,6 +9192,9 @@
8555	9192	#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
8556	9193	#define GEN7_PCODE_TIMEOUT 0x2
8557	9194	#define GEN7_PCODE_ILLEGAL_DATA 0x3
	9195	+#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
	9196	+#define GEN11_PCODE_LOCKED 0x6
	9197	+#define GEN11_PCODE_REJECTED 0x11
8558	9198	#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
8559	9199	#define GEN6_PCODE_WRITE_RC6VIDS 0x4
8560	9200	#define GEN6_PCODE_READ_RC6VIDS 0x5
..	..	@@ -8573,10 +9213,21 @@
8573	9213	#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
8574	9214	#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
8575	9215	#define GEN6_READ_OC_PARAMS 0xc
	9216	+#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
	9217	+#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
	9218	+#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) \| (0x1 << 8))
	9219	+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
	9220	+#define ICL_PCODE_POINTS_RESTRICTED 0x0
	9221	+#define ICL_PCODE_POINTS_RESTRICTED_MASK 0x1
8576	9222	#define GEN6_PCODE_READ_D_COMP 0x10
8577	9223	#define GEN6_PCODE_WRITE_D_COMP 0x11
	9224	+#define ICL_PCODE_EXIT_TCCOLD 0x12
8578	9225	#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
8579	9226	#define DISPLAY_IPS_CONTROL 0x19
	9227	+#define TGL_PCODE_TCCOLD 0x26
	9228	+#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
	9229	+#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
	9230	+#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
8580	9231	/* See also IPS_CTL */
8581	9232	#define IPS_PCODE_CONTROL (1 << 30)
8582	9233	#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
..	..	@@ -8584,6 +9235,10 @@
8584	9235	#define GEN9_SAGV_DISABLE 0x0
8585	9236	#define GEN9_SAGV_IS_DISABLED 0x1
8586	9237	#define GEN9_SAGV_ENABLE 0x3
	9238	+#define DG1_PCODE_STATUS 0x7E
	9239	+#define DG1_UNCORE_GET_INIT_STATUS 0x0
	9240	+#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
	9241	+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
8587	9242	#define GEN6_PCODE_DATA _MMIO(0x138128)
8588	9243	#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
8589	9244	#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
..	..	@@ -8661,8 +9316,9 @@
8661	9316	#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
8662	9317	#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
8663	9318
8664		-#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
8665		-#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
	9319	+#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
	9320	+#define ENABLE_SMALLPL REG_BIT(15)
	9321	+#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
8666	9322
8667	9323	/* IVYBRIDGE DPF */
8668	9324	#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
..	..	@@ -8699,11 +9355,18 @@
8699	9355	#define THROTTLE_12_5 (7 << 2)
8700	9356	#define DISABLE_EARLY_EOT (1 << 1)
8701	9357
8702		-#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
	9358	+#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
	9359	+#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
	9360	+#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
	9361	+
8703	9362	#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
8704	9363	#define DOP_CLOCK_GATING_DISABLE (1 << 0)
8705	9364	#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
8706	9365	#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
	9366	+
	9367	+#define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
	9368	+#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
	9369	+#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
8707	9370
8708	9371	#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
8709	9372	#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
..	..	@@ -8724,7 +9387,7 @@
8724	9387	#define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2)
8725	9388
8726	9389	/* Audio */
8727		-#define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
	9390	+#define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
8728	9391	#define INTEL_AUDIO_DEVCL 0x808629FB
8729	9392	#define INTEL_AUDIO_DEVBLC 0x80862801
8730	9393	#define INTEL_AUDIO_DEVCTG 0x80862802
..	..	@@ -8805,37 +9468,41 @@
8805	9468	#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
8806	9469	#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
8807	9470	#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
	9471	+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16)
	9472	+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16)
	9473	+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16)
	9474	+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16)
8808	9475	#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
8809	9476
8810	9477	/* HSW Audio */
8811	9478	#define _HSW_AUD_CONFIG_A 0x65000
8812	9479	#define _HSW_AUD_CONFIG_B 0x65100
8813		-#define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
	9480	+#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
8814	9481
8815	9482	#define _HSW_AUD_MISC_CTRL_A 0x65010
8816	9483	#define _HSW_AUD_MISC_CTRL_B 0x65110
8817		-#define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
	9484	+#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
8818	9485
8819	9486	#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
8820	9487	#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
8821		-#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
	9488	+#define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
8822	9489	#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
8823	9490	#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
8824	9491	#define AUD_CONFIG_M_MASK 0xfffff
8825	9492
8826	9493	#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
8827	9494	#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
8828		-#define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
	9495	+#define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
8829	9496
8830	9497	/* Audio Digital Converter */
8831	9498	#define _HSW_AUD_DIG_CNVT_1 0x65080
8832	9499	#define _HSW_AUD_DIG_CNVT_2 0x65180
8833		-#define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
	9500	+#define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
8834	9501	#define DIP_PORT_SEL_MASK 0x3
8835	9502
8836	9503	#define _HSW_AUD_EDID_DATA_A 0x65050
8837	9504	#define _HSW_AUD_EDID_DATA_B 0x65150
8838		-#define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
	9505	+#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
8839	9506
8840	9507	#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
8841	9508	#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
..	..	@@ -8847,46 +9514,117 @@
8847	9514	#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
8848	9515	#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
8849	9516
8850		-/* HSW Power Wells */
8851		-#define _HSW_PWR_WELL_CTL1 0x45400
8852		-#define _HSW_PWR_WELL_CTL2 0x45404
8853		-#define _HSW_PWR_WELL_CTL3 0x45408
8854		-#define _HSW_PWR_WELL_CTL4 0x4540C
	9517	+#define AUD_FREQ_CNTRL _MMIO(0x65900)
	9518	+#define AUD_PIN_BUF_CTL _MMIO(0x48414)
	9519	+#define AUD_PIN_BUF_ENABLE REG_BIT(31)
8855	9520
8856		-#define _ICL_PWR_WELL_CTL_AUX1 0x45440
8857		-#define _ICL_PWR_WELL_CTL_AUX2 0x45444
8858		-#define _ICL_PWR_WELL_CTL_AUX4 0x4544C
	9521	+/* Display Audio Config Reg */
	9522	+#define AUD_CONFIG_BE _MMIO(0x65ef0)
	9523	+#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe)))
	9524	+#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe)))
	9525	+#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6)))
	9526	+#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6))
	9527	+#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6))
	9528	+#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6))
8859	9529
8860		-#define _ICL_PWR_WELL_CTL_DDI1 0x45450
8861		-#define _ICL_PWR_WELL_CTL_DDI2 0x45454
8862		-#define _ICL_PWR_WELL_CTL_DDI4 0x4545C
	9530	+#define HBLANK_START_COUNT_8 0
	9531	+#define HBLANK_START_COUNT_16 1
	9532	+#define HBLANK_START_COUNT_32 2
	9533	+#define HBLANK_START_COUNT_64 3
	9534	+#define HBLANK_START_COUNT_96 4
	9535	+#define HBLANK_START_COUNT_128 5
8863	9536
8864	9537	/*
8865		- * Each power well control register contains up to 16 (request, status) HW
8866		- * flag tuples. The register index and HW flag shift is determined by the
8867		- * power well ID (see i915_power_well_id). There are 4 possible sources of
8868		- * power well requests each source having its own set of control registers:
8869		- * BIOS, DRIVER, KVMR, DEBUG.
	9538	+ * HSW - ICL power wells
	9539	+ *
	9540	+ * Platforms have up to 3 power well control register sets, each set
	9541	+ * controlling up to 16 power wells via a request/status HW flag tuple:
	9542	+ * - main (HSW_PWR_WELL_CTL[1-4])
	9543	+ * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
	9544	+ * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
	9545	+ * Each control register set consists of up to 4 registers used by different
	9546	+ * sources that can request a power well to be enabled:
	9547	+ * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
	9548	+ * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
	9549	+ * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
	9550	+ * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
8870	9551	*/
8871		-#define _HSW_PW_REG_IDX(pw) ((pw) >> 4)
8872		-#define _HSW_PW_SHIFT(pw) (((pw) & 0xf) * 2)
8873		-#define HSW_PWR_WELL_CTL_BIOS(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8874		- _HSW_PWR_WELL_CTL1, \
8875		- _ICL_PWR_WELL_CTL_AUX1, \
8876		- _ICL_PWR_WELL_CTL_DDI1))
8877		-#define HSW_PWR_WELL_CTL_DRIVER(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8878		- _HSW_PWR_WELL_CTL2, \
8879		- _ICL_PWR_WELL_CTL_AUX2, \
8880		- _ICL_PWR_WELL_CTL_DDI2))
8881		-/* KVMR doesn't have a reg for AUX or DDI power well control */
8882		-#define HSW_PWR_WELL_CTL_KVMR _MMIO(_HSW_PWR_WELL_CTL3)
8883		-#define HSW_PWR_WELL_CTL_DEBUG(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8884		- _HSW_PWR_WELL_CTL4, \
8885		- _ICL_PWR_WELL_CTL_AUX4, \
8886		- _ICL_PWR_WELL_CTL_DDI4))
	9552	+#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
	9553	+#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
	9554	+#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
	9555	+#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
	9556	+#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
	9557	+#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
8887	9558
8888		-#define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1))
8889		-#define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw))
	9559	+/* HSW/BDW power well */
	9560	+#define HSW_PW_CTL_IDX_GLOBAL 15
	9561	+
	9562	+/* SKL/BXT/GLK/CNL power wells */
	9563	+#define SKL_PW_CTL_IDX_PW_2 15
	9564	+#define SKL_PW_CTL_IDX_PW_1 14
	9565	+#define CNL_PW_CTL_IDX_AUX_F 12
	9566	+#define CNL_PW_CTL_IDX_AUX_D 11
	9567	+#define GLK_PW_CTL_IDX_AUX_C 10
	9568	+#define GLK_PW_CTL_IDX_AUX_B 9
	9569	+#define GLK_PW_CTL_IDX_AUX_A 8
	9570	+#define CNL_PW_CTL_IDX_DDI_F 6
	9571	+#define SKL_PW_CTL_IDX_DDI_D 4
	9572	+#define SKL_PW_CTL_IDX_DDI_C 3
	9573	+#define SKL_PW_CTL_IDX_DDI_B 2
	9574	+#define SKL_PW_CTL_IDX_DDI_A_E 1
	9575	+#define GLK_PW_CTL_IDX_DDI_A 1
	9576	+#define SKL_PW_CTL_IDX_MISC_IO 0
	9577	+
	9578	+/* ICL/TGL - power wells */
	9579	+#define TGL_PW_CTL_IDX_PW_5 4
	9580	+#define ICL_PW_CTL_IDX_PW_4 3
	9581	+#define ICL_PW_CTL_IDX_PW_3 2
	9582	+#define ICL_PW_CTL_IDX_PW_2 1
	9583	+#define ICL_PW_CTL_IDX_PW_1 0
	9584	+
	9585	+#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
	9586	+#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
	9587	+#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
	9588	+#define TGL_PW_CTL_IDX_AUX_TBT6 14
	9589	+#define TGL_PW_CTL_IDX_AUX_TBT5 13
	9590	+#define TGL_PW_CTL_IDX_AUX_TBT4 12
	9591	+#define ICL_PW_CTL_IDX_AUX_TBT4 11
	9592	+#define TGL_PW_CTL_IDX_AUX_TBT3 11
	9593	+#define ICL_PW_CTL_IDX_AUX_TBT3 10
	9594	+#define TGL_PW_CTL_IDX_AUX_TBT2 10
	9595	+#define ICL_PW_CTL_IDX_AUX_TBT2 9
	9596	+#define TGL_PW_CTL_IDX_AUX_TBT1 9
	9597	+#define ICL_PW_CTL_IDX_AUX_TBT1 8
	9598	+#define TGL_PW_CTL_IDX_AUX_TC6 8
	9599	+#define TGL_PW_CTL_IDX_AUX_TC5 7
	9600	+#define TGL_PW_CTL_IDX_AUX_TC4 6
	9601	+#define ICL_PW_CTL_IDX_AUX_F 5
	9602	+#define TGL_PW_CTL_IDX_AUX_TC3 5
	9603	+#define ICL_PW_CTL_IDX_AUX_E 4
	9604	+#define TGL_PW_CTL_IDX_AUX_TC2 4
	9605	+#define ICL_PW_CTL_IDX_AUX_D 3
	9606	+#define TGL_PW_CTL_IDX_AUX_TC1 3
	9607	+#define ICL_PW_CTL_IDX_AUX_C 2
	9608	+#define ICL_PW_CTL_IDX_AUX_B 1
	9609	+#define ICL_PW_CTL_IDX_AUX_A 0
	9610	+
	9611	+#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
	9612	+#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
	9613	+#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
	9614	+#define TGL_PW_CTL_IDX_DDI_TC6 8
	9615	+#define TGL_PW_CTL_IDX_DDI_TC5 7
	9616	+#define TGL_PW_CTL_IDX_DDI_TC4 6
	9617	+#define ICL_PW_CTL_IDX_DDI_F 5
	9618	+#define TGL_PW_CTL_IDX_DDI_TC3 5
	9619	+#define ICL_PW_CTL_IDX_DDI_E 4
	9620	+#define TGL_PW_CTL_IDX_DDI_TC2 4
	9621	+#define ICL_PW_CTL_IDX_DDI_D 3
	9622	+#define TGL_PW_CTL_IDX_DDI_TC1 3
	9623	+#define ICL_PW_CTL_IDX_DDI_C 2
	9624	+#define ICL_PW_CTL_IDX_DDI_B 1
	9625	+#define ICL_PW_CTL_IDX_DDI_A 0
	9626	+
	9627	+/* HSW - power well misc debug registers */
8890	9628	#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
8891	9629	#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
8892	9630	#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
..	..	@@ -8898,28 +9636,47 @@
8898	9636	SKL_PG0,
8899	9637	SKL_PG1,
8900	9638	SKL_PG2,
	9639	+ ICL_PG3,
	9640	+ ICL_PG4,
8901	9641	};
8902	9642
8903	9643	#define SKL_FUSE_STATUS _MMIO(0x42000)
8904	9644	#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
8905		-/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */
8906		-#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1)
8907		-/* PG0 (HW control->no power well ID), PG1..PG4 (ICL_DISP_PW1..ICL_DISP_PW4) */
8908		-#define ICL_PW_TO_PG(pw) ((pw) - ICL_DISP_PW_1 + SKL_PG1)
	9645	+/*
	9646	+ * PG0 is HW controlled, so doesn't have a corresponding power well control knob
	9647	+ * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
	9648	+ */
	9649	+#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
	9650	+ ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
	9651	+/*
	9652	+ * PG0 is HW controlled, so doesn't have a corresponding power well control knob
	9653	+ * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
	9654	+ */
	9655	+#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
	9656	+ ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
8909	9657	#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
8910	9658
8911		-#define _CNL_AUX_REG_IDX(pw) ((pw) - 9)
	9659	+#define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
8912	9660	#define _CNL_AUX_ANAOVRD1_B 0x162250
8913	9661	#define _CNL_AUX_ANAOVRD1_C 0x162210
8914	9662	#define _CNL_AUX_ANAOVRD1_D 0x1622D0
8915	9663	#define _CNL_AUX_ANAOVRD1_F 0x162A90
8916		-#define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \
	9664	+#define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
8917	9665	_CNL_AUX_ANAOVRD1_B, \
8918	9666	_CNL_AUX_ANAOVRD1_C, \
8919	9667	_CNL_AUX_ANAOVRD1_D, \
8920	9668	_CNL_AUX_ANAOVRD1_F))
8921	9669	#define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
8922	9670	#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
	9671	+
	9672	+#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
	9673	+#define _ICL_AUX_ANAOVRD1_A 0x162398
	9674	+#define _ICL_AUX_ANAOVRD1_B 0x6C398
	9675	+#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
	9676	+ _ICL_AUX_ANAOVRD1_A, \
	9677	+ _ICL_AUX_ANAOVRD1_B))
	9678	+#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
	9679	+#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
8923	9680
8924	9681	/* HDCP Key Registers */
8925	9682	#define HDCP_KEY_CONF _MMIO(0x66c00)
..	..	@@ -8937,12 +9694,20 @@
8937	9694
8938	9695	/* HDCP Repeater Registers */
8939	9696	#define HDCP_REP_CTL _MMIO(0x66d00)
	9697	+#define HDCP_TRANSA_REP_PRESENT BIT(31)
	9698	+#define HDCP_TRANSB_REP_PRESENT BIT(30)
	9699	+#define HDCP_TRANSC_REP_PRESENT BIT(29)
	9700	+#define HDCP_TRANSD_REP_PRESENT BIT(28)
8940	9701	#define HDCP_DDIB_REP_PRESENT BIT(30)
8941	9702	#define HDCP_DDIA_REP_PRESENT BIT(29)
8942	9703	#define HDCP_DDIC_REP_PRESENT BIT(28)
8943	9704	#define HDCP_DDID_REP_PRESENT BIT(27)
8944	9705	#define HDCP_DDIF_REP_PRESENT BIT(26)
8945	9706	#define HDCP_DDIE_REP_PRESENT BIT(25)
	9707	+#define HDCP_TRANSA_SHA1_M0 (1 << 20)
	9708	+#define HDCP_TRANSB_SHA1_M0 (2 << 20)
	9709	+#define HDCP_TRANSC_SHA1_M0 (3 << 20)
	9710	+#define HDCP_TRANSD_SHA1_M0 (4 << 20)
8946	9711	#define HDCP_DDIB_SHA1_M0 (1 << 20)
8947	9712	#define HDCP_DDIA_SHA1_M0 (2 << 20)
8948	9713	#define HDCP_DDIC_SHA1_M0 (3 << 20)
..	..	@@ -8982,15 +9747,92 @@
8982	9747	_PORTE_HDCP_AUTHENC, \
8983	9748	_PORTF_HDCP_AUTHENC) + (x))
8984	9749	#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
	9750	+#define _TRANSA_HDCP_CONF 0x66400
	9751	+#define _TRANSB_HDCP_CONF 0x66500
	9752	+#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
	9753	+ _TRANSB_HDCP_CONF)
	9754	+#define HDCP_CONF(dev_priv, trans, port) \
	9755	+ (INTEL_GEN(dev_priv) >= 12 ? \
	9756	+ TRANS_HDCP_CONF(trans) : \
	9757	+ PORT_HDCP_CONF(port))
	9758	+
8985	9759	#define HDCP_CONF_CAPTURE_AN BIT(0)
8986	9760	#define HDCP_CONF_AUTH_AND_ENC (BIT(1) \| BIT(0))
8987	9761	#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
	9762	+#define _TRANSA_HDCP_ANINIT 0x66404
	9763	+#define _TRANSB_HDCP_ANINIT 0x66504
	9764	+#define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \
	9765	+ _TRANSA_HDCP_ANINIT, \
	9766	+ _TRANSB_HDCP_ANINIT)
	9767	+#define HDCP_ANINIT(dev_priv, trans, port) \
	9768	+ (INTEL_GEN(dev_priv) >= 12 ? \
	9769	+ TRANS_HDCP_ANINIT(trans) : \
	9770	+ PORT_HDCP_ANINIT(port))
	9771	+
8988	9772	#define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
	9773	+#define _TRANSA_HDCP_ANLO 0x66408
	9774	+#define _TRANSB_HDCP_ANLO 0x66508
	9775	+#define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
	9776	+ _TRANSB_HDCP_ANLO)
	9777	+#define HDCP_ANLO(dev_priv, trans, port) \
	9778	+ (INTEL_GEN(dev_priv) >= 12 ? \
	9779	+ TRANS_HDCP_ANLO(trans) : \
	9780	+ PORT_HDCP_ANLO(port))
	9781	+
8989	9782	#define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
	9783	+#define _TRANSA_HDCP_ANHI 0x6640C
	9784	+#define _TRANSB_HDCP_ANHI 0x6650C
	9785	+#define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
	9786	+ _TRANSB_HDCP_ANHI)
	9787	+#define HDCP_ANHI(dev_priv, trans, port) \
	9788	+ (INTEL_GEN(dev_priv) >= 12 ? \
	9789	+ TRANS_HDCP_ANHI(trans) : \
	9790	+ PORT_HDCP_ANHI(port))
	9791	+
8990	9792	#define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
	9793	+#define _TRANSA_HDCP_BKSVLO 0x66410
	9794	+#define _TRANSB_HDCP_BKSVLO 0x66510
	9795	+#define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \
	9796	+ _TRANSA_HDCP_BKSVLO, \
	9797	+ _TRANSB_HDCP_BKSVLO)
	9798	+#define HDCP_BKSVLO(dev_priv, trans, port) \
	9799	+ (INTEL_GEN(dev_priv) >= 12 ? \
	9800	+ TRANS_HDCP_BKSVLO(trans) : \
	9801	+ PORT_HDCP_BKSVLO(port))
	9802	+
8991	9803	#define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
	9804	+#define _TRANSA_HDCP_BKSVHI 0x66414
	9805	+#define _TRANSB_HDCP_BKSVHI 0x66514
	9806	+#define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \
	9807	+ _TRANSA_HDCP_BKSVHI, \
	9808	+ _TRANSB_HDCP_BKSVHI)
	9809	+#define HDCP_BKSVHI(dev_priv, trans, port) \
	9810	+ (INTEL_GEN(dev_priv) >= 12 ? \
	9811	+ TRANS_HDCP_BKSVHI(trans) : \
	9812	+ PORT_HDCP_BKSVHI(port))
	9813	+
8992	9814	#define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
	9815	+#define _TRANSA_HDCP_RPRIME 0x66418
	9816	+#define _TRANSB_HDCP_RPRIME 0x66518
	9817	+#define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \
	9818	+ _TRANSA_HDCP_RPRIME, \
	9819	+ _TRANSB_HDCP_RPRIME)
	9820	+#define HDCP_RPRIME(dev_priv, trans, port) \
	9821	+ (INTEL_GEN(dev_priv) >= 12 ? \
	9822	+ TRANS_HDCP_RPRIME(trans) : \
	9823	+ PORT_HDCP_RPRIME(port))
	9824	+
8993	9825	#define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
	9826	+#define _TRANSA_HDCP_STATUS 0x6641C
	9827	+#define _TRANSB_HDCP_STATUS 0x6651C
	9828	+#define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \
	9829	+ _TRANSA_HDCP_STATUS, \
	9830	+ _TRANSB_HDCP_STATUS)
	9831	+#define HDCP_STATUS(dev_priv, trans, port) \
	9832	+ (INTEL_GEN(dev_priv) >= 12 ? \
	9833	+ TRANS_HDCP_STATUS(trans) : \
	9834	+ PORT_HDCP_STATUS(port))
	9835	+
8994	9836	#define HDCP_STATUS_STREAM_A_ENC BIT(31)
8995	9837	#define HDCP_STATUS_STREAM_B_ENC BIT(30)
8996	9838	#define HDCP_STATUS_STREAM_C_ENC BIT(29)
..	..	@@ -9003,19 +9845,79 @@
9003	9845	#define HDCP_STATUS_CIPHER BIT(16)
9004	9846	#define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff)
9005	9847
	9848	+/* HDCP2.2 Registers */
	9849	+#define _PORTA_HDCP2_BASE 0x66800
	9850	+#define _PORTB_HDCP2_BASE 0x66500
	9851	+#define _PORTC_HDCP2_BASE 0x66600
	9852	+#define _PORTD_HDCP2_BASE 0x66700
	9853	+#define _PORTE_HDCP2_BASE 0x66A00
	9854	+#define _PORTF_HDCP2_BASE 0x66900
	9855	+#define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \
	9856	+ _PORTA_HDCP2_BASE, \
	9857	+ _PORTB_HDCP2_BASE, \
	9858	+ _PORTC_HDCP2_BASE, \
	9859	+ _PORTD_HDCP2_BASE, \
	9860	+ _PORTE_HDCP2_BASE, \
	9861	+ _PORTF_HDCP2_BASE) + (x))
	9862	+#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
	9863	+#define _TRANSA_HDCP2_AUTH 0x66498
	9864	+#define _TRANSB_HDCP2_AUTH 0x66598
	9865	+#define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \
	9866	+ _TRANSB_HDCP2_AUTH)
	9867	+#define AUTH_LINK_AUTHENTICATED BIT(31)
	9868	+#define AUTH_LINK_TYPE BIT(30)
	9869	+#define AUTH_FORCE_CLR_INPUTCTR BIT(19)
	9870	+#define AUTH_CLR_KEYS BIT(18)
	9871	+#define HDCP2_AUTH(dev_priv, trans, port) \
	9872	+ (INTEL_GEN(dev_priv) >= 12 ? \
	9873	+ TRANS_HDCP2_AUTH(trans) : \
	9874	+ PORT_HDCP2_AUTH(port))
	9875	+
	9876	+#define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0)
	9877	+#define _TRANSA_HDCP2_CTL 0x664B0
	9878	+#define _TRANSB_HDCP2_CTL 0x665B0
	9879	+#define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \
	9880	+ _TRANSB_HDCP2_CTL)
	9881	+#define CTL_LINK_ENCRYPTION_REQ BIT(31)
	9882	+#define HDCP2_CTL(dev_priv, trans, port) \
	9883	+ (INTEL_GEN(dev_priv) >= 12 ? \
	9884	+ TRANS_HDCP2_CTL(trans) : \
	9885	+ PORT_HDCP2_CTL(port))
	9886	+
	9887	+#define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4)
	9888	+#define _TRANSA_HDCP2_STATUS 0x664B4
	9889	+#define _TRANSB_HDCP2_STATUS 0x665B4
	9890	+#define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \
	9891	+ _TRANSA_HDCP2_STATUS, \
	9892	+ _TRANSB_HDCP2_STATUS)
	9893	+#define LINK_TYPE_STATUS BIT(22)
	9894	+#define LINK_AUTH_STATUS BIT(21)
	9895	+#define LINK_ENCRYPTION_STATUS BIT(20)
	9896	+#define HDCP2_STATUS(dev_priv, trans, port) \
	9897	+ (INTEL_GEN(dev_priv) >= 12 ? \
	9898	+ TRANS_HDCP2_STATUS(trans) : \
	9899	+ PORT_HDCP2_STATUS(port))
	9900	+
9006	9901	/* Per-pipe DDI Function Control */
9007	9902	#define _TRANS_DDI_FUNC_CTL_A 0x60400
9008	9903	#define _TRANS_DDI_FUNC_CTL_B 0x61400
9009	9904	#define _TRANS_DDI_FUNC_CTL_C 0x62400
	9905	+#define _TRANS_DDI_FUNC_CTL_D 0x63400
9010	9906	#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
	9907	+#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
	9908	+#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
9011	9909	#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
9012	9910
9013	9911	#define TRANS_DDI_FUNC_ENABLE (1 << 31)
9014	9912	/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
9015		-#define TRANS_DDI_PORT_MASK (7 << 28)
9016	9913	#define TRANS_DDI_PORT_SHIFT 28
9017		-#define TRANS_DDI_SELECT_PORT(x) ((x) << 28)
9018		-#define TRANS_DDI_PORT_NONE (0 << 28)
	9914	+#define TGL_TRANS_DDI_PORT_SHIFT 27
	9915	+#define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
	9916	+#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
	9917	+#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
	9918	+#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
	9919	+#define TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) (((val) & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT)
	9920	+#define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) ((((val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
9019	9921	#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
9020	9922	#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
9021	9923	#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
..	..	@@ -9027,13 +9929,20 @@
9027	9929	#define TRANS_DDI_BPC_10 (1 << 20)
9028	9930	#define TRANS_DDI_BPC_6 (2 << 20)
9029	9931	#define TRANS_DDI_BPC_12 (3 << 20)
	9932	+#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) /* bdw-cnl */
	9933	+#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
9030	9934	#define TRANS_DDI_PVSYNC (1 << 17)
9031	9935	#define TRANS_DDI_PHSYNC (1 << 16)
	9936	+#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) /* bdw-cnl */
9032	9937	#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
9033	9938	#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
9034	9939	#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
9035	9940	#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
9036	9941	#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
	9942	+#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
	9943	+#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
	9944	+#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
	9945	+ REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
9037	9946	#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
9038	9947	#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
9039	9948	#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
..	..	@@ -9045,11 +9954,25 @@
9045	9954	\| TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
9046	9955	\| TRANS_DDI_HDMI_SCRAMBLING)
9047	9956
	9957	+#define _TRANS_DDI_FUNC_CTL2_A 0x60404
	9958	+#define _TRANS_DDI_FUNC_CTL2_B 0x61404
	9959	+#define _TRANS_DDI_FUNC_CTL2_C 0x62404
	9960	+#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
	9961	+#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
	9962	+#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
	9963	+#define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A)
	9964	+#define PORT_SYNC_MODE_ENABLE REG_BIT(4)
	9965	+#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
	9966	+#define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
	9967	+
9048	9968	/* DisplayPort Transport Control */
9049	9969	#define _DP_TP_CTL_A 0x64040
9050	9970	#define _DP_TP_CTL_B 0x64140
	9971	+#define _TGL_DP_TP_CTL_A 0x60540
9051	9972	#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
	9973	+#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
9052	9974	#define DP_TP_CTL_ENABLE (1 << 31)
	9975	+#define DP_TP_CTL_FEC_ENABLE (1 << 30)
9053	9976	#define DP_TP_CTL_MODE_SST (0 << 27)
9054	9977	#define DP_TP_CTL_MODE_MST (1 << 27)
9055	9978	#define DP_TP_CTL_FORCE_ACT (1 << 25)
..	..	@@ -9067,7 +9990,10 @@
9067	9990	/* DisplayPort Transport Status */
9068	9991	#define _DP_TP_STATUS_A 0x64044
9069	9992	#define _DP_TP_STATUS_B 0x64144
	9993	+#define _TGL_DP_TP_STATUS_A 0x60544
9070	9994	#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
	9995	+#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
	9996	+#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
9071	9997	#define DP_TP_STATUS_IDLE_DONE (1 << 25)
9072	9998	#define DP_TP_STATUS_ACT_SENT (1 << 24)
9073	9999	#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
..	..	@@ -9097,6 +10023,24 @@
9097	10023	#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
9098	10024	#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
9099	10025	#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
	10026	+
	10027	+/* DDI DP Compliance Control */
	10028	+#define _DDI_DP_COMP_CTL_A 0x605F0
	10029	+#define _DDI_DP_COMP_CTL_B 0x615F0
	10030	+#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
	10031	+#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
	10032	+#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
	10033	+#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
	10034	+#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
	10035	+#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
	10036	+#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
	10037	+#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
	10038	+#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
	10039	+
	10040	+/* DDI DP Compliance Pattern */
	10041	+#define _DDI_DP_COMP_PAT_A 0x605F4
	10042	+#define _DDI_DP_COMP_PAT_B 0x615F4
	10043	+#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
9100	10044
9101	10045	/* Sideband Interface (SBI) is programmed indirectly, via
9102	10046	* SBI_ADDR, which contains the register offset; and SBI_DATA,
..	..	@@ -9147,24 +10091,28 @@
9147	10091	/* SPLL */
9148	10092	#define SPLL_CTL _MMIO(0x46020)
9149	10093	#define SPLL_PLL_ENABLE (1 << 31)
9150		-#define SPLL_PLL_SSC (1 << 28)
9151		-#define SPLL_PLL_NON_SSC (2 << 28)
9152		-#define SPLL_PLL_LCPLL (3 << 28)
9153		-#define SPLL_PLL_REF_MASK (3 << 28)
9154		-#define SPLL_PLL_FREQ_810MHz (0 << 26)
9155		-#define SPLL_PLL_FREQ_1350MHz (1 << 26)
9156		-#define SPLL_PLL_FREQ_2700MHz (2 << 26)
9157		-#define SPLL_PLL_FREQ_MASK (3 << 26)
	10094	+#define SPLL_REF_BCLK (0 << 28)
	10095	+#define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
	10096	+#define SPLL_REF_NON_SSC_HSW (2 << 28)
	10097	+#define SPLL_REF_PCH_SSC_BDW (2 << 28)
	10098	+#define SPLL_REF_LCPLL (3 << 28)
	10099	+#define SPLL_REF_MASK (3 << 28)
	10100	+#define SPLL_FREQ_810MHz (0 << 26)
	10101	+#define SPLL_FREQ_1350MHz (1 << 26)
	10102	+#define SPLL_FREQ_2700MHz (2 << 26)
	10103	+#define SPLL_FREQ_MASK (3 << 26)
9158	10104
9159	10105	/* WRPLL */
9160	10106	#define _WRPLL_CTL1 0x46040
9161	10107	#define _WRPLL_CTL2 0x46060
9162	10108	#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
9163	10109	#define WRPLL_PLL_ENABLE (1 << 31)
9164		-#define WRPLL_PLL_SSC (1 << 28)
9165		-#define WRPLL_PLL_NON_SSC (2 << 28)
9166		-#define WRPLL_PLL_LCPLL (3 << 28)
9167		-#define WRPLL_PLL_REF_MASK (3 << 28)
	10110	+#define WRPLL_REF_BCLK (0 << 28)
	10111	+#define WRPLL_REF_PCH_SSC (1 << 28)
	10112	+#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
	10113	+#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
	10114	+#define WRPLL_REF_LCPLL (3 << 28)
	10115	+#define WRPLL_REF_MASK (3 << 28)
9168	10116	/* WRPLL divider programming */
9169	10117	#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
9170	10118	#define WRPLL_DIVIDER_REF_MASK (0xff)
..	..	@@ -9206,6 +10154,9 @@
9206	10154	/* For each transcoder, we need to select the corresponding port clock */
9207	10155	#define TRANS_CLK_SEL_DISABLED (0x0 << 29)
9208	10156	#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
	10157	+#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
	10158	+#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
	10159	+
9209	10160
9210	10161	#define CDCLK_FREQ _MMIO(0x46200)
9211	10162
..	..	@@ -9214,19 +10165,16 @@
9214	10165	#define _TRANSC_MSA_MISC 0x62410
9215	10166	#define _TRANS_EDP_MSA_MISC 0x6f410
9216	10167	#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
9217		-
9218		-#define TRANS_MSA_SYNC_CLK (1 << 0)
9219		-#define TRANS_MSA_6_BPC (0 << 5)
9220		-#define TRANS_MSA_8_BPC (1 << 5)
9221		-#define TRANS_MSA_10_BPC (2 << 5)
9222		-#define TRANS_MSA_12_BPC (3 << 5)
9223		-#define TRANS_MSA_16_BPC (4 << 5)
9224		-#define TRANS_MSA_CEA_RANGE (1 << 3)
	10168	+/* See DP_MSA_MISC_* for the bit definitions */
9225	10169
9226	10170	/* LCPLL Control */
9227	10171	#define LCPLL_CTL _MMIO(0x130040)
9228	10172	#define LCPLL_PLL_DISABLE (1 << 31)
9229	10173	#define LCPLL_PLL_LOCK (1 << 30)
	10174	+#define LCPLL_REF_NON_SSC (0 << 28)
	10175	+#define LCPLL_REF_BCLK (2 << 28)
	10176	+#define LCPLL_REF_PCH_SSC (3 << 28)
	10177	+#define LCPLL_REF_MASK (3 << 28)
9230	10178	#define LCPLL_CLK_FREQ_MASK (3 << 26)
9231	10179	#define LCPLL_CLK_FREQ_450 (0 << 26)
9232	10180	#define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
..	..	@@ -9258,7 +10206,10 @@
9258	10206	#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
9259	10207	#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
9260	10208	#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
	10209	+#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
9261	10210	#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
	10211	+#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
	10212	+#define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE
9262	10213	#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
9263	10214	#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
9264	10215
..	..	@@ -9330,13 +10281,27 @@
9330	10281	* CNL Clocks
9331	10282	*/
9332	10283	#define DPCLKA_CFGCR0 _MMIO(0x6C200)
9333		-#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
9334	10284	#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
9335	10285	(port) + 10))
9336	10286	#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
9337	10287	(port) * 2)
9338	10288	#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
9339	10289	#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
	10290	+
	10291	+#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
	10292	+#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
	10293	+#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
	10294	+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
	10295	+ (tc_port) + 12 : \
	10296	+ (tc_port) - PORT_TC4 + 21))
	10297	+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
	10298	+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
	10299	+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
	10300	+#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
	10301	+#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
	10302	+ (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
	10303	+#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
	10304	+ ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
9340	10305
9341	10306	/* CNL PLL */
9342	10307	#define DPLL0_ENABLE 0x46010
..	..	@@ -9354,7 +10319,7 @@
9354	10319	#define _MG_PLL3_ENABLE 0x46038
9355	10320	#define _MG_PLL4_ENABLE 0x4603C
9356	10321	/* Bits are the same as DPLL0_ENABLE */
9357		-#define MG_PLL_ENABLE(port) _MMIO_PORT((port) - PORT_C, _MG_PLL1_ENABLE, \
	10322	+#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
9358	10323	_MG_PLL2_ENABLE)
9359	10324
9360	10325	#define _MG_REFCLKIN_CTL_PORT1 0x16892C
..	..	@@ -9363,9 +10328,9 @@
9363	10328	#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
9364	10329	#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
9365	10330	#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
9366		-#define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \
9367		- _MG_REFCLKIN_CTL_PORT1, \
9368		- _MG_REFCLKIN_CTL_PORT2)
	10331	+#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
	10332	+ _MG_REFCLKIN_CTL_PORT1, \
	10333	+ _MG_REFCLKIN_CTL_PORT2)
9369	10334
9370	10335	#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
9371	10336	#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
..	..	@@ -9375,9 +10340,9 @@
9375	10340	#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
9376	10341	#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
9377	10342	#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
9378		-#define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \
9379		- _MG_CLKTOP2_CORECLKCTL1_PORT1, \
9380		- _MG_CLKTOP2_CORECLKCTL1_PORT2)
	10343	+#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
	10344	+ _MG_CLKTOP2_CORECLKCTL1_PORT1, \
	10345	+ _MG_CLKTOP2_CORECLKCTL1_PORT2)
9381	10346
9382	10347	#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
9383	10348	#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
..	..	@@ -9387,23 +10352,30 @@
9387	10352	#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
9388	10353	#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
9389	10354	#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
9390		-#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x) ((x) << 12)
9391	10355	#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
	10356	+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
	10357	+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
	10358	+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
	10359	+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
9392	10360	#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
	10361	+#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
9393	10362	#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
9394		-#define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
9395		- _MG_CLKTOP2_HSCLKCTL_PORT1, \
9396		- _MG_CLKTOP2_HSCLKCTL_PORT2)
	10363	+#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
	10364	+ _MG_CLKTOP2_HSCLKCTL_PORT1, \
	10365	+ _MG_CLKTOP2_HSCLKCTL_PORT2)
9397	10366
9398	10367	#define _MG_PLL_DIV0_PORT1 0x168A00
9399	10368	#define _MG_PLL_DIV0_PORT2 0x169A00
9400	10369	#define _MG_PLL_DIV0_PORT3 0x16AA00
9401	10370	#define _MG_PLL_DIV0_PORT4 0x16BA00
9402	10371	#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
	10372	+#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
	10373	+#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
9403	10374	#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
	10375	+#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
9404	10376	#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
9405		-#define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV0_PORT1, \
9406		- _MG_PLL_DIV0_PORT2)
	10377	+#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
	10378	+ _MG_PLL_DIV0_PORT2)
9407	10379
9408	10380	#define _MG_PLL_DIV1_PORT1 0x168A04
9409	10381	#define _MG_PLL_DIV1_PORT2 0x169A04
..	..	@@ -9415,9 +10387,10 @@
9415	10387	#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
9416	10388	#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
9417	10389	#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
	10390	+#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
9418	10391	#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
9419		-#define MG_PLL_DIV1(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV1_PORT1, \
9420		- _MG_PLL_DIV1_PORT2)
	10392	+#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
	10393	+ _MG_PLL_DIV1_PORT2)
9421	10394
9422	10395	#define _MG_PLL_LF_PORT1 0x168A08
9423	10396	#define _MG_PLL_LF_PORT2 0x169A08
..	..	@@ -9429,8 +10402,8 @@
9429	10402	#define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
9430	10403	#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
9431	10404	#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
9432		-#define MG_PLL_LF(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_LF_PORT1, \
9433		- _MG_PLL_LF_PORT2)
	10405	+#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
	10406	+ _MG_PLL_LF_PORT2)
9434	10407
9435	10408	#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
9436	10409	#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
..	..	@@ -9442,9 +10415,9 @@
9442	10415	#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
9443	10416	#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
9444	10417	#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
9445		-#define MG_PLL_FRAC_LOCK(port) _MMIO_PORT((port) - PORT_C, \
9446		- _MG_PLL_FRAC_LOCK_PORT1, \
9447		- _MG_PLL_FRAC_LOCK_PORT2)
	10418	+#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
	10419	+ _MG_PLL_FRAC_LOCK_PORT1, \
	10420	+ _MG_PLL_FRAC_LOCK_PORT2)
9448	10421
9449	10422	#define _MG_PLL_SSC_PORT1 0x168A10
9450	10423	#define _MG_PLL_SSC_PORT2 0x169A10
..	..	@@ -9456,8 +10429,8 @@
9456	10429	#define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
9457	10430	#define MG_PLL_SSC_FLLEN (1 << 9)
9458	10431	#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
9459		-#define MG_PLL_SSC(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_SSC_PORT1, \
9460		- _MG_PLL_SSC_PORT2)
	10432	+#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
	10433	+ _MG_PLL_SSC_PORT2)
9461	10434
9462	10435	#define _MG_PLL_BIAS_PORT1 0x168A14
9463	10436	#define _MG_PLL_BIAS_PORT2 0x169A14
..	..	@@ -9476,8 +10449,8 @@
9476	10449	#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
9477	10450	#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
9478	10451	#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
9479		-#define MG_PLL_BIAS(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_BIAS_PORT1, \
9480		- _MG_PLL_BIAS_PORT2)
	10452	+#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
	10453	+ _MG_PLL_BIAS_PORT2)
9481	10454
9482	10455	#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
9483	10456	#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
..	..	@@ -9488,9 +10461,9 @@
9488	10461	#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
9489	10462	#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
9490	10463	#define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
9491		-#define MG_PLL_TDC_COLDST_BIAS(port) _MMIO_PORT((port) - PORT_C, \
9492		- _MG_PLL_TDC_COLDST_BIAS_PORT1, \
9493		- _MG_PLL_TDC_COLDST_BIAS_PORT2)
	10464	+#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
	10465	+ _MG_PLL_TDC_COLDST_BIAS_PORT1, \
	10466	+ _MG_PLL_TDC_COLDST_BIAS_PORT2)
9494	10467
9495	10468	#define _CNL_DPLL0_CFGCR0 0x6C000
9496	10469	#define _CNL_DPLL1_CFGCR0 0x6C080
..	..	@@ -9524,7 +10497,7 @@
9524	10497	#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
9525	10498	#define DPLL_CFGCR1_KDIV_1 (1 << 6)
9526	10499	#define DPLL_CFGCR1_KDIV_2 (2 << 6)
9527		-#define DPLL_CFGCR1_KDIV_4 (4 << 6)
	10500	+#define DPLL_CFGCR1_KDIV_3 (4 << 6)
9528	10501	#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
9529	10502	#define DPLL_CFGCR1_PDIV_SHIFT (2)
9530	10503	#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
..	..	@@ -9534,6 +10507,7 @@
9534	10507	#define DPLL_CFGCR1_PDIV_7 (8 << 2)
9535	10508	#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
9536	10509	#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
	10510	+#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
9537	10511	#define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
9538	10512
9539	10513	#define _ICL_DPLL0_CFGCR0 0x164000
..	..	@@ -9545,6 +10519,184 @@
9545	10519	#define _ICL_DPLL1_CFGCR1 0x164084
9546	10520	#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
9547	10521	_ICL_DPLL1_CFGCR1)
	10522	+
	10523	+#define _TGL_DPLL0_CFGCR0 0x164284
	10524	+#define _TGL_DPLL1_CFGCR0 0x16428C
	10525	+#define _TGL_TBTPLL_CFGCR0 0x16429C
	10526	+#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
	10527	+ _TGL_DPLL1_CFGCR0, \
	10528	+ _TGL_TBTPLL_CFGCR0)
	10529	+#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
	10530	+ _TGL_DPLL1_CFGCR0)
	10531	+
	10532	+#define _TGL_DPLL0_CFGCR1 0x164288
	10533	+#define _TGL_DPLL1_CFGCR1 0x164290
	10534	+#define _TGL_TBTPLL_CFGCR1 0x1642A0
	10535	+#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
	10536	+ _TGL_DPLL1_CFGCR1, \
	10537	+ _TGL_TBTPLL_CFGCR1)
	10538	+#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
	10539	+ _TGL_DPLL1_CFGCR1)
	10540	+
	10541	+#define _DKL_PHY1_BASE 0x168000
	10542	+#define _DKL_PHY2_BASE 0x169000
	10543	+#define _DKL_PHY3_BASE 0x16A000
	10544	+#define _DKL_PHY4_BASE 0x16B000
	10545	+#define _DKL_PHY5_BASE 0x16C000
	10546	+#define _DKL_PHY6_BASE 0x16D000
	10547	+
	10548	+/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
	10549	+#define _DKL_PLL_DIV0 0x200
	10550	+#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16)
	10551	+#define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16)
	10552	+#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12)
	10553	+#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
	10554	+#define DKL_PLL_DIV0_FBPREDIV_SHIFT (8)
	10555	+#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT)
	10556	+#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
	10557	+#define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
	10558	+#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0)
	10559	+#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
	10560	+ _DKL_PHY2_BASE) + \
	10561	+ _DKL_PLL_DIV0)
	10562	+
	10563	+#define _DKL_PLL_DIV1 0x204
	10564	+#define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16)
	10565	+#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16)
	10566	+#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0)
	10567	+#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
	10568	+#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
	10569	+ _DKL_PHY2_BASE) + \
	10570	+ _DKL_PLL_DIV1)
	10571	+
	10572	+#define _DKL_PLL_SSC 0x210
	10573	+#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29)
	10574	+#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29)
	10575	+#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16)
	10576	+#define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16)
	10577	+#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11)
	10578	+#define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11)
	10579	+#define DKL_PLL_SSC_EN (1 << 9)
	10580	+#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
	10581	+ _DKL_PHY2_BASE) + \
	10582	+ _DKL_PLL_SSC)
	10583	+
	10584	+#define _DKL_PLL_BIAS 0x214
	10585	+#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30)
	10586	+#define DKL_PLL_BIAS_FBDIV_SHIFT (8)
	10587	+#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
	10588	+#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
	10589	+#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
	10590	+ _DKL_PHY2_BASE) + \
	10591	+ _DKL_PLL_BIAS)
	10592	+
	10593	+#define _DKL_PLL_TDC_COLDST_BIAS 0x218
	10594	+#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8)
	10595	+#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8)
	10596	+#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0)
	10597	+#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0)
	10598	+#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
	10599	+ _DKL_PHY1_BASE, \
	10600	+ _DKL_PHY2_BASE) + \
	10601	+ _DKL_PLL_TDC_COLDST_BIAS)
	10602	+
	10603	+#define _DKL_REFCLKIN_CTL 0x12C
	10604	+/* Bits are the same as MG_REFCLKIN_CTL */
	10605	+#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \
	10606	+ _DKL_PHY1_BASE, \
	10607	+ _DKL_PHY2_BASE) + \
	10608	+ _DKL_REFCLKIN_CTL)
	10609	+
	10610	+#define _DKL_CLKTOP2_HSCLKCTL 0xD4
	10611	+/* Bits are the same as MG_CLKTOP2_HSCLKCTL */
	10612	+#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \
	10613	+ _DKL_PHY1_BASE, \
	10614	+ _DKL_PHY2_BASE) + \
	10615	+ _DKL_CLKTOP2_HSCLKCTL)
	10616	+
	10617	+#define _DKL_CLKTOP2_CORECLKCTL1 0xD8
	10618	+/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
	10619	+#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \
	10620	+ _DKL_PHY1_BASE, \
	10621	+ _DKL_PHY2_BASE) + \
	10622	+ _DKL_CLKTOP2_CORECLKCTL1)
	10623	+
	10624	+#define _DKL_TX_DPCNTL0 0x2C0
	10625	+#define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13)
	10626	+#define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13)
	10627	+#define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8)
	10628	+#define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8)
	10629	+#define DKL_TX_VSWING_CONTROL(x) ((x) << 0)
	10630	+#define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0)
	10631	+#define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \
	10632	+ _DKL_PHY1_BASE, \
	10633	+ _DKL_PHY2_BASE) + \
	10634	+ _DKL_TX_DPCNTL0)
	10635	+
	10636	+#define _DKL_TX_DPCNTL1 0x2C4
	10637	+/* Bits are the same as DKL_TX_DPCNTRL0 */
	10638	+#define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \
	10639	+ _DKL_PHY1_BASE, \
	10640	+ _DKL_PHY2_BASE) + \
	10641	+ _DKL_TX_DPCNTL1)
	10642	+
	10643	+#define _DKL_TX_DPCNTL2 0x2C8
	10644	+#define DKL_TX_DP20BITMODE (1 << 2)
	10645	+#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
	10646	+ _DKL_PHY1_BASE, \
	10647	+ _DKL_PHY2_BASE) + \
	10648	+ _DKL_TX_DPCNTL2)
	10649	+
	10650	+#define _DKL_TX_FW_CALIB 0x2F8
	10651	+#define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7)
	10652	+#define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \
	10653	+ _DKL_PHY1_BASE, \
	10654	+ _DKL_PHY2_BASE) + \
	10655	+ _DKL_TX_FW_CALIB)
	10656	+
	10657	+#define _DKL_TX_PMD_LANE_SUS 0xD00
	10658	+#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \
	10659	+ _DKL_PHY1_BASE, \
	10660	+ _DKL_PHY2_BASE) + \
	10661	+ _DKL_TX_PMD_LANE_SUS)
	10662	+
	10663	+#define _DKL_TX_DW17 0xDC4
	10664	+#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \
	10665	+ _DKL_PHY1_BASE, \
	10666	+ _DKL_PHY2_BASE) + \
	10667	+ _DKL_TX_DW17)
	10668	+
	10669	+#define _DKL_TX_DW18 0xDC8
	10670	+#define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \
	10671	+ _DKL_PHY1_BASE, \
	10672	+ _DKL_PHY2_BASE) + \
	10673	+ _DKL_TX_DW18)
	10674	+
	10675	+#define _DKL_DP_MODE 0xA0
	10676	+#define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
	10677	+ _DKL_PHY1_BASE, \
	10678	+ _DKL_PHY2_BASE) + \
	10679	+ _DKL_DP_MODE)
	10680	+
	10681	+#define _DKL_CMN_UC_DW27 0x36C
	10682	+#define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15)
	10683	+#define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \
	10684	+ _DKL_PHY1_BASE, \
	10685	+ _DKL_PHY2_BASE) + \
	10686	+ _DKL_CMN_UC_DW27)
	10687	+
	10688	+/*
	10689	+ * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
	10690	+ * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
	10691	+ * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address
	10692	+ * bits that point the 4KB window into the full PHY register space.
	10693	+ */
	10694	+#define _HIP_INDEX_REG0 0x1010A0
	10695	+#define _HIP_INDEX_REG1 0x1010A4
	10696	+#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \
	10697	+ : _HIP_INDEX_REG1)
	10698	+#define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4))
	10699	+#define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port))
9548	10700
9549	10701	/* BXT display engine PLL */
9550	10702	#define BXT_DE_PLL_CTL _MMIO(0x6d000)
..	..	@@ -9560,6 +10712,8 @@
9560	10712	/* GEN9 DC */
9561	10713	#define DC_STATE_EN _MMIO(0x45504)
9562	10714	#define DC_STATE_DISABLE 0
	10715	+#define DC_STATE_EN_DC3CO REG_BIT(30)
	10716	+#define DC_STATE_DC3CO_STATUS REG_BIT(29)
9563	10717	#define DC_STATE_EN_UPTO_DC5 (1 << 0)
9564	10718	#define DC_STATE_EN_DC9 (1 << 3)
9565	10719	#define DC_STATE_EN_UPTO_DC6 (2 << 0)
..	..	@@ -9568,6 +10722,80 @@
9568	10722	#define DC_STATE_DEBUG _MMIO(0x45520)
9569	10723	#define DC_STATE_DEBUG_MASK_CORES (1 << 0)
9570	10724	#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
	10725	+
	10726	+#define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
	10727	+#define BXT_REQ_DATA_MASK 0x3F
	10728	+#define BXT_DRAM_CHANNEL_ACTIVE_SHIFT 12
	10729	+#define BXT_DRAM_CHANNEL_ACTIVE_MASK (0xF << 12)
	10730	+#define BXT_MEMORY_FREQ_MULTIPLIER_HZ 133333333
	10731	+
	10732	+#define BXT_D_CR_DRP0_DUNIT8 0x1000
	10733	+#define BXT_D_CR_DRP0_DUNIT9 0x1200
	10734	+#define BXT_D_CR_DRP0_DUNIT_START 8
	10735	+#define BXT_D_CR_DRP0_DUNIT_END 11
	10736	+#define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \
	10737	+ _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
	10738	+ BXT_D_CR_DRP0_DUNIT9))
	10739	+#define BXT_DRAM_RANK_MASK 0x3
	10740	+#define BXT_DRAM_RANK_SINGLE 0x1
	10741	+#define BXT_DRAM_RANK_DUAL 0x3
	10742	+#define BXT_DRAM_WIDTH_MASK (0x3 << 4)
	10743	+#define BXT_DRAM_WIDTH_SHIFT 4
	10744	+#define BXT_DRAM_WIDTH_X8 (0x0 << 4)
	10745	+#define BXT_DRAM_WIDTH_X16 (0x1 << 4)
	10746	+#define BXT_DRAM_WIDTH_X32 (0x2 << 4)
	10747	+#define BXT_DRAM_WIDTH_X64 (0x3 << 4)
	10748	+#define BXT_DRAM_SIZE_MASK (0x7 << 6)
	10749	+#define BXT_DRAM_SIZE_SHIFT 6
	10750	+#define BXT_DRAM_SIZE_4GBIT (0x0 << 6)
	10751	+#define BXT_DRAM_SIZE_6GBIT (0x1 << 6)
	10752	+#define BXT_DRAM_SIZE_8GBIT (0x2 << 6)
	10753	+#define BXT_DRAM_SIZE_12GBIT (0x3 << 6)
	10754	+#define BXT_DRAM_SIZE_16GBIT (0x4 << 6)
	10755	+#define BXT_DRAM_TYPE_MASK (0x7 << 22)
	10756	+#define BXT_DRAM_TYPE_SHIFT 22
	10757	+#define BXT_DRAM_TYPE_DDR3 (0x0 << 22)
	10758	+#define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22)
	10759	+#define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22)
	10760	+#define BXT_DRAM_TYPE_DDR4 (0x4 << 22)
	10761	+
	10762	+#define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666
	10763	+#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
	10764	+#define SKL_REQ_DATA_MASK (0xF << 0)
	10765	+
	10766	+#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
	10767	+#define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0)
	10768	+#define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0)
	10769	+#define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0)
	10770	+#define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
	10771	+#define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
	10772	+
	10773	+#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
	10774	+#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
	10775	+#define SKL_DRAM_S_SHIFT 16
	10776	+#define SKL_DRAM_SIZE_MASK 0x3F
	10777	+#define SKL_DRAM_WIDTH_MASK (0x3 << 8)
	10778	+#define SKL_DRAM_WIDTH_SHIFT 8
	10779	+#define SKL_DRAM_WIDTH_X8 (0x0 << 8)
	10780	+#define SKL_DRAM_WIDTH_X16 (0x1 << 8)
	10781	+#define SKL_DRAM_WIDTH_X32 (0x2 << 8)
	10782	+#define SKL_DRAM_RANK_MASK (0x1 << 10)
	10783	+#define SKL_DRAM_RANK_SHIFT 10
	10784	+#define SKL_DRAM_RANK_1 (0x0 << 10)
	10785	+#define SKL_DRAM_RANK_2 (0x1 << 10)
	10786	+#define SKL_DRAM_RANK_MASK (0x1 << 10)
	10787	+#define CNL_DRAM_SIZE_MASK 0x7F
	10788	+#define CNL_DRAM_WIDTH_MASK (0x3 << 7)
	10789	+#define CNL_DRAM_WIDTH_SHIFT 7
	10790	+#define CNL_DRAM_WIDTH_X8 (0x0 << 7)
	10791	+#define CNL_DRAM_WIDTH_X16 (0x1 << 7)
	10792	+#define CNL_DRAM_WIDTH_X32 (0x2 << 7)
	10793	+#define CNL_DRAM_RANK_MASK (0x3 << 9)
	10794	+#define CNL_DRAM_RANK_SHIFT 9
	10795	+#define CNL_DRAM_RANK_1 (0x0 << 9)
	10796	+#define CNL_DRAM_RANK_2 (0x1 << 9)
	10797	+#define CNL_DRAM_RANK_3 (0x2 << 9)
	10798	+#define CNL_DRAM_RANK_4 (0x3 << 9)
9571	10799
9572	10800	/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
9573	10801	* since on HSW we can't write to it using I915_WRITE. */
..	..	@@ -9578,13 +10806,13 @@
9578	10806	#define D_COMP_COMP_DISABLE (1 << 0)
9579	10807
9580	10808	/* Pipe WM_LINETIME - watermark line time */
9581		-#define _PIPE_WM_LINETIME_A 0x45270
9582		-#define _PIPE_WM_LINETIME_B 0x45274
9583		-#define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
9584		-#define PIPE_WM_LINETIME_MASK (0x1ff)
9585		-#define PIPE_WM_LINETIME_TIME(x) ((x))
9586		-#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff << 16)
9587		-#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x) << 16)
	10809	+#define _WM_LINETIME_A 0x45270
	10810	+#define _WM_LINETIME_B 0x45274
	10811	+#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
	10812	+#define HSW_LINETIME_MASK REG_GENMASK(8, 0)
	10813	+#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
	10814	+#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
	10815	+#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
9588	10816
9589	10817	/* SFUSE_STRAP */
9590	10818	#define SFUSE_STRAP _MMIO(0xc2014)
..	..	@@ -9612,10 +10840,14 @@
9612	10840	#define _PIPE_A_CSC_COEFF_BU 0x4901c
9613	10841	#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
9614	10842	#define _PIPE_A_CSC_COEFF_BV 0x49024
	10843	+
9615	10844	#define _PIPE_A_CSC_MODE 0x49028
9616		-#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
9617		-#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
9618		-#define CSC_MODE_YUV_TO_RGB (1 << 0)
	10845	+#define ICL_CSC_ENABLE (1 << 31) /* icl+ */
	10846	+#define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */
	10847	+#define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */
	10848	+#define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */
	10849	+#define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */
	10850	+
9619	10851	#define _PIPE_A_CSC_PREOFF_HI 0x49030
9620	10852	#define _PIPE_A_CSC_PREOFF_ME 0x49034
9621	10853	#define _PIPE_A_CSC_PREOFF_LO 0x49038
..	..	@@ -9651,6 +10883,70 @@
9651	10883	#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
9652	10884	#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
9653	10885
	10886	+/* Pipe Output CSC */
	10887	+#define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050
	10888	+#define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054
	10889	+#define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058
	10890	+#define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c
	10891	+#define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060
	10892	+#define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064
	10893	+#define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068
	10894	+#define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c
	10895	+#define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070
	10896	+#define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074
	10897	+#define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078
	10898	+#define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c
	10899	+
	10900	+#define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150
	10901	+#define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154
	10902	+#define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158
	10903	+#define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c
	10904	+#define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160
	10905	+#define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164
	10906	+#define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168
	10907	+#define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c
	10908	+#define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170
	10909	+#define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174
	10910	+#define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178
	10911	+#define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c
	10912	+
	10913	+#define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\
	10914	+ _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
	10915	+ _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
	10916	+#define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \
	10917	+ _PIPE_A_OUTPUT_CSC_COEFF_BY, \
	10918	+ _PIPE_B_OUTPUT_CSC_COEFF_BY)
	10919	+#define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \
	10920	+ _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
	10921	+ _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
	10922	+#define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \
	10923	+ _PIPE_A_OUTPUT_CSC_COEFF_BU, \
	10924	+ _PIPE_B_OUTPUT_CSC_COEFF_BU)
	10925	+#define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \
	10926	+ _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
	10927	+ _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
	10928	+#define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \
	10929	+ _PIPE_A_OUTPUT_CSC_COEFF_BV, \
	10930	+ _PIPE_B_OUTPUT_CSC_COEFF_BV)
	10931	+#define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \
	10932	+ _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
	10933	+ _PIPE_B_OUTPUT_CSC_PREOFF_HI)
	10934	+#define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \
	10935	+ _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
	10936	+ _PIPE_B_OUTPUT_CSC_PREOFF_ME)
	10937	+#define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \
	10938	+ _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
	10939	+ _PIPE_B_OUTPUT_CSC_PREOFF_LO)
	10940	+#define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \
	10941	+ _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
	10942	+ _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
	10943	+#define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \
	10944	+ _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
	10945	+ _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
	10946	+#define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \
	10947	+ _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
	10948	+ _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
	10949	+
9654	10950	/* pipe degamma/gamma LUTs on IVB+ */
9655	10951	#define _PAL_PREC_INDEX_A 0x4A400
9656	10952	#define _PAL_PREC_INDEX_B 0x4AC00
..	..	@@ -9659,12 +10955,16 @@
9659	10955	#define PAL_PREC_SPLIT_MODE (1 << 31)
9660	10956	#define PAL_PREC_AUTO_INCREMENT (1 << 15)
9661	10957	#define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
	10958	+#define PAL_PREC_INDEX_VALUE(x) ((x) << 0)
9662	10959	#define _PAL_PREC_DATA_A 0x4A404
9663	10960	#define _PAL_PREC_DATA_B 0x4AC04
9664	10961	#define _PAL_PREC_DATA_C 0x4B404
9665	10962	#define _PAL_PREC_GC_MAX_A 0x4A410
9666	10963	#define _PAL_PREC_GC_MAX_B 0x4AC10
9667	10964	#define _PAL_PREC_GC_MAX_C 0x4B410
	10965	+#define PREC_PAL_DATA_RED_MASK REG_GENMASK(29, 20)
	10966	+#define PREC_PAL_DATA_GREEN_MASK REG_GENMASK(19, 10)
	10967	+#define PREC_PAL_DATA_BLUE_MASK REG_GENMASK(9, 0)
9668	10968	#define _PAL_PREC_EXT_GC_MAX_A 0x4A420
9669	10969	#define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
9670	10970	#define _PAL_PREC_EXT_GC_MAX_C 0x4B420
..	..	@@ -9676,6 +10976,7 @@
9676	10976	#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
9677	10977	#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
9678	10978	#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
	10979	+#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
9679	10980
9680	10981	#define _PRE_CSC_GAMC_INDEX_A 0x4A484
9681	10982	#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
..	..	@@ -9687,6 +10988,28 @@
9687	10988
9688	10989	#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
9689	10990	#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
	10991	+
	10992	+/* ICL Multi segmented gamma */
	10993	+#define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408
	10994	+#define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08
	10995	+#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15)
	10996	+#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0)
	10997	+
	10998	+#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
	10999	+#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
	11000	+#define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24)
	11001	+#define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20)
	11002	+#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
	11003	+#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
	11004	+#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4)
	11005	+#define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0)
	11006	+
	11007	+#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
	11008	+ _PAL_PREC_MULTI_SEG_INDEX_A, \
	11009	+ _PAL_PREC_MULTI_SEG_INDEX_B)
	11010	+#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
	11011	+ _PAL_PREC_MULTI_SEG_DATA_A, \
	11012	+ _PAL_PREC_MULTI_SEG_DATA_B)
9690	11013
9691	11014	/* pipe CSC & degamma/gamma LUTs on CHV */
9692	11015	#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
..	..	@@ -9700,6 +11023,9 @@
9700	11023	#define CGM_PIPE_MODE_GAMMA (1 << 2)
9701	11024	#define CGM_PIPE_MODE_CSC (1 << 1)
9702	11025	#define CGM_PIPE_MODE_DEGAMMA (1 << 0)
	11026	+#define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0)
	11027	+#define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16)
	11028	+#define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0)
9703	11029
9704	11030	#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
9705	11031	#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
..	..	@@ -9724,6 +11050,10 @@
9724	11050	#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
9725	11051	#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
9726	11052
	11053	+/* Gen11 DSI */
	11054	+#define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
	11055	+ dsi0, dsi1)
	11056	+
9727	11057	#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
9728	11058	#define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
9729	11059	#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
..	..	@@ -9744,6 +11074,57 @@
9744	11074	#define ICL_ESC_CLK_DIV_MASK 0x1ff
9745	11075	#define ICL_ESC_CLK_DIV_SHIFT 0
9746	11076	#define DSI_MAX_ESC_CLK 20000 /* in KHz */
	11077	+
	11078	+#define _DSI_CMD_FRMCTL_0 0x6b034
	11079	+#define _DSI_CMD_FRMCTL_1 0x6b834
	11080	+#define DSI_CMD_FRMCTL(port) _MMIO_PORT(port, \
	11081	+ _DSI_CMD_FRMCTL_0,\
	11082	+ _DSI_CMD_FRMCTL_1)
	11083	+#define DSI_FRAME_UPDATE_REQUEST (1 << 31)
	11084	+#define DSI_PERIODIC_FRAME_UPDATE_ENABLE (1 << 29)
	11085	+#define DSI_NULL_PACKET_ENABLE (1 << 28)
	11086	+#define DSI_FRAME_IN_PROGRESS (1 << 0)
	11087	+
	11088	+#define _DSI_INTR_MASK_REG_0 0x6b070
	11089	+#define _DSI_INTR_MASK_REG_1 0x6b870
	11090	+#define DSI_INTR_MASK_REG(port) _MMIO_PORT(port, \
	11091	+ _DSI_INTR_MASK_REG_0,\
	11092	+ _DSI_INTR_MASK_REG_1)
	11093	+
	11094	+#define _DSI_INTR_IDENT_REG_0 0x6b074
	11095	+#define _DSI_INTR_IDENT_REG_1 0x6b874
	11096	+#define DSI_INTR_IDENT_REG(port) _MMIO_PORT(port, \
	11097	+ _DSI_INTR_IDENT_REG_0,\
	11098	+ _DSI_INTR_IDENT_REG_1)
	11099	+#define DSI_TE_EVENT (1 << 31)
	11100	+#define DSI_RX_DATA_OR_BTA_TERMINATED (1 << 30)
	11101	+#define DSI_TX_DATA (1 << 29)
	11102	+#define DSI_ULPS_ENTRY_DONE (1 << 28)
	11103	+#define DSI_NON_TE_TRIGGER_RECEIVED (1 << 27)
	11104	+#define DSI_HOST_CHKSUM_ERROR (1 << 26)
	11105	+#define DSI_HOST_MULTI_ECC_ERROR (1 << 25)
	11106	+#define DSI_HOST_SINGL_ECC_ERROR (1 << 24)
	11107	+#define DSI_HOST_CONTENTION_DETECTED (1 << 23)
	11108	+#define DSI_HOST_FALSE_CONTROL_ERROR (1 << 22)
	11109	+#define DSI_HOST_TIMEOUT_ERROR (1 << 21)
	11110	+#define DSI_HOST_LOW_POWER_TX_SYNC_ERROR (1 << 20)
	11111	+#define DSI_HOST_ESCAPE_MODE_ENTRY_ERROR (1 << 19)
	11112	+#define DSI_FRAME_UPDATE_DONE (1 << 16)
	11113	+#define DSI_PROTOCOL_VIOLATION_REPORTED (1 << 15)
	11114	+#define DSI_INVALID_TX_LENGTH (1 << 13)
	11115	+#define DSI_INVALID_VC (1 << 12)
	11116	+#define DSI_INVALID_DATA_TYPE (1 << 11)
	11117	+#define DSI_PERIPHERAL_CHKSUM_ERROR (1 << 10)
	11118	+#define DSI_PERIPHERAL_MULTI_ECC_ERROR (1 << 9)
	11119	+#define DSI_PERIPHERAL_SINGLE_ECC_ERROR (1 << 8)
	11120	+#define DSI_PERIPHERAL_CONTENTION_DETECTED (1 << 7)
	11121	+#define DSI_PERIPHERAL_FALSE_CTRL_ERROR (1 << 6)
	11122	+#define DSI_PERIPHERAL_TIMEOUT_ERROR (1 << 5)
	11123	+#define DSI_PERIPHERAL_LP_TX_SYNC_ERROR (1 << 4)
	11124	+#define DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR (1 << 3)
	11125	+#define DSI_EOT_SYNC_ERROR (1 << 2)
	11126	+#define DSI_SOT_SYNC_ERROR (1 << 1)
	11127	+#define DSI_SOT_ERROR (1 << 0)
9747	11128
9748	11129	/* Gen4+ Timestamp and Pipe Frame time stamp registers */
9749	11130	#define GEN4_TIMESTAMP _MMIO(0x2358)
..	..	@@ -9886,6 +11267,39 @@
9886	11267	_ICL_DSI_IO_MODECTL_0, \
9887	11268	_ICL_DSI_IO_MODECTL_1)
9888	11269	#define COMBO_PHY_MODE_DSI (1 << 0)
	11270	+
	11271	+/* Display Stream Splitter Control */
	11272	+#define DSS_CTL1 _MMIO(0x67400)
	11273	+#define SPLITTER_ENABLE (1 << 31)
	11274	+#define JOINER_ENABLE (1 << 30)
	11275	+#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
	11276	+#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
	11277	+#define OVERLAP_PIXELS_MASK (0xf << 16)
	11278	+#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
	11279	+#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
	11280	+#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
	11281	+#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
	11282	+
	11283	+#define DSS_CTL2 _MMIO(0x67404)
	11284	+#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
	11285	+#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
	11286	+#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
	11287	+#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
	11288	+
	11289	+#define _ICL_PIPE_DSS_CTL1_PB 0x78200
	11290	+#define _ICL_PIPE_DSS_CTL1_PC 0x78400
	11291	+#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
	11292	+ _ICL_PIPE_DSS_CTL1_PB, \
	11293	+ _ICL_PIPE_DSS_CTL1_PC)
	11294	+#define BIG_JOINER_ENABLE (1 << 29)
	11295	+#define MASTER_BIG_JOINER_ENABLE (1 << 28)
	11296	+#define VGA_CENTERING_ENABLE (1 << 27)
	11297	+
	11298	+#define _ICL_PIPE_DSS_CTL2_PB 0x78204
	11299	+#define _ICL_PIPE_DSS_CTL2_PC 0x78404
	11300	+#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
	11301	+ _ICL_PIPE_DSS_CTL2_PB, \
	11302	+ _ICL_PIPE_DSS_CTL2_PC)
9889	11303
9890	11304	#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
9891	11305	#define STAP_SELECT (1 << 0)
..	..	@@ -10217,6 +11631,243 @@
10217	11631	#define PREPARE_COUNT_SHIFT 0
10218	11632	#define PREPARE_COUNT_MASK (0x3f << 0)
10219	11633
	11634	+#define _ICL_DSI_T_INIT_MASTER_0 0x6b088
	11635	+#define _ICL_DSI_T_INIT_MASTER_1 0x6b888
	11636	+#define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \
	11637	+ _ICL_DSI_T_INIT_MASTER_0,\
	11638	+ _ICL_DSI_T_INIT_MASTER_1)
	11639	+
	11640	+#define _DPHY_CLK_TIMING_PARAM_0 0x162180
	11641	+#define _DPHY_CLK_TIMING_PARAM_1 0x6c180
	11642	+#define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
	11643	+ _DPHY_CLK_TIMING_PARAM_0,\
	11644	+ _DPHY_CLK_TIMING_PARAM_1)
	11645	+#define _DSI_CLK_TIMING_PARAM_0 0x6b080
	11646	+#define _DSI_CLK_TIMING_PARAM_1 0x6b880
	11647	+#define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
	11648	+ _DSI_CLK_TIMING_PARAM_0,\
	11649	+ _DSI_CLK_TIMING_PARAM_1)
	11650	+#define CLK_PREPARE_OVERRIDE (1 << 31)
	11651	+#define CLK_PREPARE(x) ((x) << 28)
	11652	+#define CLK_PREPARE_MASK (0x7 << 28)
	11653	+#define CLK_PREPARE_SHIFT 28
	11654	+#define CLK_ZERO_OVERRIDE (1 << 27)
	11655	+#define CLK_ZERO(x) ((x) << 20)
	11656	+#define CLK_ZERO_MASK (0xf << 20)
	11657	+#define CLK_ZERO_SHIFT 20
	11658	+#define CLK_PRE_OVERRIDE (1 << 19)
	11659	+#define CLK_PRE(x) ((x) << 16)
	11660	+#define CLK_PRE_MASK (0x3 << 16)
	11661	+#define CLK_PRE_SHIFT 16
	11662	+#define CLK_POST_OVERRIDE (1 << 15)
	11663	+#define CLK_POST(x) ((x) << 8)
	11664	+#define CLK_POST_MASK (0x7 << 8)
	11665	+#define CLK_POST_SHIFT 8
	11666	+#define CLK_TRAIL_OVERRIDE (1 << 7)
	11667	+#define CLK_TRAIL(x) ((x) << 0)
	11668	+#define CLK_TRAIL_MASK (0xf << 0)
	11669	+#define CLK_TRAIL_SHIFT 0
	11670	+
	11671	+#define _DPHY_DATA_TIMING_PARAM_0 0x162184
	11672	+#define _DPHY_DATA_TIMING_PARAM_1 0x6c184
	11673	+#define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
	11674	+ _DPHY_DATA_TIMING_PARAM_0,\
	11675	+ _DPHY_DATA_TIMING_PARAM_1)
	11676	+#define _DSI_DATA_TIMING_PARAM_0 0x6B084
	11677	+#define _DSI_DATA_TIMING_PARAM_1 0x6B884
	11678	+#define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
	11679	+ _DSI_DATA_TIMING_PARAM_0,\
	11680	+ _DSI_DATA_TIMING_PARAM_1)
	11681	+#define HS_PREPARE_OVERRIDE (1 << 31)
	11682	+#define HS_PREPARE(x) ((x) << 24)
	11683	+#define HS_PREPARE_MASK (0x7 << 24)
	11684	+#define HS_PREPARE_SHIFT 24
	11685	+#define HS_ZERO_OVERRIDE (1 << 23)
	11686	+#define HS_ZERO(x) ((x) << 16)
	11687	+#define HS_ZERO_MASK (0xf << 16)
	11688	+#define HS_ZERO_SHIFT 16
	11689	+#define HS_TRAIL_OVERRIDE (1 << 15)
	11690	+#define HS_TRAIL(x) ((x) << 8)
	11691	+#define HS_TRAIL_MASK (0x7 << 8)
	11692	+#define HS_TRAIL_SHIFT 8
	11693	+#define HS_EXIT_OVERRIDE (1 << 7)
	11694	+#define HS_EXIT(x) ((x) << 0)
	11695	+#define HS_EXIT_MASK (0x7 << 0)
	11696	+#define HS_EXIT_SHIFT 0
	11697	+
	11698	+#define _DPHY_TA_TIMING_PARAM_0 0x162188
	11699	+#define _DPHY_TA_TIMING_PARAM_1 0x6c188
	11700	+#define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
	11701	+ _DPHY_TA_TIMING_PARAM_0,\
	11702	+ _DPHY_TA_TIMING_PARAM_1)
	11703	+#define _DSI_TA_TIMING_PARAM_0 0x6b098
	11704	+#define _DSI_TA_TIMING_PARAM_1 0x6b898
	11705	+#define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
	11706	+ _DSI_TA_TIMING_PARAM_0,\
	11707	+ _DSI_TA_TIMING_PARAM_1)
	11708	+#define TA_SURE_OVERRIDE (1 << 31)
	11709	+#define TA_SURE(x) ((x) << 16)
	11710	+#define TA_SURE_MASK (0x1f << 16)
	11711	+#define TA_SURE_SHIFT 16
	11712	+#define TA_GO_OVERRIDE (1 << 15)
	11713	+#define TA_GO(x) ((x) << 8)
	11714	+#define TA_GO_MASK (0xf << 8)
	11715	+#define TA_GO_SHIFT 8
	11716	+#define TA_GET_OVERRIDE (1 << 7)
	11717	+#define TA_GET(x) ((x) << 0)
	11718	+#define TA_GET_MASK (0xf << 0)
	11719	+#define TA_GET_SHIFT 0
	11720	+
	11721	+/* DSI transcoder configuration */
	11722	+#define _DSI_TRANS_FUNC_CONF_0 0x6b030
	11723	+#define _DSI_TRANS_FUNC_CONF_1 0x6b830
	11724	+#define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \
	11725	+ _DSI_TRANS_FUNC_CONF_0,\
	11726	+ _DSI_TRANS_FUNC_CONF_1)
	11727	+#define OP_MODE_MASK (0x3 << 28)
	11728	+#define OP_MODE_SHIFT 28
	11729	+#define CMD_MODE_NO_GATE (0x0 << 28)
	11730	+#define CMD_MODE_TE_GATE (0x1 << 28)
	11731	+#define VIDEO_MODE_SYNC_EVENT (0x2 << 28)
	11732	+#define VIDEO_MODE_SYNC_PULSE (0x3 << 28)
	11733	+#define TE_SOURCE_GPIO (1 << 27)
	11734	+#define LINK_READY (1 << 20)
	11735	+#define PIX_FMT_MASK (0x3 << 16)
	11736	+#define PIX_FMT_SHIFT 16
	11737	+#define PIX_FMT_RGB565 (0x0 << 16)
	11738	+#define PIX_FMT_RGB666_PACKED (0x1 << 16)
	11739	+#define PIX_FMT_RGB666_LOOSE (0x2 << 16)
	11740	+#define PIX_FMT_RGB888 (0x3 << 16)
	11741	+#define PIX_FMT_RGB101010 (0x4 << 16)
	11742	+#define PIX_FMT_RGB121212 (0x5 << 16)
	11743	+#define PIX_FMT_COMPRESSED (0x6 << 16)
	11744	+#define BGR_TRANSMISSION (1 << 15)
	11745	+#define PIX_VIRT_CHAN(x) ((x) << 12)
	11746	+#define PIX_VIRT_CHAN_MASK (0x3 << 12)
	11747	+#define PIX_VIRT_CHAN_SHIFT 12
	11748	+#define PIX_BUF_THRESHOLD_MASK (0x3 << 10)
	11749	+#define PIX_BUF_THRESHOLD_SHIFT 10
	11750	+#define PIX_BUF_THRESHOLD_1_4 (0x0 << 10)
	11751	+#define PIX_BUF_THRESHOLD_1_2 (0x1 << 10)
	11752	+#define PIX_BUF_THRESHOLD_3_4 (0x2 << 10)
	11753	+#define PIX_BUF_THRESHOLD_FULL (0x3 << 10)
	11754	+#define CONTINUOUS_CLK_MASK (0x3 << 8)
	11755	+#define CONTINUOUS_CLK_SHIFT 8
	11756	+#define CLK_ENTER_LP_AFTER_DATA (0x0 << 8)
	11757	+#define CLK_HS_OR_LP (0x2 << 8)
	11758	+#define CLK_HS_CONTINUOUS (0x3 << 8)
	11759	+#define LINK_CALIBRATION_MASK (0x3 << 4)
	11760	+#define LINK_CALIBRATION_SHIFT 4
	11761	+#define CALIBRATION_DISABLED (0x0 << 4)
	11762	+#define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4)
	11763	+#define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4)
	11764	+#define BLANKING_PACKET_ENABLE (1 << 2)
	11765	+#define S3D_ORIENTATION_LANDSCAPE (1 << 1)
	11766	+#define EOTP_DISABLED (1 << 0)
	11767	+
	11768	+#define _DSI_CMD_RXCTL_0 0x6b0d4
	11769	+#define _DSI_CMD_RXCTL_1 0x6b8d4
	11770	+#define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \
	11771	+ _DSI_CMD_RXCTL_0,\
	11772	+ _DSI_CMD_RXCTL_1)
	11773	+#define READ_UNLOADS_DW (1 << 16)
	11774	+#define RECEIVED_UNASSIGNED_TRIGGER (1 << 15)
	11775	+#define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14)
	11776	+#define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13)
	11777	+#define RECEIVED_RESET_TRIGGER (1 << 12)
	11778	+#define RECEIVED_PAYLOAD_WAS_LOST (1 << 11)
	11779	+#define RECEIVED_CRC_WAS_LOST (1 << 10)
	11780	+#define NUMBER_RX_PLOAD_DW_MASK (0xff << 0)
	11781	+#define NUMBER_RX_PLOAD_DW_SHIFT 0
	11782	+
	11783	+#define _DSI_CMD_TXCTL_0 0x6b0d0
	11784	+#define _DSI_CMD_TXCTL_1 0x6b8d0
	11785	+#define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \
	11786	+ _DSI_CMD_TXCTL_0,\
	11787	+ _DSI_CMD_TXCTL_1)
	11788	+#define KEEP_LINK_IN_HS (1 << 24)
	11789	+#define FREE_HEADER_CREDIT_MASK (0x1f << 8)
	11790	+#define FREE_HEADER_CREDIT_SHIFT 0x8
	11791	+#define FREE_PLOAD_CREDIT_MASK (0xff << 0)
	11792	+#define FREE_PLOAD_CREDIT_SHIFT 0
	11793	+#define MAX_HEADER_CREDIT 0x10
	11794	+#define MAX_PLOAD_CREDIT 0x40
	11795	+
	11796	+#define _DSI_CMD_TXHDR_0 0x6b100
	11797	+#define _DSI_CMD_TXHDR_1 0x6b900
	11798	+#define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \
	11799	+ _DSI_CMD_TXHDR_0,\
	11800	+ _DSI_CMD_TXHDR_1)
	11801	+#define PAYLOAD_PRESENT (1 << 31)
	11802	+#define LP_DATA_TRANSFER (1 << 30)
	11803	+#define VBLANK_FENCE (1 << 29)
	11804	+#define PARAM_WC_MASK (0xffff << 8)
	11805	+#define PARAM_WC_LOWER_SHIFT 8
	11806	+#define PARAM_WC_UPPER_SHIFT 16
	11807	+#define VC_MASK (0x3 << 6)
	11808	+#define VC_SHIFT 6
	11809	+#define DT_MASK (0x3f << 0)
	11810	+#define DT_SHIFT 0
	11811	+
	11812	+#define _DSI_CMD_TXPYLD_0 0x6b104
	11813	+#define _DSI_CMD_TXPYLD_1 0x6b904
	11814	+#define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \
	11815	+ _DSI_CMD_TXPYLD_0,\
	11816	+ _DSI_CMD_TXPYLD_1)
	11817	+
	11818	+#define _DSI_LP_MSG_0 0x6b0d8
	11819	+#define _DSI_LP_MSG_1 0x6b8d8
	11820	+#define DSI_LP_MSG(tc) _MMIO_DSI(tc, \
	11821	+ _DSI_LP_MSG_0,\
	11822	+ _DSI_LP_MSG_1)
	11823	+#define LPTX_IN_PROGRESS (1 << 17)
	11824	+#define LINK_IN_ULPS (1 << 16)
	11825	+#define LINK_ULPS_TYPE_LP11 (1 << 8)
	11826	+#define LINK_ENTER_ULPS (1 << 0)
	11827	+
	11828	+/* DSI timeout registers */
	11829	+#define _DSI_HSTX_TO_0 0x6b044
	11830	+#define _DSI_HSTX_TO_1 0x6b844
	11831	+#define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \
	11832	+ _DSI_HSTX_TO_0,\
	11833	+ _DSI_HSTX_TO_1)
	11834	+#define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16)
	11835	+#define HSTX_TIMEOUT_VALUE_SHIFT 16
	11836	+#define HSTX_TIMEOUT_VALUE(x) ((x) << 16)
	11837	+#define HSTX_TIMED_OUT (1 << 0)
	11838	+
	11839	+#define _DSI_LPRX_HOST_TO_0 0x6b048
	11840	+#define _DSI_LPRX_HOST_TO_1 0x6b848
	11841	+#define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \
	11842	+ _DSI_LPRX_HOST_TO_0,\
	11843	+ _DSI_LPRX_HOST_TO_1)
	11844	+#define LPRX_TIMED_OUT (1 << 16)
	11845	+#define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0)
	11846	+#define LPRX_TIMEOUT_VALUE_SHIFT 0
	11847	+#define LPRX_TIMEOUT_VALUE(x) ((x) << 0)
	11848	+
	11849	+#define _DSI_PWAIT_TO_0 0x6b040
	11850	+#define _DSI_PWAIT_TO_1 0x6b840
	11851	+#define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \
	11852	+ _DSI_PWAIT_TO_0,\
	11853	+ _DSI_PWAIT_TO_1)
	11854	+#define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16)
	11855	+#define PRESET_TIMEOUT_VALUE_SHIFT 16
	11856	+#define PRESET_TIMEOUT_VALUE(x) ((x) << 16)
	11857	+#define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0)
	11858	+#define PRESPONSE_TIMEOUT_VALUE_SHIFT 0
	11859	+#define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0)
	11860	+
	11861	+#define _DSI_TA_TO_0 0x6b04c
	11862	+#define _DSI_TA_TO_1 0x6b84c
	11863	+#define DSI_TA_TO(tc) _MMIO_DSI(tc, \
	11864	+ _DSI_TA_TO_0,\
	11865	+ _DSI_TA_TO_1)
	11866	+#define TA_TIMED_OUT (1 << 16)
	11867	+#define TA_TIMEOUT_VALUE_MASK (0xffff << 0)
	11868	+#define TA_TIMEOUT_VALUE_SHIFT 0
	11869	+#define TA_TIMEOUT_VALUE(x) ((x) << 0)
	11870	+
10220	11871	/* bits 31:0 */
10221	11872	#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
10222	11873	#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
..	..	@@ -10329,25 +11980,28 @@
10329	11980	#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
10330	11981	#define READ_DATA_VALID(n) (1 << (n))
10331	11982
10332		-/* For UMS only (deprecated): */
10333		-#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
10334		-#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
10335		-
10336	11983	/* MOCS (Memory Object Control State) registers */
10337	11984	#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
10338	11985
10339		-#define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */
10340		-#define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */
10341		-#define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */
10342		-#define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
10343		-#define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
10344		-/* Media decoder 2 MOCS registers */
10345		-#define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4)
	11986	+#define __GEN9_RCS0_MOCS0 0xc800
	11987	+#define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
	11988	+#define __GEN9_VCS0_MOCS0 0xc900
	11989	+#define GEN9_MFX0_MOCS(i) _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
	11990	+#define __GEN9_VCS1_MOCS0 0xca00
	11991	+#define GEN9_MFX1_MOCS(i) _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
	11992	+#define __GEN9_VECS0_MOCS0 0xcb00
	11993	+#define GEN9_VEBOX_MOCS(i) _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
	11994	+#define __GEN9_BCS0_MOCS0 0xcc00
	11995	+#define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
	11996	+#define __GEN11_VCS2_MOCS0 0x10000
	11997	+#define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
10346	11998
10347	11999	#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
10348	12000	#define PMFLUSHDONE_LNICRSDROP (1 << 20)
10349	12001	#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
10350	12002	#define PMFLUSHDONE_LNEBLK (1 << 22)
	12003	+
	12004	+#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
10351	12005
10352	12006	/* gamt regs */
10353	12007	#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
..	..	@@ -10364,11 +12018,12 @@
10364	12018	#define _ICL_PHY_MISC_B 0x64C04
10365	12019	#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \
10366	12020	_ICL_PHY_MISC_B)
	12021	+#define ICL_PHY_MISC_MUX_DDID (1 << 28)
10367	12022	#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
10368	12023
10369	12024	/* Icelake Display Stream Compression Registers */
10370		-#define DSCA_PICTURE_PARAMETER_SET_0 0x6B200
10371		-#define DSCC_PICTURE_PARAMETER_SET_0 0x6BA00
	12025	+#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
	12026	+#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
10372	12027	#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
10373	12028	#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
10374	12029	#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
..	..	@@ -10388,8 +12043,8 @@
10388	12043	#define DSC_VER_MIN_SHIFT 4
10389	12044	#define DSC_VER_MAJ (0x1 << 0)
10390	12045
10391		-#define DSCA_PICTURE_PARAMETER_SET_1 0x6B204
10392		-#define DSCC_PICTURE_PARAMETER_SET_1 0x6BA04
	12046	+#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
	12047	+#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
10393	12048	#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
10394	12049	#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
10395	12050	#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
..	..	@@ -10402,8 +12057,8 @@
10402	12057	_ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
10403	12058	#define DSC_BPP(bpp) ((bpp) << 0)
10404	12059
10405		-#define DSCA_PICTURE_PARAMETER_SET_2 0x6B208
10406		-#define DSCC_PICTURE_PARAMETER_SET_2 0x6BA08
	12060	+#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
	12061	+#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
10407	12062	#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
10408	12063	#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
10409	12064	#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
..	..	@@ -10417,8 +12072,8 @@
10417	12072	#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
10418	12073	#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
10419	12074
10420		-#define DSCA_PICTURE_PARAMETER_SET_3 0x6B20C
10421		-#define DSCC_PICTURE_PARAMETER_SET_3 0x6BA0C
	12075	+#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
	12076	+#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
10422	12077	#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
10423	12078	#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
10424	12079	#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
..	..	@@ -10432,8 +12087,8 @@
10432	12087	#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
10433	12088	#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
10434	12089
10435		-#define DSCA_PICTURE_PARAMETER_SET_4 0x6B210
10436		-#define DSCC_PICTURE_PARAMETER_SET_4 0x6BA10
	12090	+#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
	12091	+#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
10437	12092	#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
10438	12093	#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
10439	12094	#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
..	..	@@ -10447,8 +12102,8 @@
10447	12102	#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
10448	12103	#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
10449	12104
10450		-#define DSCA_PICTURE_PARAMETER_SET_5 0x6B214
10451		-#define DSCC_PICTURE_PARAMETER_SET_5 0x6BA14
	12105	+#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
	12106	+#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
10452	12107	#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
10453	12108	#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
10454	12109	#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
..	..	@@ -10459,11 +12114,11 @@
10459	12114	#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10460	12115	_ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
10461	12116	_ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
10462		-#define DSC_SCALE_DEC_INTINT(scale_dec) ((scale_dec) << 16)
	12117	+#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
10463	12118	#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
10464	12119
10465		-#define DSCA_PICTURE_PARAMETER_SET_6 0x6B218
10466		-#define DSCC_PICTURE_PARAMETER_SET_6 0x6BA18
	12120	+#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
	12121	+#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
10467	12122	#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
10468	12123	#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
10469	12124	#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
..	..	@@ -10474,13 +12129,13 @@
10474	12129	#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10475	12130	_ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
10476	12131	_ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
10477		-#define DSC_FLATNESS_MAX_QP(max_qp) (qp << 24)
10478		-#define DSC_FLATNESS_MIN_QP(min_qp) (qp << 16)
	12132	+#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
	12133	+#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
10479	12134	#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
10480	12135	#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
10481	12136
10482		-#define DSCA_PICTURE_PARAMETER_SET_7 0x6B21C
10483		-#define DSCC_PICTURE_PARAMETER_SET_7 0x6BA1C
	12137	+#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
	12138	+#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
10484	12139	#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
10485	12140	#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
10486	12141	#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
..	..	@@ -10494,8 +12149,8 @@
10494	12149	#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
10495	12150	#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
10496	12151
10497		-#define DSCA_PICTURE_PARAMETER_SET_8 0x6B220
10498		-#define DSCC_PICTURE_PARAMETER_SET_8 0x6BA20
	12152	+#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
	12153	+#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
10499	12154	#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
10500	12155	#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
10501	12156	#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
..	..	@@ -10509,8 +12164,8 @@
10509	12164	#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
10510	12165	#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
10511	12166
10512		-#define DSCA_PICTURE_PARAMETER_SET_9 0x6B224
10513		-#define DSCC_PICTURE_PARAMETER_SET_9 0x6BA24
	12167	+#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
	12168	+#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
10514	12169	#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
10515	12170	#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
10516	12171	#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
..	..	@@ -10524,8 +12179,8 @@
10524	12179	#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
10525	12180	#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
10526	12181
10527		-#define DSCA_PICTURE_PARAMETER_SET_10 0x6B228
10528		-#define DSCC_PICTURE_PARAMETER_SET_10 0x6BA28
	12182	+#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
	12183	+#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
10529	12184	#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
10530	12185	#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
10531	12186	#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
..	..	@@ -10541,8 +12196,8 @@
10541	12196	#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
10542	12197	#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
10543	12198
10544		-#define DSCA_PICTURE_PARAMETER_SET_11 0x6B22C
10545		-#define DSCC_PICTURE_PARAMETER_SET_11 0x6BA2C
	12199	+#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
	12200	+#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
10546	12201	#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
10547	12202	#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
10548	12203	#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
..	..	@@ -10554,8 +12209,8 @@
10554	12209	_ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
10555	12210	_ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
10556	12211
10557		-#define DSCA_PICTURE_PARAMETER_SET_12 0x6B260
10558		-#define DSCC_PICTURE_PARAMETER_SET_12 0x6BA60
	12212	+#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
	12213	+#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
10559	12214	#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
10560	12215	#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
10561	12216	#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
..	..	@@ -10567,8 +12222,8 @@
10567	12222	_ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
10568	12223	_ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
10569	12224
10570		-#define DSCA_PICTURE_PARAMETER_SET_13 0x6B264
10571		-#define DSCC_PICTURE_PARAMETER_SET_13 0x6BA64
	12225	+#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
	12226	+#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
10572	12227	#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
10573	12228	#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
10574	12229	#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
..	..	@@ -10580,8 +12235,8 @@
10580	12235	_ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
10581	12236	_ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
10582	12237
10583		-#define DSCA_PICTURE_PARAMETER_SET_14 0x6B268
10584		-#define DSCC_PICTURE_PARAMETER_SET_14 0x6BA68
	12238	+#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
	12239	+#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
10585	12240	#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
10586	12241	#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
10587	12242	#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
..	..	@@ -10593,8 +12248,8 @@
10593	12248	_ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
10594	12249	_ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
10595	12250
10596		-#define DSCA_PICTURE_PARAMETER_SET_15 0x6B26C
10597		-#define DSCC_PICTURE_PARAMETER_SET_15 0x6BA6C
	12251	+#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
	12252	+#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
10598	12253	#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
10599	12254	#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
10600	12255	#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
..	..	@@ -10606,8 +12261,8 @@
10606	12261	_ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
10607	12262	_ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
10608	12263
10609		-#define DSCA_PICTURE_PARAMETER_SET_16 0x6B270
10610		-#define DSCC_PICTURE_PARAMETER_SET_16 0x6BA70
	12264	+#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
	12265	+#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
10611	12266	#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
10612	12267	#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
10613	12268	#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
..	..	@@ -10618,8 +12273,9 @@
10618	12273	#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10619	12274	_ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
10620	12275	_ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
	12276	+#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
10621	12277	#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
10622		-#define DSC_SLICE_CHUNK_SIZE(slice_chunk_aize) (slice_chunk_size << 0)
	12278	+#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
10623	12279
10624	12280	/* Icelake Rate Control Buffer Threshold Registers */
10625	12281	#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
..	..	@@ -10672,4 +12328,39 @@
10672	12328	_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
10673	12329	_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
10674	12330
	12331	+#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
	12332	+#define MODULAR_FIA_MASK (1 << 4)
	12333	+#define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
	12334	+#define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
	12335	+#define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
	12336	+#define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
	12337	+#define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
	12338	+
	12339	+#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
	12340	+#define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
	12341	+
	12342	+#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
	12343	+#define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
	12344	+
	12345	+#define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
	12346	+#define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
	12347	+#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
	12348	+#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
	12349	+
	12350	+/* This register controls the Display State Buffer (DSB) engines. */
	12351	+#define _DSBSL_INSTANCE_BASE 0x70B00
	12352	+#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
	12353	+ (pipe) * 0x1000 + (id) * 0x100)
	12354	+#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
	12355	+#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
	12356	+#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
	12357	+#define DSB_ENABLE (1 << 31)
	12358	+#define DSB_STATUS (1 << 0)
	12359	+
	12360	+#define TGL_ROOT_DEVICE_ID 0x9A00
	12361	+#define TGL_ROOT_DEVICE_MASK 0xFF00
	12362	+#define TGL_ROOT_DEVICE_SKU_MASK 0xF
	12363	+#define TGL_ROOT_DEVICE_SKU_ULX 0x2
	12364	+#define TGL_ROOT_DEVICE_SKU_ULT 0x4
	12365	+
10675	12366	#endif /* _I915_REG_H_ */