forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920 
 kernel/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
....@@ -2076,6 +2076,8 @@
20762076 #define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0x0000000c
20772077 #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
20782078 #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x00000004
2079
+#define CRTC_CONTROL__CRTC_PREFETCH_EN_MASK                0x10000000L
2080
+#define	CRTC_CONTROL__CRTC_PREFETCH_EN__SHIFT              0x0000001c
20792081 #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
20802082 #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x00000000
20812083 #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001eL
....@@ -6364,6 +6366,8 @@
63646366 #define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x00000000
63656367 #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000L
63666368 #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x00000010
6369
+#define DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK_MASK 0x00030000L
6370
+#define	DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT 0x00000010
63676371 #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
63686372 #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x00000000
63696373 #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x00000010L
....@@ -6384,6 +6388,8 @@
63846388 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x00000008
63856389 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
63866390 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x00000004
6391
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00003000L
6392
+#define	DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x0000000c
63876393 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000L
63886394 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x00000010
63896395 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
....@@ -6406,6 +6412,8 @@
64066412 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x00000008
64076413 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
64086414 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x00000000
6415
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00003000L
6416
+#define	DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0000000c
64096417 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000L
64106418 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x00000010
64116419 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
....@@ -7256,6 +7264,8 @@
72567264 #define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x00000008
72577265 #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0x000c0000L
72587266 #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x00000012
7267
+#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK                 0x00f00000L
7268
+#define	GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT               0x00000014
72597269 #define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000cL
72607270 #define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x00000002
72617271 #define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000L
....@@ -9835,4 +9845,98 @@
98359845 #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
98369846 #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
98379847 
9848
+// DATA_FORMAT
9849
+#define DATA_FORMAT__INTERLEAVE_EN_MASK                    0x00000001L
9850
+#define	DATA_FORMAT__INTERLEAVE_EN__SHIFT                  0x00000000
9851
+#define DATA_FORMAT__RESET_REQ_AT_EOL_MASK                 0x00000010L
9852
+#define	DATA_FORMAT__RESET_REQ_AT_EOL__SHIFT               0x00000004
9853
+#define DATA_FORMAT__PREFETCH_MASK                         0x00001000L
9854
+#define	DATA_FORMAT__PREFETCH__SHIFT                       0x0000000c
9855
+#define DATA_FORMAT__SOF_READ_PT_MASK                      0x001f0000L
9856
+#define	DATA_FORMAT__SOF_READ_PT__SHIFT                    0x00000010
9857
+#define DATA_FORMAT__REQUEST_MODE_MASK                     0x03000000L
9858
+#define	DATA_FORMAT__REQUEST_MODE__SHIFT                   0x00000018
9859
+#define DATA_FORMAT__ALLOW_REQ_MODE_1_2_MASK               0x10000000L
9860
+#define	DATA_FORMAT__ALLOW_REQ_MODE_1_2__SHIFT             0x0000001c
9861
+
9862
+
9863
+// DC_LB_MEMORY_SPLIT
9864
+#define DC_LB_MEMORY_SPLIT__LB_NUM_PARTITIONS_MASK         0x000f0000L
9865
+#define	DC_LB_MEMORY_SPLIT__LB_NUM_PARTITIONS__SHIFT       0x00000010
9866
+#define DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG_MASK       0x00300000L
9867
+#define	DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG__SHIFT     0x00000014
9868
+
9869
+// DC_LB_MEM_SIZE
9870
+#define DC_LB_MEM_SIZE__DC_LB_MEM_SIZE_MASK                0x000007ffL
9871
+#define	DC_LB_MEM_SIZE__DC_LB_MEM_SIZE__SHIFT              0x00000000
9872
+
9873
+// SCL_TAP_CONTROL
9874
+#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK            0x00000007L
9875
+#define	SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT          0x00000000
9876
+#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK            0x00000f00L
9877
+#define	SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT          0x00000008
9878
+
9879
+// INT_MASK
9880
+#define INT_MASK__VBLANK_INT_MASK                          0x00000001L
9881
+#define	INT_MASK__VBLANK_INT__SHIFT                        0x00000000
9882
+#define INT_MASK__VLINE_INT_MASK                           0x00000010L
9883
+#define	INT_MASK__VLINE_INT__SHIFT                         0x00000004
9884
+
9885
+// PRIORITY_A_CNT
9886
+#define PRIORITY_A_CNT__PRIORITY_MARK_A_MASK               0x00007fffL
9887
+#define	PRIORITY_A_CNT__PRIORITY_MARK_A__SHIFT             0x00000000
9888
+#define PRIORITY_A_CNT__PRIORITY_A_OFF_MASK                0x00010000L
9889
+#define	PRIORITY_A_CNT__PRIORITY_A_OFF__SHIFT              0x00000010
9890
+#define PRIORITY_A_CNT__PRIORITY_A_ALWAYS_ON_MASK          0x00100000L
9891
+#define	PRIORITY_A_CNT__PRIORITY_A_ALWAYS_ON__SHIFT        0x00000014
9892
+#define PRIORITY_A_CNT__PRIORITY_A_FORCE_MASK_MASK         0x01000000L
9893
+#define	PRIORITY_A_CNT__PRIORITY_A_FORCE_MASK__SHIFT       0x00000018
9894
+
9895
+// PRIORITY_B_CNT
9896
+#define PRIORITY_B_CNT__PRIORITY_MARK_B_MASK               0x00007fffL
9897
+#define	PRIORITY_B_CNT__PRIORITY_MARK_B__SHIFT             0x00000000
9898
+#define PRIORITY_B_CNT__PRIORITY_B_OFF_MASK                0x00010000L
9899
+#define	PRIORITY_B_CNT__PRIORITY_B_OFF__SHIFT              0x00000010
9900
+#define PRIORITY_B_CNT__PRIORITY_B_ALWAYS_ON_MASK          0x00100000L
9901
+#define	PRIORITY_B_CNT__PRIORITY_B_ALWAYS_ON__SHIFT        0x00000014
9902
+#define PRIORITY_B_CNT__PRIORITY_B_FORCE_MASK_MASK         0x01000000L
9903
+#define	PRIORITY_B_CNT__PRIORITY_B_FORCE_MASK__SHIFT       0x00000018
9904
+
9905
+// VLINE_STATUS
9906
+#define VLINE_STATUS__VLINE_OCCURRED_MASK                  0x00000001L
9907
+#define	VLINE_STATUS__VLINE_OCCURRED__SHIFT                0x00000000
9908
+#define VLINE_STATUS__VLINE_ACK_MASK                       0x00000010L
9909
+#define	VLINE_STATUS__VLINE_ACK__SHIFT                     0x00000004
9910
+#define VLINE_STATUS__VLINE_STAT_MASK                      0x00001000L
9911
+#define	VLINE_STATUS__VLINE_STAT__SHIFT                    0x0000000c
9912
+#define VLINE_STATUS__VLINE_INTERRUPT_MASK                 0x00010000L
9913
+#define	VLINE_STATUS__VLINE_INTERRUPT__SHIFT               0x00000010
9914
+#define VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK            0x00020000L
9915
+#define	VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT          0x00000011
9916
+
9917
+// VBLANK_STATUS
9918
+#define VBLANK_STATUS__VBLANK_OCCURRED_MASK                0x00000001L
9919
+#define	VBLANK_STATUS__VBLANK_OCCURRED__SHIFT              0x00000000
9920
+#define VBLANK_STATUS__VBLANK_ACK_MASK                     0x00000010L
9921
+#define	VBLANK_STATUS__VBLANK_ACK__SHIFT                   0x00000004
9922
+#define VBLANK_STATUS__VBLANK_STAT_MASK                    0x00001000L
9923
+#define	VBLANK_STATUS__VBLANK_STAT__SHIFT                  0x0000000c
9924
+#define VBLANK_STATUS__VBLANK_INTERRUPT_MASK               0x00010000L
9925
+#define	VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT             0x00000010
9926
+#define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK          0x00020000L
9927
+#define	VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT        0x00000011
9928
+
9929
+// SCL_HORZ_FILTER_INIT_RGB_LUMA
9930
+#define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_FRAC_RGB_Y_MASK 0x0000ffffL
9931
+#define	SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_FRAC_RGB_Y__SHIFT 0x00000000
9932
+#define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_INT_RGB_Y_MASK 0x000f0000L
9933
+#define	SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_INT_RGB_Y__SHIFT 0x00000010
9934
+
9935
+// SCL_HORZ_FILTER_INIT_CHROMA
9936
+#define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_FRAC_CBCR_MASK 0x0000ffffL
9937
+#define	SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_FRAC_CBCR__SHIFT 0x00000000
9938
+#define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_INT_CBCR_MASK 0x00070000L
9939
+#define	SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_INT_CBCR__SHIFT 0x00000010
9940
+
9941
+
98389942 #endif