add lvds1024*800

hc

2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920

 kernel/drivers/clk/renesas/clk-sh73a0.c
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..
@@ -1,16 +1,14 @@
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+// SPDX-License-Identifier: GPL-2.0
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 /*
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  * sh73a0 Core CPG Clocks
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  *
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  * Copyright (C) 2014  Ulrich Hecht
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; version 2 of the License.
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  */
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 #include <linux/clk-provider.h>
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 #include <linux/clk/renesas.h>
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 #include <linux/init.h>
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+#include <linux/io.h>
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 #include <linux/kernel.h>
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 #include <linux/of.h>
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 #include <linux/of_address.h>
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@@ -206,8 +204,8 @@
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 		clk = sh73a0_cpg_register_clock(np, cpg, name);
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 		if (IS_ERR(clk))
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-			pr_err("%s: failed to register %s %s clock (%ld)\n",
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-			       __func__, np->name, name, PTR_ERR(clk));
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+			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
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+			       __func__, np, name, PTR_ERR(clk));
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 		else
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 			cpg->data.clks[i] = clk;
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 	}