forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920
kernel/drivers/clk/renesas/clk-div6.c
....@@ -1,13 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23 * r8a7790 Common Clock Framework support
34 *
45 * Copyright (C) 2013 Renesas Solutions Corp.
56 *
67 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; version 2 of the License.
118 */
129
1310 #include <linux/clk-provider.h>
....@@ -33,8 +30,8 @@
3330 * @div: divisor value (1-64)
3431 * @src_shift: Shift to access the register bits to select the parent clock
3532 * @src_width: Number of register bits to select the parent clock (may be 0)
36
- * @parents: Array to map from valid parent clocks indices to hardware indices
3733 * @nb: Notifier block to save/restore clock state for system resume
34
+ * @parents: Array to map from valid parent clocks indices to hardware indices
3835 */
3936 struct div6_clock {
4037 struct clk_hw hw;
....@@ -42,8 +39,8 @@
4239 unsigned int div;
4340 u32 src_shift;
4441 u32 src_width;
45
- u8 *parents;
4642 struct notifier_block nb;
43
+ u8 parents[];
4744 };
4845
4946 #define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
....@@ -219,21 +216,14 @@
219216 struct raw_notifier_head *notifiers)
220217 {
221218 unsigned int valid_parents;
222
- struct clk_init_data init = {};
219
+ struct clk_init_data init;
223220 struct div6_clock *clock;
224221 struct clk *clk;
225222 unsigned int i;
226223
227
- clock = kzalloc(sizeof(*clock), GFP_KERNEL);
224
+ clock = kzalloc(struct_size(clock, parents, num_parents), GFP_KERNEL);
228225 if (!clock)
229226 return ERR_PTR(-ENOMEM);
230
-
231
- clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),
232
- GFP_KERNEL);
233
- if (!clock->parents) {
234
- clk = ERR_PTR(-ENOMEM);
235
- goto free_clock;
236
- }
237227
238228 clock->reg = reg;
239229
....@@ -262,7 +252,7 @@
262252 pr_err("%s: invalid number of parents for DIV6 clock %s\n",
263253 __func__, name);
264254 clk = ERR_PTR(-EINVAL);
265
- goto free_parents;
255
+ goto free_clock;
266256 }
267257
268258 /* Filter out invalid parents */
....@@ -277,7 +267,7 @@
277267 /* Register the clock. */
278268 init.name = name;
279269 init.ops = &cpg_div6_clock_ops;
280
- init.flags = CLK_IS_BASIC;
270
+ init.flags = 0;
281271 init.parent_names = parent_names;
282272 init.num_parents = valid_parents;
283273
....@@ -285,7 +275,7 @@
285275
286276 clk = clk_register(NULL, &clock->hw);
287277 if (IS_ERR(clk))
288
- goto free_parents;
278
+ goto free_clock;
289279
290280 if (notifiers) {
291281 clock->nb.notifier_call = cpg_div6_clock_notifier_call;
....@@ -294,8 +284,6 @@
294284
295285 return clk;
296286
297
-free_parents:
298
- kfree(clock->parents);
299287 free_clock:
300288 kfree(clock);
301289 return clk;
....@@ -312,8 +300,8 @@
312300
313301 num_parents = of_clk_get_parent_count(np);
314302 if (num_parents < 1) {
315
- pr_err("%s: no parent found for %s DIV6 clock\n",
316
- __func__, np->name);
303
+ pr_err("%s: no parent found for %pOFn DIV6 clock\n",
304
+ __func__, np);
317305 return;
318306 }
319307
....@@ -324,8 +312,8 @@
324312
325313 reg = of_iomap(np, 0);
326314 if (reg == NULL) {
327
- pr_err("%s: failed to map %s DIV6 clock register\n",
328
- __func__, np->name);
315
+ pr_err("%s: failed to map %pOFn DIV6 clock register\n",
316
+ __func__, np);
329317 goto error;
330318 }
331319
....@@ -337,8 +325,8 @@
337325
338326 clk = cpg_div6_register(clk_name, num_parents, parent_names, reg, NULL);
339327 if (IS_ERR(clk)) {
340
- pr_err("%s: failed to register %s DIV6 clock (%ld)\n",
341
- __func__, np->name, PTR_ERR(clk));
328
+ pr_err("%s: failed to register %pOFn DIV6 clock (%ld)\n",
329
+ __func__, np, PTR_ERR(clk));
342330 goto error;
343331 }
344332