forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920
kernel/arch/arm64/boot/dts/rockchip/NK-R36S0.dtsi
....@@ -19,6 +19,7 @@
1919 rk_headset: rk-headset {
2020 compatible = "rockchip_headset";
2121 headset_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>;
22
+ spk_ctl_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;//AMP_SD_GPIO4_C2_3V3
2223 pinctrl-names = "default";
2324 pinctrl-0 = <&hp_det>;
2425 };
....@@ -88,10 +89,108 @@
8889 regulator-boot-on;
8990 };
9091 #endif
91
-
92
+ ndj_io_init {
93
+ compatible = "nk_io_control";
94
+ pinctrl-names = "default";
95
+ pinctrl-0 = <&nk_io_gpio>;
96
+
97
+ //gpio_op0 = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
98
+
99
+ vcc_5v {
100
+ gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; //VCC5_IO_EN_GPIO1_A4_3V3
101
+ gpio_function = <0>;
102
+ };
103
+
104
+ vcc_12v {
105
+ gpio_num = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; //VCC12_IO_EN_GPIO0_C7_3V3
106
+ gpio_function = <0>;
107
+ };
108
+
109
+ hub_host2_rst {
110
+ gpio_num = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; //HUB_RST_GPIO4_D2_3V3
111
+ gpio_function = <3>;
112
+ };
113
+
114
+ hub_host3 {
115
+ gpio_num = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; //HOST3_EN_GPIO4_B2_1V8
116
+ gpio_function = <0>;
117
+ };
118
+
119
+ wake_4g {
120
+ gpio_num = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; //4G_WAKEUP_GPIO01_B1_3V3
121
+ gpio_function = <0>;
122
+ };
123
+
124
+ air_mode_4g {
125
+ gpio_num = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; //4G_AIR_MODE_GPIO01_B0_3V3
126
+ gpio_function = <0>;
127
+ };
128
+
129
+ reset_4g {
130
+ gpio_num = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; //4G_RST_GPIO01_B2_3V3
131
+ gpio_function = <3>;
132
+ };
133
+
134
+ en_4g {
135
+ gpio_num = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; //4G_PWREN_H_GPIO0_C6
136
+ gpio_function = <0>;
137
+ };
138
+
139
+ hp_en {
140
+ gpio_num = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;//HP_EN_GPIO3_A6_3V3
141
+ gpio_function = <0>;
142
+ };
143
+
144
+ wifi_power_en {
145
+ gpio_num = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; //WIFI_PWREN_GPIO3_C6_1V8
146
+ gpio_function = <0>;
147
+ };
148
+ #if 0
149
+ do1 {
150
+ gpio_num = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
151
+ gpio_function = <0>;
152
+ };
153
+
154
+ do2 {
155
+ gpio_num = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
156
+ gpio_function = <0>;
157
+ };
158
+
159
+ do3 {
160
+ gpio_num = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
161
+ gpio_function = <0>;
162
+ };
163
+
164
+ do4 {
165
+ gpio_num = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
166
+ gpio_function = <0>;
167
+ };
168
+
169
+ do5 {
170
+ gpio_num = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>;
171
+ gpio_function = <0>;
172
+ };
173
+
174
+ do6 {
175
+ gpio_num = <&gpio2 RK_PD7 GPIO_ACTIVE_LOW>;
176
+ gpio_function = <0>;
177
+ };
178
+
179
+ do7 {
180
+ gpio_num = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
181
+ gpio_function = <0>;
182
+ };
183
+
184
+ di1 {
185
+ gpio_num = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>;
186
+ gpio_function = <1>;
187
+ };
188
+ #endif
189
+ };
190
+#if 0
92191 nk_io_init {
93192 compatible = "nk_io_control";
94
- vcc3_io_en_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; //VCC3_IO_EN_GPIO0_C4_3V3
193
+// vcc3_io_en_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; //VCC3_IO_EN_GPIO0_C4_3V3
95194 hub_host2_5V_rest_gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; //HUB_RST_GPIO4_D2_3V3
96195 hub_host3_5v_gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; //HOST3_EN_GPIO4_B2_1V8
97196 vcc_5v_io = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; //VCC5_IO_EN_GPIO1_A4_3V3
....@@ -101,13 +200,13 @@
101200 air_mode_4g_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; //4G_AIR_MODE_GPIO01_B0_3V3
102201 wake_4g_gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; //4G_WAKEUP_GPIO01_B1_3V3
103202 hp_en_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;//HP_EN_GPIO3_A6_3V3
104
- spk_out_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;//AMP_SD_GPIO4_C2_3V3
203
+// spk_out_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;//AMP_SD_GPIO4_C2_3V3
105204 wifi_power_en_gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; //WIFI_PWREN_GPIO3_C6_1V8
106205 // pcie_power_en_gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;//PCIE_PWREN_H_GPIO0_D4
107206 pinctrl-names = "default";
108207 pinctrl-0 = <&nk_io_gpio>;
109208 };
110
-
209
+#endif
111210 panel: panel {
112211 compatible = "simple-panel";
113212 backlight = <&backlight>;
....@@ -127,8 +226,8 @@
127226 nodka-lvds = <15>;
128227
129228 display-timings {
130
- native-mode = <&timing0>;
131
- timing0: timing0 {
229
+ native-mode = <&timing>;
230
+ timing: timing {
132231 clock-frequency = <72500000>;
133232 hactive = <1280>;
134233 vactive = <800>;
....@@ -145,8 +244,8 @@
145244 };
146245 };
147246 ports {
148
- panel_in: endpoint {
149
- remote-endpoint = <&edp_out>;
247
+ panel_in_lvds: endpoint {
248
+ remote-endpoint = <&lvds_out>;
150249 };
151250 };
152251 };
....@@ -213,7 +312,7 @@
213312 * when dsi0 is enabled
214313 */
215314 &video_phy0 {
216
- status = "disabled";
315
+ status = "okay";
217316 };
218317
219318 &dsi0 {
....@@ -238,7 +337,7 @@
238337 */
239338
240339 &video_phy1 {
241
- status = "okay";
340
+ status = "disabled";
242341 };
243342 &dsi1 {
244343 status = "disabled";
....@@ -249,11 +348,11 @@
249348 };
250349
251350 &dsi1_in_vp1 {
252
- status = "okay";
351
+ status = "disabled";
253352 };
254353
255354 &dsi1_panel {
256
- power-supply = <&vcc3v3_lcd1_n>; //MIPI_3V3EN_GPIO3_A3_d_3V3
355
+// power-supply = <&vcc3v3_lcd1_n>; //MIPI_3V3EN_GPIO3_A3_d_3V3
257356 vddio-mipi = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; //MIPI_EN_1V8_GPIO3_A4_d_3V3
258357 reset-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_LOW>; //MIPI_RST_L_GPIO3_C7
259358 vcc-5v-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; //VCC5_IO_EN_GPIO1_A4_3V3
....@@ -273,20 +372,11 @@
273372
274373 &edp {
275374 force-hpd;
276
- status = "okay";
277
- ports {
278
- port@1 {
279
- reg = <1>;
280
- edp_out: endpoint {
281
- remote-endpoint = <&panel_in>;
282
- };
283
- };
284
- };
375
+ status = "disabled";
285376 };
286377
287378 &edp_phy {
288
- status = "okay";
289
-
379
+ status = "disabled";
290380 };
291381
292382 &edp_in_vp0 {
....@@ -294,18 +384,40 @@
294384 };
295385
296386 &edp_in_vp1 {
297
- status = "okay";
387
+ status = "disabled";
298388
299389 };
300390
301391 &route_edp {
302
- status = "okay";
392
+ status = "disabled";
303393 connect = <&vp1_out_edp>;
304394 };
305395
306396 &route_edp {
397
+ status = "disabled";
398
+};
399
+
400
+&lvds {
401
+ status = "okay";
402
+ ports {
403
+ port@1 {
404
+ reg = <1>;
405
+ lvds_out:endpoint {
406
+ remote-endpoint = <&panel_in_lvds>;
407
+ };
408
+ };
409
+ };
410
+};
411
+
412
+&route_lvds{
413
+ status = "okay";
414
+ connect = <&vp1_out_lvds>;
415
+};
416
+
417
+&lvds_in_vp1 {
307418 status = "okay";
308419 };
420
+
309421 /*
310422 * edp_end
311423 */
....@@ -350,7 +462,7 @@
350462 phy-mode = "rgmii";
351463 clock_in_out = "output";
352464
353
- snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
465
+ snps,reset-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
354466 snps,reset-active-low;
355467 /* Reset time is 20ms, 100ms for rtl8211f */
356468 snps,reset-delays-us = <0 20000 100000>;
....@@ -370,7 +482,9 @@
370482 rx_delay = <0x2f>;
371483
372484 phy-handle = <&rgmii_phy0>;
485
+
373486 status = "disabled";
487
+
374488 };
375489
376490 &gmac1 {
....@@ -404,9 +518,7 @@
404518 * power-supply should switche to vcc3v3_lcd1_n
405519 * when mipi panel is connected to dsi1.
406520 */
407
-&gt1x {
408
- power-supply = <&vcc3v3_lcd0_n>;
409
-};
521
+
410522
411523 &i2c3 {
412524 status = "okay";
....@@ -425,7 +537,7 @@
425537 };
426538
427539 &i2c4 {
428
- status = "okay";
540
+ status = "disabled";
429541 gc8034: gc8034@37 {
430542 compatible = "galaxycore,gc8034";
431543 status = "okay";
....@@ -437,7 +549,6 @@
437549 reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>;
438550 pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>;
439551 rockchip,grf = <&grf>;
440
- power-domains = <&power RK3568_PD_VI>;
441552 rockchip,camera-module-index = <0>;
442553 rockchip,camera-module-facing = "back";
443554 rockchip,camera-module-name = "RK-CMK-8M-2-v1";
....@@ -471,7 +582,7 @@
471582 };
472583 };
473584 ov5695: ov5695@36 {
474
- status = "okay";
585
+ status = "disabled";
475586 compatible = "ovti,ov5695";
476587 reg = <0x36>;
477588 clocks = <&cru CLK_CIF_OUT>;
....@@ -543,7 +654,8 @@
543654 // };
544655 headphone {
545656 hp_det: hp-det {
546
- rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
657
+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>,
658
+ <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
547659 };
548660 };
549661
....@@ -578,12 +690,15 @@
578690 <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
579691 <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>,
580692 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>,
581
- <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
582693 <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,
583694 <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
584695 <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>,
585696 <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
586697 <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>,
698
+ <2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,//93 SPI2_CS0_M1_3V3
699
+ <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>,//94 SPI2_MOSI_M1_3V3
700
+ <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>,//95 SPI2_MISO_M1_3V3
701
+ <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>,//96 SPI2_CLK_M1_3V3
587702 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
588703 };
589704 };
....@@ -610,8 +725,6 @@
610725 };
611726 };
612727 };
613
-
614
-
615728
616729
617730
....@@ -673,20 +786,25 @@
673786 clock-names = "ext_clock";
674787 //wifi-bt-power-toggle;
675788 uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
676
- BT,power_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
677789 pinctrl-names = "default", "rts_gpio";
678790 pinctrl-0 = <&uart1m0_rtsn>;
679791 pinctrl-1 = <&uart1_gpios>;
680
- BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
681
- BT,wake_gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
682
- BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
683
- status = "disabled";
792
+ BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
793
+ BT,wake_gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
794
+ BT,wake_host_irq = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
795
+ status = "okay";
684796 };
685797
686798 &uart0 {
687799 status = "okay";
688800 };
689801
802
+&uart1 {
803
+ pinctrl-names = "default";
804
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
805
+ status = "okay";
806
+};
807
+
690808 &uart3 {
691809 status = "okay";
692810 pinctrl-0 = <&uart3m1_xfer>;