add lvds1024*800

hc

2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920

 kernel/Documentation/admin-guide/hw-vuln/spectre.rst
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@@ -479,8 +479,16 @@
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    On Intel Skylake-era systems the mitigation covers most, but not all,
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    cases. See :ref:`[3] <spec_ref3>` for more details.
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-   On CPUs with hardware mitigation for Spectre variant 2 (e.g. Enhanced
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-   IBRS on x86), retpoline is automatically disabled at run time.
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+   On CPUs with hardware mitigation for Spectre variant 2 (e.g. IBRS
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+   or enhanced IBRS on x86), retpoline is automatically disabled at run time.
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+
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+   Systems which support enhanced IBRS (eIBRS) enable IBRS protection once at
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+   boot, by setting the IBRS bit, and they're automatically protected against
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+   Spectre v2 variant attacks, including cross-thread branch target injections
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+   on SMT systems (STIBP). In other words, eIBRS enables STIBP too.
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+
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+   Legacy IBRS systems clear the IBRS bit on exit to userspace and
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+   therefore explicitly enable STIBP for that
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    The retpoline mitigation is turned on by default on vulnerable
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    CPUs. It can be forced on or off by the administrator
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@@ -504,9 +512,12 @@
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    For Spectre variant 2 mitigation, individual user programs
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    can be compiled with return trampolines for indirect branches.
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    This protects them from consuming poisoned entries in the branch
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-   target buffer left by malicious software.  Alternatively, the
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-   programs can disable their indirect branch speculation via prctl()
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-   (See :ref:`Documentation/userspace-api/spec_ctrl.rst <set_spec_ctrl>`).
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+   target buffer left by malicious software.
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+
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+   On legacy IBRS systems, at return to userspace, implicit STIBP is disabled
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+   because the kernel clears the IBRS bit. In this case, the userspace programs
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+   can disable indirect branch speculation via prctl() (See
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+   :ref:`Documentation/userspace-api/spec_ctrl.rst <set_spec_ctrl>`).
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    On x86, this will turn on STIBP to guard against attacks from the
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    sibling thread when the user program is running, and use IBPB to
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    flush the branch target buffer when switching to/from the program.