forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-11-07 f45e756958099c35d6afb746df1d40a1c6302cfc 
 kernel/sound/soc/rockchip/rockchip_i2s_tdm.h
....@@ -144,12 +144,16 @@
144144 #define I2S_DMACR_RDE_SHIFT	24
145145 #define I2S_DMACR_RDE_DISABLE	(0 << I2S_DMACR_RDE_SHIFT)
146146 #define I2S_DMACR_RDE_ENABLE	(1 << I2S_DMACR_RDE_SHIFT)
147
+#define I2S_DMACR_RDE_MASK	(1 << I2S_DMACR_RDE_SHIFT)
148
+#define I2S_DMACR_RDE(x)	((x) << I2S_DMACR_RDE_SHIFT)
147149 #define I2S_DMACR_RDL_SHIFT	16
148150 #define I2S_DMACR_RDL(x)	(((x) - 1) << I2S_DMACR_RDL_SHIFT)
149151 #define I2S_DMACR_RDL_MASK	(0x1f << I2S_DMACR_RDL_SHIFT)
150152 #define I2S_DMACR_TDE_SHIFT	8
151153 #define I2S_DMACR_TDE_DISABLE	(0 << I2S_DMACR_TDE_SHIFT)
152154 #define I2S_DMACR_TDE_ENABLE	(1 << I2S_DMACR_TDE_SHIFT)
155
+#define I2S_DMACR_TDE_MASK	(1 << I2S_DMACR_TDE_SHIFT)
156
+#define I2S_DMACR_TDE(x)	((x) << I2S_DMACR_TDE_SHIFT)
153157 #define I2S_DMACR_TDL_SHIFT	0
154158 #define I2S_DMACR_TDL(x)	((x) << I2S_DMACR_TDL_SHIFT)
155159 #define I2S_DMACR_TDL_MASK	(0x1f << I2S_DMACR_TDL_SHIFT)
....@@ -162,8 +166,8 @@
162166 #define I2S_INTCR_RFT(x)	(((x) - 1) << I2S_INTCR_RFT_SHIFT)
163167 #define I2S_INTCR_RXOIC		BIT(18)
164168 #define I2S_INTCR_RXOIE_SHIFT	17
165
-#define I2S_INTCR_RXOIE_DISABLE	(0 << I2S_INTCR_RXOIE_SHIFT)
166
-#define I2S_INTCR_RXOIE_ENABLE	(1 << I2S_INTCR_RXOIE_SHIFT)
169
+#define I2S_INTCR_RXOIE_MASK	(1 << I2S_INTCR_RXOIE_SHIFT)
170
+#define I2S_INTCR_RXOIE(x)	((x) << I2S_INTCR_RXOIE_SHIFT)
167171 #define I2S_INTCR_RXFIE_SHIFT	16
168172 #define I2S_INTCR_RXFIE_DISABLE	(0 << I2S_INTCR_RXFIE_SHIFT)
169173 #define I2S_INTCR_RXFIE_ENABLE	(1 << I2S_INTCR_RXFIE_SHIFT)
....@@ -172,8 +176,8 @@
172176 #define I2S_INTCR_TFT_MASK	(0x1f << I2S_INTCR_TFT_SHIFT)
173177 #define I2S_INTCR_TXUIC		BIT(2)
174178 #define I2S_INTCR_TXUIE_SHIFT	1
175
-#define I2S_INTCR_TXUIE_DISABLE	(0 << I2S_INTCR_TXUIE_SHIFT)
176
-#define I2S_INTCR_TXUIE_ENABLE	(1 << I2S_INTCR_TXUIE_SHIFT)
179
+#define I2S_INTCR_TXUIE_MASK	(1 << I2S_INTCR_TXUIE_SHIFT)
180
+#define I2S_INTCR_TXUIE(x)	((x) << I2S_INTCR_TXUIE_SHIFT)
177181 
178182 /*
179183  * INTSR
....@@ -199,12 +203,37 @@
199203  * XFER
200204  * Transfer start register
201205  */
206
+/*
207
+ * lp mode2 swap:
208
+ * i2s sdi0_l <- i2s sdo0_l
209
+ * i2s sdi0_r <- codec sdo_r
210
+ *
211
+ * lp mode2:
212
+ * i2s sdi0_l <- codec sdo_l
213
+ * i2s sdi0_r <- i2s sdo0_r
214
+ *
215
+ * lp mode1:
216
+ * i2s sdi0_l <- codec sdo_l
217
+ * i2s sdi0_r <- codec sdo_r
218
+ * i2s sdi1_l <- i2s sdo0_l
219
+ * i2s sdi1_r <- i2s sdo0_r
220
+ *
221
+ */
222
+#define I2S_XFER_LP_MODE_MASK	GENMASK(4, 2)
223
+#define I2S_XFER_LP_MODE_2_SWAP	(BIT(4) | BIT(3))
224
+#define I2S_XFER_LP_MODE_2	BIT(3)
225
+#define I2S_XFER_LP_MODE_1	BIT(2)
226
+#define I2S_XFER_LP_MODE_DIS	0
202227 #define I2S_XFER_RXS_SHIFT	1
203228 #define I2S_XFER_RXS_STOP	(0 << I2S_XFER_RXS_SHIFT)
204229 #define I2S_XFER_RXS_START	(1 << I2S_XFER_RXS_SHIFT)
230
+#define I2S_XFER_RXS_MASK	(1 << I2S_XFER_RXS_SHIFT)
231
+#define I2S_XFER_RXS(x)		((x) << I2S_XFER_RXS_SHIFT)
205232 #define I2S_XFER_TXS_SHIFT	0
206233 #define I2S_XFER_TXS_STOP	(0 << I2S_XFER_TXS_SHIFT)
207234 #define I2S_XFER_TXS_START	(1 << I2S_XFER_TXS_SHIFT)
235
+#define I2S_XFER_TXS_MASK	(1 << I2S_XFER_TXS_SHIFT)
236
+#define I2S_XFER_TXS(x)		((x) << I2S_XFER_TXS_SHIFT)
208237 
209238 /*
210239  * CLR