forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-11-07 f45e756958099c35d6afb746df1d40a1c6302cfc 
 kernel/arch/arm/boot/dts/rk3066a.dtsi
....@@ -465,10 +465,6 @@
465465 			bias-pull-pin-default;
466466 		};
467467 
468
-		pcfg_pull_up: pcfg-pull-up {
469
-			bias-pull-up;
470
-		};
471
-
472468 		pcfg_pull_none: pcfg_pull_none {
473469 			bias-disable;
474470 		};
....@@ -609,8 +605,8 @@
609605 
610606 		uart0 {
611607 			uart0_xfer: uart0-xfer {
612
-				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>,
613
-						<1 RK_PA1 1 &pcfg_pull_up>;
608
+				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
609
+						<1 RK_PA1 1 &pcfg_pull_default>;
614610 			};
615611 
616612 			uart0_cts: uart0-cts {
....@@ -624,8 +620,8 @@
624620 
625621 		uart1 {
626622 			uart1_xfer: uart1-xfer {
627
-				rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>,
628
-						<1 RK_PA5 1 &pcfg_pull_up>;
623
+				rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>,
624
+						<1 RK_PA5 1 &pcfg_pull_default>;
629625 			};
630626 
631627 			uart1_cts: uart1-cts {
....@@ -639,16 +635,16 @@
639635 
640636 		uart2 {
641637 			uart2_xfer: uart2-xfer {
642
-				rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>,
643
-						<1 RK_PB1 1 &pcfg_pull_up>;
638
+				rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
639
+						<1 RK_PB1 1 &pcfg_pull_default>;
644640 			};
645641 			/* no rts / cts for uart2 */
646642 		};
647643 
648644 		uart3 {
649645 			uart3_xfer: uart3-xfer {
650
-				rockchip,pins = <3 RK_PD3 1 &pcfg_pull_up>,
651
-						<3 RK_PD4 1 &pcfg_pull_up>;
646
+				rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
647
+						<3 RK_PD4 1 &pcfg_pull_default>;
652648 			};
653649 
654650 			uart3_cts: uart3-cts {