forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-10 ee930fffee469d076998274a2ca55e13dc1efb67
u-boot/arch/arm/include/asm/arch-rockchip/clock.h
....@@ -12,6 +12,13 @@
1212 #define RKCLK_PLL_MODE_NORMAL 1
1313 #define RKCLK_PLL_MODE_DEEP 2
1414
15
+/*
16
+ * PLL flags
17
+ */
18
+#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
19
+/* normal mode only. now only for pll_rk3036, pll_rk3328 type */
20
+#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
21
+
1522 enum {
1623 ROCKCHIP_SYSCON_NOC,
1724 ROCKCHIP_SYSCON_GRF,
....@@ -29,6 +36,7 @@
2936 ROCKCHIP_SYSCON_PIPE_PHY2_GRF,
3037 ROCKCHIP_SYSCON_VOP_GRF,
3138 ROCKCHIP_SYSCON_VO_GRF,
39
+ ROCKCHIP_SYSCON_IOC,
3240 };
3341
3442 /* Standard Rockchip clock numbers */