enable tun/tap/iptables

hc

2024-05-10 ee930fffee469d076998274a2ca55e13dc1efb67

 kernel/include/linux/platform_data/dma-dw.h
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@@ -1,20 +1,22 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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 /*
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  * Driver for the Synopsys DesignWare DMA Controller
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  *
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  * Copyright (C) 2007 Atmel Corporation
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  * Copyright (C) 2010-2011 ST Microelectronics
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #ifndef _PLATFORM_DATA_DMA_DW_H
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 #define _PLATFORM_DATA_DMA_DW_H
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-#include <linux/device.h>
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+#include <linux/bits.h>
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+#include <linux/types.h>
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 #define DW_DMA_MAX_NR_MASTERS	4
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 #define DW_DMA_MAX_NR_CHANNELS	8
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+#define DW_DMA_MIN_BURST	1
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+#define DW_DMA_MAX_BURST	256
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+
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+struct device;
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 /**
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  * struct dw_dma_slave - Controller-specific information about a slave
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@@ -24,6 +26,7 @@
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  * @dst_id:	dst request line
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  * @m_master:	memory master for transfers on allocated channel
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  * @p_master:	peripheral master for transfers on allocated channel
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+ * @channels:	mask of the channels permitted for allocation (zero value means any)
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  * @hs_polarity:set active low polarity of handshake interface
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  */
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 struct dw_dma_slave {
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 	u8			dst_id;
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 	u8			m_master;
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 	u8			p_master;
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+	u8			channels;
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 	bool			hs_polarity;
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 };
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 /**
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  * struct dw_dma_platform_data - Controller configuration parameters
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  * @nr_channels: Number of channels supported by hardware (max 8)
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- * @is_private: The device channels should be marked as private and not for
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- *	by the general purpose DMA channel allocator.
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- * @is_memcpy: The device channels do support memory-to-memory transfers.
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- * @is_idma32: The type of the DMA controller is iDMA32
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  * @chan_allocation_order: Allocate channels starting from 0 or 7
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  * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
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  * @block_size: Maximum block size supported by the controller
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@@ -49,13 +49,12 @@
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  * @data_width: Maximum data width supported by hardware per AHB master
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  *		(in bytes, power of 2)
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  * @multi_block: Multi block transfers supported by hardware per channel.
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+ * @max_burst: Maximum value of burst transaction size supported by hardware
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+ *	       per channel (in units of CTL.SRC_TR_WIDTH/CTL.DST_TR_WIDTH).
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  * @protctl: Protection control signals setting per channel.
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  */
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 struct dw_dma_platform_data {
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 	unsigned int	nr_channels;
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-	bool		is_private;
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-	bool		is_memcpy;
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-	bool		is_idma32;
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 #define CHAN_ALLOCATION_ASCENDING	0	/* zero to seven */
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 #define CHAN_ALLOCATION_DESCENDING	1	/* seven to zero */
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 	unsigned char	chan_allocation_order;
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@@ -66,6 +65,7 @@
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 	unsigned char	nr_masters;
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 	unsigned char	data_width[DW_DMA_MAX_NR_MASTERS];
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 	unsigned char	multi_block[DW_DMA_MAX_NR_CHANNELS];
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+	u32		max_burst[DW_DMA_MAX_NR_CHANNELS];
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 #define CHAN_PROTCTL_PRIVILEGED		BIT(0)
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 #define CHAN_PROTCTL_BUFFERABLE		BIT(1)
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 #define CHAN_PROTCTL_CACHEABLE		BIT(2)