enable tun/tap/iptables

hc

2024-05-10 ee930fffee469d076998274a2ca55e13dc1efb67

 kernel/include/dt-bindings/clock/exynos5420.h
..
..
@@ -1,13 +1,10 @@
1
+/* SPDX-License-Identifier: GPL-2.0 */
1
2
 /*
2
3
  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3
4
  * Author: Andrzej Hajda <a.hajda@samsung.com>
4
5
  *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License version 2 as
7
- * published by the Free Software Foundation.
8
- *
9
6
  * Device Tree binding constants for Exynos5420 clock controller.
10
-*/
7
+ */
11
8
 
12
9
 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
13
10
 #define _DT_BINDINGS_CLOCK_EXYNOS_5420_H
..
..
@@ -63,6 +60,7 @@
63
60
 #define CLK_MAU_EPLL		159
64
61
 #define CLK_SCLK_HSIC_12M	160
65
62
 #define CLK_SCLK_MPHY_IXTAL24	161
63
+#define CLK_SCLK_BPLL		162
66
64
 
67
65
 /* gate clocks */
68
66
 #define CLK_UART0		257
..
..
@@ -198,6 +196,16 @@
198
196
 #define CLK_ACLK432_CAM		518
199
197
 #define CLK_ACLK_FL1550_CAM	519
200
198
 #define CLK_ACLK550_CAM		520
199
+#define CLK_CLKM_PHY0		521
200
+#define CLK_CLKM_PHY1		522
201
+#define CLK_ACLK_PPMU_DREX0_0	523
202
+#define CLK_ACLK_PPMU_DREX0_1	524
203
+#define CLK_ACLK_PPMU_DREX1_0	525
204
+#define CLK_ACLK_PPMU_DREX1_1	526
205
+#define CLK_PCLK_PPMU_DREX0_0	527
206
+#define CLK_PCLK_PPMU_DREX0_1	528
207
+#define CLK_PCLK_PPMU_DREX1_0	529
208
+#define CLK_PCLK_PPMU_DREX1_1	530
201
209
 
202
210
 /* mux clocks */
203
211
 #define CLK_MOUT_HDMI		640
..
..
@@ -220,6 +228,14 @@
220
228
 #define CLK_MOUT_EPLL		657
221
229
 #define CLK_MOUT_MAU_EPLL	658
222
230
 #define CLK_MOUT_USER_MAU_EPLL	659
231
+#define CLK_MOUT_SCLK_SPLL	660
232
+#define CLK_MOUT_MX_MSPLL_CCORE_PHY	661
233
+#define CLK_MOUT_SW_ACLK_G3D	662
234
+#define CLK_MOUT_APLL		663
235
+#define CLK_MOUT_MSPLL_CPU	664
236
+#define CLK_MOUT_KPLL		665
237
+#define CLK_MOUT_MSPLL_KFC	666
238
+
223
239
 
224
240
 /* divider clocks */
225
241
 #define CLK_DOUT_PIXEL		768
..
..
@@ -251,8 +267,11 @@
251
267
 #define CLK_DOUT_CCLK_DREX0	794
252
268
 #define CLK_DOUT_CLK2X_PHY0	795
253
269
 #define CLK_DOUT_PCLK_CORE_MEM	796
270
+#define CLK_FF_DOUT_SPLL2	797
271
+#define CLK_DOUT_PCLK_DREX0	798
272
+#define CLK_DOUT_PCLK_DREX1	799
254
273
 
255
274
 /* must be greater than maximal clock id */
256
-#define CLK_NR_CLKS		797
275
+#define CLK_NR_CLKS		800
257
276
 
258
277
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */