| .. | .. |
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| 239 | 239 | #define EP_STATE_ENABLED 1 |
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| 240 | 240 | |
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| 241 | 241 | static const unsigned int pcie_gen_freq[] = { |
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| 242 | + GEN1_CORE_CLK_FREQ, /* PCI_EXP_LNKSTA_CLS == 0; undefined */ |
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| 242 | 243 | GEN1_CORE_CLK_FREQ, |
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| 243 | 244 | GEN2_CORE_CLK_FREQ, |
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| 244 | 245 | GEN3_CORE_CLK_FREQ, |
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| .. | .. |
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| 470 | 471 | |
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| 471 | 472 | speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & |
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| 472 | 473 | PCI_EXP_LNKSTA_CLS; |
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| 473 | | - clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); |
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| 474 | + |
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| 475 | + if (speed >= ARRAY_SIZE(pcie_gen_freq)) |
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| 476 | + speed = 0; |
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| 477 | + |
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| 478 | + clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]); |
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| 474 | 479 | |
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| 475 | 480 | /* If EP doesn't advertise L1SS, just return */ |
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| 476 | 481 | val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); |
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| .. | .. |
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| 973 | 978 | |
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| 974 | 979 | speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & |
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| 975 | 980 | PCI_EXP_LNKSTA_CLS; |
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| 976 | | - clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); |
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| 981 | + |
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| 982 | + if (speed >= ARRAY_SIZE(pcie_gen_freq)) |
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| 983 | + speed = 0; |
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| 984 | + |
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| 985 | + clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]); |
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| 977 | 986 | |
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| 978 | 987 | tegra_pcie_enable_interrupts(pp); |
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| 979 | 988 | |
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