enable tun/tap/iptables

hc

2024-05-10 ee930fffee469d076998274a2ca55e13dc1efb67

 kernel/drivers/pci/controller/dwc/pcie-spear13xx.c
..
..
@@ -26,7 +26,6 @@
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 	void __iomem		*app_base;
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 	struct phy		*phy;
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 	struct clk		*clk;
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-	bool			is_gen1;
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 };
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 struct pcie_app_reg {
..
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@@ -65,8 +64,6 @@
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 /* CR6 */
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 #define MSI_CTRL_INT				(1 << 26)
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-#define EXP_CAP_ID_OFFSET			0x70
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-
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 #define to_spear13xx_pcie(x)	dev_get_drvdata((x)->dev)
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68
 
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 static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
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@@ -75,7 +72,7 @@
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 	struct pcie_port *pp = &pci->pp;
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 	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
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 	u32 val;
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-	u32 exp_cap_off = EXP_CAP_ID_OFFSET;
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+	u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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 	if (dw_pcie_link_up(pci)) {
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 		dev_err(pci->dev, "link already up\n");
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@@ -89,36 +86,12 @@
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 	 * default value in capability register is 512 bytes. So force
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 	 * it to 128 here.
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 	 */
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-	dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
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+	val = dw_pcie_readw_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL);
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 	val &= ~PCI_EXP_DEVCTL_READRQ;
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-	dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
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+	dw_pcie_writew_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL, val);
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-	dw_pcie_write(pci->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
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-	dw_pcie_write(pci->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
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-
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-	/*
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-	 * if is_gen1 is set then handle it, so that some buggy card
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-	 * also works
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-	 */
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-	if (spear13xx_pcie->is_gen1) {
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-		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
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-			     4, &val);
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-		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
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-			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
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-			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
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-			dw_pcie_write(pci->dbi_base + exp_cap_off +
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-				      PCI_EXP_LNKCAP, 4, val);
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-		}
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-
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-		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
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-			     2, &val);
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-		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
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-			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
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-			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
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-			dw_pcie_write(pci->dbi_base + exp_cap_off +
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-				      PCI_EXP_LNKCTL2, 2, val);
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-		}
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-	}
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+	dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, 0x104A);
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+	dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, 0xCD80);
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 	/* enable ltssm */
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 	writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
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@@ -198,10 +171,9 @@
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 	int ret;
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 	pp->irq = platform_get_irq(pdev, 0);
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-	if (pp->irq < 0) {
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-		dev_err(dev, "failed to get irq\n");
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+	if (pp->irq < 0)
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 		return pp->irq;
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-	}
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+
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 	ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
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 			       IRQF_SHARED | IRQF_NO_THREAD,
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 			       "spear1340-pcie", spear13xx_pcie);
..
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@@ -273,14 +245,13 @@
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 	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
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 	pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
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 	if (IS_ERR(pci->dbi_base)) {
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-		dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
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 		ret = PTR_ERR(pci->dbi_base);
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 		goto fail_clk;
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 	}
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 	spear13xx_pcie->app_base = pci->dbi_base + 0x2000;
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 	if (of_property_read_bool(np, "st,pcie-is-gen1"))
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-		spear13xx_pcie->is_gen1 = true;
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+		pci->link_gen = 1;
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 	platform_set_drvdata(pdev, spear13xx_pcie);
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