forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-10 ee930fffee469d076998274a2ca55e13dc1efb67 
 kernel/drivers/pci/controller/dwc/pcie-kirin.c
....@@ -2,8 +2,8 @@
22 /*
33  * PCIe host controller driver for Kirin Phone SoCs
44  *
5
- * Copyright (C) 2017 Hilisicon Electronics Co., Ltd.
6
- *		http://www.huawei.com
5
+ * Copyright (C) 2017 HiSilicon Electronics Co., Ltd.
6
+ *		https://www.huawei.com
77  *
88  * Author: Xiaowei Song <songxiaowei@huawei.com>
99  */
....@@ -147,23 +147,18 @@
147147 static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
148148 				    struct platform_device *pdev)
149149 {
150
-	struct device *dev = &pdev->dev;
151
-	struct resource *apb;
152
-	struct resource *phy;
153
-	struct resource *dbi;
154
-
155
-	apb = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb");
156
-	kirin_pcie->apb_base = devm_ioremap_resource(dev, apb);
150
+	kirin_pcie->apb_base =
151
+		devm_platform_ioremap_resource_byname(pdev, "apb");
157152 	if (IS_ERR(kirin_pcie->apb_base))
158153 		return PTR_ERR(kirin_pcie->apb_base);
159154 
160
-	phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
161
-	kirin_pcie->phy_base = devm_ioremap_resource(dev, phy);
155
+	kirin_pcie->phy_base =
156
+		devm_platform_ioremap_resource_byname(pdev, "phy");
162157 	if (IS_ERR(kirin_pcie->phy_base))
163158 		return PTR_ERR(kirin_pcie->phy_base);
164159 
165
-	dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
166
-	kirin_pcie->pci->dbi_base = devm_ioremap_resource(dev, dbi);
160
+	kirin_pcie->pci->dbi_base =
161
+		devm_platform_ioremap_resource_byname(pdev, "dbi");
167162 	if (IS_ERR(kirin_pcie->pci->dbi_base))
168163 		return PTR_ERR(kirin_pcie->pci->dbi_base);
169164 
....@@ -335,33 +330,36 @@
335330 	kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR);
336331 }
337332 
338
-static int kirin_pcie_rd_own_conf(struct pcie_port *pp,
333
+static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
339334 				  int where, int size, u32 *val)
340335 {
341
-	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
342
-	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
343
-	int ret;
336
+	struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
344337 
345
-	kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
346
-	ret = dw_pcie_read(pci->dbi_base + where, size, val);
347
-	kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
338
+	if (PCI_SLOT(devfn)) {
339
+		*val = ~0;
340
+		return PCIBIOS_DEVICE_NOT_FOUND;
341
+	}
348342 
349
-	return ret;
343
+	*val = dw_pcie_read_dbi(pci, where, size);
344
+	return PCIBIOS_SUCCESSFUL;
350345 }
351346 
352
-static int kirin_pcie_wr_own_conf(struct pcie_port *pp,
347
+static int kirin_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn,
353348 				  int where, int size, u32 val)
354349 {
355
-	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
356
-	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
357
-	int ret;
350
+	struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
358351 
359
-	kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
360
-	ret = dw_pcie_write(pci->dbi_base + where, size, val);
361
-	kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
352
+	if (PCI_SLOT(devfn))
353
+		return PCIBIOS_DEVICE_NOT_FOUND;
362354 
363
-	return ret;
355
+	dw_pcie_write_dbi(pci, where, size, val);
356
+	return PCIBIOS_SUCCESSFUL;
364357 }
358
+
359
+static struct pci_ops kirin_pci_ops = {
360
+	.read = kirin_pcie_rd_own_conf,
361
+	.write = kirin_pcie_wr_own_conf,
362
+};
365363 
366364 static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
367365 			       u32 reg, size_t size)
....@@ -428,23 +426,21 @@
428426 
429427 static int kirin_pcie_host_init(struct pcie_port *pp)
430428 {
431
-	kirin_pcie_establish_link(pp);
429
+	pp->bridge->ops = &kirin_pci_ops;
432430 
433
-	if (IS_ENABLED(CONFIG_PCI_MSI))
434
-		dw_pcie_msi_init(pp);
431
+	kirin_pcie_establish_link(pp);
432
+	dw_pcie_msi_init(pp);
435433 
436434 	return 0;
437435 }
438436 
439
-static struct dw_pcie_ops kirin_dw_pcie_ops = {
437
+static const struct dw_pcie_ops kirin_dw_pcie_ops = {
440438 	.read_dbi = kirin_pcie_read_dbi,
441439 	.write_dbi = kirin_pcie_write_dbi,
442440 	.link_up = kirin_pcie_link_up,
443441 };
444442 
445443 static const struct dw_pcie_host_ops kirin_pcie_host_ops = {
446
-	.rd_own_conf = kirin_pcie_rd_own_conf,
447
-	.wr_own_conf = kirin_pcie_wr_own_conf,
448444 	.host_init = kirin_pcie_host_init,
449445 };
450446 
....@@ -455,11 +451,8 @@
455451 
456452 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
457453 		irq = platform_get_irq(pdev, 0);
458
-		if (irq < 0) {
459
-			dev_err(&pdev->dev,
460
-				"failed to get MSI IRQ (%d)\n", irq);
454
+		if (irq < 0)
461455 			return irq;
462
-		}
463456 
464457 		pci->pp.msi_irq = irq;
465458 	}
....@@ -515,8 +508,12 @@
515508 
516509 	kirin_pcie->gpio_id_reset = of_get_named_gpio(dev->of_node,
517510 						      "reset-gpios", 0);
518
-	if (kirin_pcie->gpio_id_reset < 0)
511
+	if (kirin_pcie->gpio_id_reset == -EPROBE_DEFER) {
512
+		return -EPROBE_DEFER;
513
+	} else if (!gpio_is_valid(kirin_pcie->gpio_id_reset)) {
514
+		dev_err(dev, "unable to get a valid gpio pin\n");
519515 		return -ENODEV;
516
+	}
520517 
521518 	ret = kirin_pcie_power_on(kirin_pcie);
522519 	if (ret)