enable tun/tap/iptables

hc

2024-05-10 ee930fffee469d076998274a2ca55e13dc1efb67

 kernel/drivers/pci/controller/dwc/pcie-histb.c
..
..
@@ -122,31 +122,36 @@
122
122
 	histb_pcie_dbi_w_mode(&pci->pp, false);
123
123
 }
124
124
 
125
-static int histb_pcie_rd_own_conf(struct pcie_port *pp, int where,
126
-				  int size, u32 *val)
125
+static int histb_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
126
+				  int where, int size, u32 *val)
127
127
 {
128
-	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
129
-	int ret;
128
+	struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
130
129
 
131
-	histb_pcie_dbi_r_mode(pp, true);
132
-	ret = dw_pcie_read(pci->dbi_base + where, size, val);
133
-	histb_pcie_dbi_r_mode(pp, false);
130
+	if (PCI_SLOT(devfn)) {
131
+		*val = ~0;
132
+		return PCIBIOS_DEVICE_NOT_FOUND;
133
+	}
134
134
 
135
-	return ret;
135
+	*val = dw_pcie_read_dbi(pci, where, size);
136
+	return PCIBIOS_SUCCESSFUL;
136
137
 }
137
138
 
138
-static int histb_pcie_wr_own_conf(struct pcie_port *pp, int where,
139
-				  int size, u32 val)
139
+static int histb_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn,
140
+				  int where, int size, u32 val)
140
141
 {
141
-	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
142
-	int ret;
142
+	struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
143
143
 
144
-	histb_pcie_dbi_w_mode(pp, true);
145
-	ret = dw_pcie_write(pci->dbi_base + where, size, val);
146
-	histb_pcie_dbi_w_mode(pp, false);
144
+	if (PCI_SLOT(devfn))
145
+		return PCIBIOS_DEVICE_NOT_FOUND;
147
146
 
148
-	return ret;
147
+	dw_pcie_write_dbi(pci, where, size, val);
148
+	return PCIBIOS_SUCCESSFUL;
149
149
 }
150
+
151
+static struct pci_ops histb_pci_ops = {
152
+	.read = histb_pcie_rd_own_conf,
153
+	.write = histb_pcie_wr_own_conf,
154
+};
150
155
 
151
156
 static int histb_pcie_link_up(struct dw_pcie *pci)
152
157
 {
..
..
@@ -194,17 +199,15 @@
194
199
 
195
200
 static int histb_pcie_host_init(struct pcie_port *pp)
196
201
 {
197
-	histb_pcie_establish_link(pp);
202
+	pp->bridge->ops = &histb_pci_ops;
198
203
 
199
-	if (IS_ENABLED(CONFIG_PCI_MSI))
200
-		dw_pcie_msi_init(pp);
204
+	histb_pcie_establish_link(pp);
205
+	dw_pcie_msi_init(pp);
201
206
 
202
207
 	return 0;
203
208
 }
204
209
 
205
-static struct dw_pcie_host_ops histb_pcie_host_ops = {
206
-	.rd_own_conf = histb_pcie_rd_own_conf,
207
-	.wr_own_conf = histb_pcie_wr_own_conf,
210
+static const struct dw_pcie_host_ops histb_pcie_host_ops = {
208
211
 	.host_init = histb_pcie_host_init,
209
212
 };
210
213
 
..
..
@@ -304,7 +307,6 @@
304
307
 	struct histb_pcie *hipcie;
305
308
 	struct dw_pcie *pci;
306
309
 	struct pcie_port *pp;
307
-	struct resource *res;
308
310
 	struct device_node *np = pdev->dev.of_node;
309
311
 	struct device *dev = &pdev->dev;
310
312
 	enum of_gpio_flags of_flags;
..
..
@@ -324,15 +326,13 @@
324
326
 	pci->dev = dev;
325
327
 	pci->ops = &dw_pcie_ops;
326
328
 
327
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");
328
-	hipcie->ctrl = devm_ioremap_resource(dev, res);
329
+	hipcie->ctrl = devm_platform_ioremap_resource_byname(pdev, "control");
329
330
 	if (IS_ERR(hipcie->ctrl)) {
330
331
 		dev_err(dev, "cannot get control reg base\n");
331
332
 		return PTR_ERR(hipcie->ctrl);
332
333
 	}
333
334
 
334
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc-dbi");
335
-	pci->dbi_base = devm_ioremap_resource(dev, res);
335
+	pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc-dbi");
336
336
 	if (IS_ERR(pci->dbi_base)) {
337
337
 		dev_err(dev, "cannot get rc-dbi base\n");
338
338
 		return PTR_ERR(pci->dbi_base);
..
..
@@ -402,10 +402,8 @@
402
402
 
403
403
 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
404
404
 		pp->msi_irq = platform_get_irq_byname(pdev, "msi");
405
-		if (pp->msi_irq < 0) {
406
-			dev_err(dev, "Failed to get MSI IRQ\n");
405
+		if (pp->msi_irq < 0)
407
406
 			return pp->msi_irq;
408
-		}
409
407
 	}
410
408
 
411
409
 	hipcie->phy = devm_phy_get(dev, "phy");