forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-10 ee930fffee469d076998274a2ca55e13dc1efb67 
 kernel/drivers/pci/controller/dwc/pcie-artpec6.c
....@@ -44,16 +44,6 @@
4444 
4545 static const struct of_device_id artpec6_pcie_of_match[];
4646 
47
-/* PCIe Port Logic registers (memory-mapped) */
48
-#define PL_OFFSET			0x700
49
-
50
-#define ACK_F_ASPM_CTRL_OFF		(PL_OFFSET + 0xc)
51
-#define ACK_N_FTS_MASK			GENMASK(15, 8)
52
-#define ACK_N_FTS(x)			(((x) << 8) & ACK_N_FTS_MASK)
53
-
54
-#define FAST_TRAINING_SEQ_MASK		GENMASK(7, 0)
55
-#define FAST_TRAINING_SEQ(x)		(((x) << 0) & FAST_TRAINING_SEQ_MASK)
56
-
5747 /* ARTPEC-6 specific registers */
5848 #define PCIECFG				0x18
5949 #define  PCIECFG_DBG_OEN		BIT(24)
....@@ -292,33 +282,6 @@
292282 	}
293283 }
294284 
295
-static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie)
296
-{
297
-	struct dw_pcie *pci = artpec6_pcie->pci;
298
-	u32 val;
299
-
300
-	if (artpec6_pcie->variant != ARTPEC7)
301
-		return;
302
-
303
-	/*
304
-	 * Increase the N_FTS (Number of Fast Training Sequences)
305
-	 * to be transmitted when transitioning from L0s to L0.
306
-	 */
307
-	val = dw_pcie_readl_dbi(pci, ACK_F_ASPM_CTRL_OFF);
308
-	val &= ~ACK_N_FTS_MASK;
309
-	val |= ACK_N_FTS(180);
310
-	dw_pcie_writel_dbi(pci, ACK_F_ASPM_CTRL_OFF, val);
311
-
312
-	/*
313
-	 * Set the Number of Fast Training Sequences that the core
314
-	 * advertises as its N_FTS during Gen2 or Gen3 link training.
315
-	 */
316
-	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
317
-	val &= ~FAST_TRAINING_SEQ_MASK;
318
-	val |= FAST_TRAINING_SEQ(180);
319
-	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
320
-}
321
-
322285 static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
323286 {
324287 	u32 val;
....@@ -352,29 +315,23 @@
352315 	usleep_range(100, 200);
353316 }
354317 
355
-static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
356
-{
357
-	struct dw_pcie *pci = artpec6_pcie->pci;
358
-	struct pcie_port *pp = &pci->pp;
359
-
360
-	if (IS_ENABLED(CONFIG_PCI_MSI))
361
-		dw_pcie_msi_init(pp);
362
-}
363
-
364318 static int artpec6_pcie_host_init(struct pcie_port *pp)
365319 {
366320 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
367321 	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
368322 
323
+	if (artpec6_pcie->variant == ARTPEC7) {
324
+		pci->n_fts[0] = 180;
325
+		pci->n_fts[1] = 180;
326
+	}
369327 	artpec6_pcie_assert_core_reset(artpec6_pcie);
370328 	artpec6_pcie_init_phy(artpec6_pcie);
371329 	artpec6_pcie_deassert_core_reset(artpec6_pcie);
372330 	artpec6_pcie_wait_for_phy(artpec6_pcie);
373
-	artpec6_pcie_set_nfts(artpec6_pcie);
374331 	dw_pcie_setup_rc(pp);
375332 	artpec6_pcie_establish_link(pci);
376333 	dw_pcie_wait_for_link(pci);
377
-	artpec6_pcie_enable_interrupts(artpec6_pcie);
334
+	dw_pcie_msi_init(pp);
378335 
379336 	return 0;
380337 }
....@@ -393,10 +350,8 @@
393350 
394351 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
395352 		pp->msi_irq = platform_get_irq_byname(pdev, "msi");
396
-		if (pp->msi_irq < 0) {
397
-			dev_err(dev, "failed to get MSI irq\n");
353
+		if (pp->msi_irq < 0)
398354 			return pp->msi_irq;
399
-		}
400355 	}
401356 
402357 	pp->ops = &artpec6_pcie_host_ops;
....@@ -420,9 +375,8 @@
420375 	artpec6_pcie_init_phy(artpec6_pcie);
421376 	artpec6_pcie_deassert_core_reset(artpec6_pcie);
422377 	artpec6_pcie_wait_for_phy(artpec6_pcie);
423
-	artpec6_pcie_set_nfts(artpec6_pcie);
424378 
425
-	for (bar = BAR_0; bar <= BAR_5; bar++)
379
+	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
426380 		dw_pcie_ep_reset_bar(pci, bar);
427381 }
428382 
....@@ -444,7 +398,7 @@
444398 	return 0;
445399 }
446400 
447
-static struct dw_pcie_ep_ops pcie_ep_ops = {
401
+static const struct dw_pcie_ep_ops pcie_ep_ops = {
448402 	.ep_init = artpec6_pcie_ep_init,
449403 	.raise_irq = artpec6_pcie_raise_irq,
450404 };
....@@ -461,8 +415,7 @@
461415 	ep = &pci->ep;
462416 	ep->ops = &pcie_ep_ops;
463417 
464
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
465
-	pci->dbi_base2 = devm_ioremap_resource(dev, res);
418
+	pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2");
466419 	if (IS_ERR(pci->dbi_base2))
467420 		return PTR_ERR(pci->dbi_base2);
468421 
....@@ -487,8 +440,6 @@
487440 	struct device *dev = &pdev->dev;
488441 	struct dw_pcie *pci;
489442 	struct artpec6_pcie *artpec6_pcie;
490
-	struct resource *dbi_base;
491
-	struct resource *phy_base;
492443 	int ret;
493444 	const struct of_device_id *match;
494445 	const struct artpec_pcie_of_data *data;
....@@ -518,13 +469,12 @@
518469 	artpec6_pcie->variant = variant;
519470 	artpec6_pcie->mode = mode;
520471 
521
-	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
522
-	pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
472
+	pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi");
523473 	if (IS_ERR(pci->dbi_base))
524474 		return PTR_ERR(pci->dbi_base);
525475 
526
-	phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
527
-	artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
476
+	artpec6_pcie->phy_base =
477
+		devm_platform_ioremap_resource_byname(pdev, "phy");
528478 	if (IS_ERR(artpec6_pcie->phy_base))
529479 		return PTR_ERR(artpec6_pcie->phy_base);
530480