| .. | .. |
|---|
| 7 | 7 | bool |
|---|
| 8 | 8 | |
|---|
| 9 | 9 | config PCIE_DW_HOST |
|---|
| 10 | | - bool |
|---|
| 10 | + bool |
|---|
| 11 | 11 | depends on PCI_MSI_IRQ_DOMAIN |
|---|
| 12 | | - select PCIE_DW |
|---|
| 12 | + select PCIE_DW |
|---|
| 13 | 13 | |
|---|
| 14 | 14 | config PCIE_DW_EP |
|---|
| 15 | 15 | bool |
|---|
| .. | .. |
|---|
| 26 | 26 | depends on OF && HAS_IOMEM && TI_PIPE3 |
|---|
| 27 | 27 | select PCIE_DW_HOST |
|---|
| 28 | 28 | select PCI_DRA7XX |
|---|
| 29 | | - default y |
|---|
| 29 | + default y if SOC_DRA7XX |
|---|
| 30 | 30 | help |
|---|
| 31 | 31 | Enables support for the PCIe controller in the DRA7xx SoC to work in |
|---|
| 32 | 32 | host mode. There are two instances of PCIe controller in DRA7xx. |
|---|
| .. | .. |
|---|
| 83 | 83 | selected. |
|---|
| 84 | 84 | |
|---|
| 85 | 85 | config PCIE_DW_ROCKCHIP |
|---|
| 86 | | - bool "Rockchip DesignWare PCIe controller" |
|---|
| 86 | + tristate "Rockchip DesignWare PCIe controller" |
|---|
| 87 | 87 | select PCIE_DW |
|---|
| 88 | 88 | select PCIE_DW_HOST |
|---|
| 89 | 89 | depends on ARCH_ROCKCHIP |
|---|
| 90 | 90 | depends on OF |
|---|
| 91 | 91 | help |
|---|
| 92 | 92 | Enables support for the DW PCIe controller in the Rockchip SoC. |
|---|
| 93 | + |
|---|
| 94 | +config PCIE_RK_THREADED_INIT |
|---|
| 95 | + bool "Threaded initialize Rockchip DW based PCIe controller" |
|---|
| 96 | + depends on PCIE_DW_ROCKCHIP |
|---|
| 97 | + default y |
|---|
| 98 | + help |
|---|
| 99 | + Enables threaded initialize Rockchip DW based PCIe controller. |
|---|
| 93 | 100 | |
|---|
| 94 | 101 | config PCIE_DW_DMATEST |
|---|
| 95 | 102 | bool "DesignWare PCIe DMA test" |
|---|
| .. | .. |
|---|
| 106 | 113 | help |
|---|
| 107 | 114 | Enables support for the DW PCIe controller in the Rockchip SoC. |
|---|
| 108 | 115 | |
|---|
| 109 | | -config PCIE_RK_THREADED_INIT |
|---|
| 110 | | - bool "Threaded initialize Rockchip DW based PCIe controller" |
|---|
| 111 | | - depends on PCIE_DW_ROCKCHIP |
|---|
| 112 | | - default y |
|---|
| 113 | | - help |
|---|
| 114 | | - Enables threaded initialize Rockchip DW based PCIe controller. |
|---|
| 115 | | - |
|---|
| 116 | 116 | config PCI_EXYNOS |
|---|
| 117 | 117 | bool "Samsung Exynos PCIe controller" |
|---|
| 118 | 118 | depends on SOC_EXYNOS5440 || COMPILE_TEST |
|---|
| .. | .. |
|---|
| 120 | 120 | select PCIE_DW_HOST |
|---|
| 121 | 121 | |
|---|
| 122 | 122 | config PCI_IMX6 |
|---|
| 123 | | - bool "Freescale i.MX6 PCIe controller" |
|---|
| 124 | | - depends on SOC_IMX6Q || (ARM && COMPILE_TEST) |
|---|
| 123 | + bool "Freescale i.MX6/7/8 PCIe controller" |
|---|
| 124 | + depends on ARCH_MXC || COMPILE_TEST |
|---|
| 125 | 125 | depends on PCI_MSI_IRQ_DOMAIN |
|---|
| 126 | 126 | select PCIE_DW_HOST |
|---|
| 127 | 127 | |
|---|
| .. | .. |
|---|
| 134 | 134 | Say Y here if you want PCIe support on SPEAr13XX SoCs. |
|---|
| 135 | 135 | |
|---|
| 136 | 136 | config PCI_KEYSTONE |
|---|
| 137 | | - bool "TI Keystone PCIe controller" |
|---|
| 138 | | - depends on ARCH_KEYSTONE || (ARM && COMPILE_TEST) |
|---|
| 137 | + bool |
|---|
| 138 | + |
|---|
| 139 | +config PCI_KEYSTONE_HOST |
|---|
| 140 | + bool "PCI Keystone Host Mode" |
|---|
| 141 | + depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) |
|---|
| 139 | 142 | depends on PCI_MSI_IRQ_DOMAIN |
|---|
| 140 | 143 | select PCIE_DW_HOST |
|---|
| 144 | + select PCI_KEYSTONE |
|---|
| 141 | 145 | help |
|---|
| 142 | | - Say Y here if you want to enable PCI controller support on Keystone |
|---|
| 143 | | - SoCs. The PCI controller on Keystone is based on DesignWare hardware |
|---|
| 144 | | - and therefore the driver re-uses the DesignWare core functions to |
|---|
| 145 | | - implement the driver. |
|---|
| 146 | + Enables support for the PCIe controller in the Keystone SoC to |
|---|
| 147 | + work in host mode. The PCI controller on Keystone is based on |
|---|
| 148 | + DesignWare hardware and therefore the driver re-uses the |
|---|
| 149 | + DesignWare core functions to implement the driver. |
|---|
| 150 | + |
|---|
| 151 | +config PCI_KEYSTONE_EP |
|---|
| 152 | + bool "PCI Keystone Endpoint Mode" |
|---|
| 153 | + depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) |
|---|
| 154 | + depends on PCI_ENDPOINT |
|---|
| 155 | + select PCIE_DW_EP |
|---|
| 156 | + select PCI_KEYSTONE |
|---|
| 157 | + help |
|---|
| 158 | + Enables support for the PCIe controller in the Keystone SoC to |
|---|
| 159 | + work in endpoint mode. The PCI controller on Keystone is based |
|---|
| 160 | + on DesignWare hardware and therefore the driver re-uses the |
|---|
| 161 | + DesignWare core functions to implement the driver. |
|---|
| 146 | 162 | |
|---|
| 147 | 163 | config PCI_LAYERSCAPE |
|---|
| 148 | | - bool "Freescale Layerscape PCIe controller" |
|---|
| 164 | + bool "Freescale Layerscape PCIe controller - Host mode" |
|---|
| 149 | 165 | depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) |
|---|
| 150 | 166 | depends on PCI_MSI_IRQ_DOMAIN |
|---|
| 151 | 167 | select MFD_SYSCON |
|---|
| 152 | 168 | select PCIE_DW_HOST |
|---|
| 153 | 169 | help |
|---|
| 154 | | - Say Y here if you want PCIe controller support on Layerscape SoCs. |
|---|
| 170 | + Say Y here if you want to enable PCIe controller support on Layerscape |
|---|
| 171 | + SoCs to work in Host mode. |
|---|
| 172 | + This controller can work either as EP or RC. The RCW[HOST_AGT_PEX] |
|---|
| 173 | + determines which PCIe controller works in EP mode and which PCIe |
|---|
| 174 | + controller works in RC mode. |
|---|
| 175 | + |
|---|
| 176 | +config PCI_LAYERSCAPE_EP |
|---|
| 177 | + bool "Freescale Layerscape PCIe controller - Endpoint mode" |
|---|
| 178 | + depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) |
|---|
| 179 | + depends on PCI_ENDPOINT |
|---|
| 180 | + select PCIE_DW_EP |
|---|
| 181 | + help |
|---|
| 182 | + Say Y here if you want to enable PCIe controller support on Layerscape |
|---|
| 183 | + SoCs to work in Endpoint mode. |
|---|
| 184 | + This controller can work either as EP or RC. The RCW[HOST_AGT_PEX] |
|---|
| 185 | + determines which PCIe controller works in EP mode and which PCIe |
|---|
| 186 | + controller works in RC mode. |
|---|
| 155 | 187 | |
|---|
| 156 | 188 | config PCI_HISI |
|---|
| 157 | 189 | depends on OF && (ARM64 || COMPILE_TEST) |
|---|
| .. | .. |
|---|
| 207 | 239 | Enables support for the PCIe controller in the ARTPEC-6 SoC to work in |
|---|
| 208 | 240 | endpoint mode. This uses the DesignWare core. |
|---|
| 209 | 241 | |
|---|
| 242 | +config PCIE_INTEL_GW |
|---|
| 243 | + bool "Intel Gateway PCIe host controller support" |
|---|
| 244 | + depends on OF && (X86 || COMPILE_TEST) |
|---|
| 245 | + depends on PCI_MSI_IRQ_DOMAIN |
|---|
| 246 | + select PCIE_DW_HOST |
|---|
| 247 | + help |
|---|
| 248 | + Say 'Y' here to enable PCIe Host controller support on Intel |
|---|
| 249 | + Gateway SoCs. |
|---|
| 250 | + The PCIe controller uses the DesignWare core plus Intel-specific |
|---|
| 251 | + hardware wrappers. |
|---|
| 252 | + |
|---|
| 210 | 253 | config PCIE_KIRIN |
|---|
| 211 | 254 | depends on OF && (ARM64 || COMPILE_TEST) |
|---|
| 212 | 255 | bool "HiSilicon Kirin series SoCs PCIe controllers" |
|---|
| .. | .. |
|---|
| 222 | 265 | depends on PCI_MSI_IRQ_DOMAIN |
|---|
| 223 | 266 | select PCIE_DW_HOST |
|---|
| 224 | 267 | help |
|---|
| 225 | | - Say Y here if you want PCIe controller support on HiSilicon STB SoCs |
|---|
| 268 | + Say Y here if you want PCIe controller support on HiSilicon STB SoCs |
|---|
| 269 | + |
|---|
| 270 | +config PCI_MESON |
|---|
| 271 | + tristate "MESON PCIe controller" |
|---|
| 272 | + depends on PCI_MSI_IRQ_DOMAIN |
|---|
| 273 | + default m if ARCH_MESON |
|---|
| 274 | + select PCIE_DW_HOST |
|---|
| 275 | + help |
|---|
| 276 | + Say Y here if you want to enable PCI controller support on Amlogic |
|---|
| 277 | + SoCs. The PCI controller on Amlogic is based on DesignWare hardware |
|---|
| 278 | + and therefore the driver re-uses the DesignWare core functions to |
|---|
| 279 | + implement the driver. |
|---|
| 280 | + |
|---|
| 281 | +config PCIE_TEGRA194 |
|---|
| 282 | + tristate |
|---|
| 283 | + |
|---|
| 284 | +config PCIE_TEGRA194_HOST |
|---|
| 285 | + tristate "NVIDIA Tegra194 (and later) PCIe controller - Host Mode" |
|---|
| 286 | + depends on ARCH_TEGRA_194_SOC || COMPILE_TEST |
|---|
| 287 | + depends on PCI_MSI_IRQ_DOMAIN |
|---|
| 288 | + select PCIE_DW_HOST |
|---|
| 289 | + select PHY_TEGRA194_P2U |
|---|
| 290 | + select PCIE_TEGRA194 |
|---|
| 291 | + help |
|---|
| 292 | + Enables support for the PCIe controller in the NVIDIA Tegra194 SoC to |
|---|
| 293 | + work in host mode. There are two instances of PCIe controllers in |
|---|
| 294 | + Tegra194. This controller can work either as EP or RC. In order to |
|---|
| 295 | + enable host-specific features PCIE_TEGRA194_HOST must be selected and |
|---|
| 296 | + in order to enable device-specific features PCIE_TEGRA194_EP must be |
|---|
| 297 | + selected. This uses the DesignWare core. |
|---|
| 298 | + |
|---|
| 299 | +config PCIE_TEGRA194_EP |
|---|
| 300 | + tristate "NVIDIA Tegra194 (and later) PCIe controller - Endpoint Mode" |
|---|
| 301 | + depends on ARCH_TEGRA_194_SOC || COMPILE_TEST |
|---|
| 302 | + depends on PCI_ENDPOINT |
|---|
| 303 | + select PCIE_DW_EP |
|---|
| 304 | + select PHY_TEGRA194_P2U |
|---|
| 305 | + select PCIE_TEGRA194 |
|---|
| 306 | + help |
|---|
| 307 | + Enables support for the PCIe controller in the NVIDIA Tegra194 SoC to |
|---|
| 308 | + work in host mode. There are two instances of PCIe controllers in |
|---|
| 309 | + Tegra194. This controller can work either as EP or RC. In order to |
|---|
| 310 | + enable host-specific features PCIE_TEGRA194_HOST must be selected and |
|---|
| 311 | + in order to enable device-specific features PCIE_TEGRA194_EP must be |
|---|
| 312 | + selected. This uses the DesignWare core. |
|---|
| 313 | + |
|---|
| 314 | +config PCIE_UNIPHIER |
|---|
| 315 | + bool "Socionext UniPhier PCIe host controllers" |
|---|
| 316 | + depends on ARCH_UNIPHIER || COMPILE_TEST |
|---|
| 317 | + depends on OF && HAS_IOMEM |
|---|
| 318 | + depends on PCI_MSI_IRQ_DOMAIN |
|---|
| 319 | + select PCIE_DW_HOST |
|---|
| 320 | + help |
|---|
| 321 | + Say Y here if you want PCIe host controller support on UniPhier SoCs. |
|---|
| 322 | + This driver supports LD20 and PXs3 SoCs. |
|---|
| 323 | + |
|---|
| 324 | +config PCIE_UNIPHIER_EP |
|---|
| 325 | + bool "Socionext UniPhier PCIe endpoint controllers" |
|---|
| 326 | + depends on ARCH_UNIPHIER || COMPILE_TEST |
|---|
| 327 | + depends on OF && HAS_IOMEM |
|---|
| 328 | + depends on PCI_ENDPOINT |
|---|
| 329 | + select PCIE_DW_EP |
|---|
| 330 | + help |
|---|
| 331 | + Say Y here if you want PCIe endpoint controller support on |
|---|
| 332 | + UniPhier SoCs. This driver supports Pro5 SoC. |
|---|
| 333 | + |
|---|
| 334 | +config PCIE_AL |
|---|
| 335 | + bool "Amazon Annapurna Labs PCIe controller" |
|---|
| 336 | + depends on OF && (ARM64 || COMPILE_TEST) |
|---|
| 337 | + depends on PCI_MSI_IRQ_DOMAIN |
|---|
| 338 | + select PCIE_DW_HOST |
|---|
| 339 | + help |
|---|
| 340 | + Say Y here to enable support of the Amazon's Annapurna Labs PCIe |
|---|
| 341 | + controller IP on Amazon SoCs. The PCIe controller uses the DesignWare |
|---|
| 342 | + core plus Annapurna Labs proprietary hardware wrappers. This is |
|---|
| 343 | + required only for DT-based platforms. ACPI platforms with the |
|---|
| 344 | + Annapurna Labs PCIe controller don't need to enable this. |
|---|
| 226 | 345 | |
|---|
| 227 | 346 | endmenu |
|---|