enable tun/tap/iptables

hc

2024-05-10 ee930fffee469d076998274a2ca55e13dc1efb67

 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
..
..
@@ -1,17 +1,7 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*******************************************************************************
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   Copyright (C) 2007-2009  STMicroelectronics Ltd
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-  This program is free software; you can redistribute it and/or modify it
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-  under the terms and conditions of the GNU General Public License,
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-  version 2, as published by the Free Software Foundation.
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-
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-  This program is distributed in the hope it will be useful, but WITHOUT
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-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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-  more details.
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-
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-  The full GNU General Public License is included in this distribution in
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-  the file called "COPYING".
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5
 
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   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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 *******************************************************************************/
..
..
@@ -26,19 +16,14 @@
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 int dwmac_dma_reset(void __iomem *ioaddr)
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 {
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 	u32 value = readl(ioaddr + DMA_BUS_MODE);
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-	int err;
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 	/* DMA SW reset */
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 	value |= DMA_BUS_MODE_SFT_RESET;
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 	writel(value, ioaddr + DMA_BUS_MODE);
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-	err = readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
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+	return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
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 				 !(value & DMA_BUS_MODE_SFT_RESET),
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-				 10000, 100000);
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-	if (err)
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-		return -EBUSY;
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-
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-	return 0;
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+				 10000, 200000);
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 }
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 /* CSR1 enables the transmit DMA to check for new descriptor */
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@@ -47,14 +32,28 @@
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 	writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
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 }
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-void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan)
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+void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
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 {
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-	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
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+	u32 value = readl(ioaddr + DMA_INTR_ENA);
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+
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+	if (rx)
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+		value |= DMA_INTR_DEFAULT_RX;
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+	if (tx)
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+		value |= DMA_INTR_DEFAULT_TX;
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+
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+	writel(value, ioaddr + DMA_INTR_ENA);
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 }
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-void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan)
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+void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
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 {
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-	writel(0, ioaddr + DMA_INTR_ENA);
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+	u32 value = readl(ioaddr + DMA_INTR_ENA);
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+
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+	if (rx)
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+		value &= ~DMA_INTR_DEFAULT_RX;
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+	if (tx)
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+		value &= ~DMA_INTR_DEFAULT_TX;
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+
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+	writel(value, ioaddr + DMA_INTR_ENA);
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 }
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58
 
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 void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)