~hc/RK356X_SDK_RELEASE.git

..	..	@@ -69,16 +69,16 @@
69	69	struct hns_roce_wqe_data_seg *dseg = NULL;
70	70	struct hns_roce_qp *qp = to_hr_qp(ibqp);
71	71	struct device *dev = &hr_dev->pdev->dev;
72		- struct hns_roce_sq_db sq_db;
73		- int ps_opcode = 0, i = 0;
	72	+ struct hns_roce_sq_db sq_db = {};
	73	+ int ps_opcode, i;
74	74	unsigned long flags = 0;
75	75	void *wqe = NULL;
76		- u32 doorbell[2];
77		- int nreq = 0;
78		- u32 ind = 0;
	76	+ __le32 doorbell[2];
79	77	int ret = 0;
80		- u8 *smac;
81	78	int loopback;
	79	+ u32 wqe_idx;
	80	+ int nreq;
	81	+ u8 *smac;
82	82
83	83	if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
84	84	ibqp->qp_type != IB_QPT_RC)) {
..	..	@@ -88,13 +88,15 @@
88	88	}
89	89
90	90	spin_lock_irqsave(&qp->sq.lock, flags);
91		- ind = qp->sq_next_wqe;
	91	+
92	92	for (nreq = 0; wr; ++nreq, wr = wr->next) {
93	93	if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
94	94	ret = -ENOMEM;
95	95	*bad_wr = wr;
96	96	goto out;
97	97	}
	98	+
	99	+ wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
98	100
99	101	if (unlikely(wr->num_sge > qp->sq.max_gs)) {
100	102	dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
..	..	@@ -104,9 +106,8 @@
104	106	goto out;
105	107	}
106	108
107		- wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
108		- qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
109		- wr->wr_id;
	109	+ wqe = hns_roce_get_send_wqe(qp, wqe_idx);
	110	+ qp->sq.wrid[wqe_idx] = wr->wr_id;
110	111
111	112	/* Corresponding to the RC and RD type wqe process separately */
112	113	if (ibqp->qp_type == IB_QPT_GSI) {
..	..	@@ -175,13 +176,11 @@
175	176	roce_set_field(ud_sq_wqe->u32_36,
176	177	UD_SEND_WQE_U32_36_FLOW_LABEL_M,
177	178	UD_SEND_WQE_U32_36_FLOW_LABEL_S,
178		- ah->av.sl_tclass_flowlabel &
179		- HNS_ROCE_FLOW_LABEL_MASK);
	179	+ ah->av.flowlabel);
180	180	roce_set_field(ud_sq_wqe->u32_36,
181	181	UD_SEND_WQE_U32_36_PRIORITY_M,
182	182	UD_SEND_WQE_U32_36_PRIORITY_S,
183		- le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
184		- HNS_ROCE_SL_SHIFT);
	183	+ ah->av.sl);
185	184	roce_set_field(ud_sq_wqe->u32_36,
186	185	UD_SEND_WQE_U32_36_SGID_INDEX_M,
187	186	UD_SEND_WQE_U32_36_SGID_INDEX_S,
..	..	@@ -195,8 +194,7 @@
195	194	roce_set_field(ud_sq_wqe->u32_40,
196	195	UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
197	196	UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
198		- ah->av.sl_tclass_flowlabel >>
199		- HNS_ROCE_TCLASS_SHIFT);
	197	+ ah->av.tclass);
200	198
201	199	memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
202	200
..	..	@@ -213,7 +211,6 @@
213	211	cpu_to_le32((wr->sg_list[1].addr) >> 32);
214	212	ud_sq_wqe->l_key1 =
215	213	cpu_to_le32(wr->sg_list[1].lkey);
216		- ind++;
217	214	} else if (ibqp->qp_type == IB_QPT_RC) {
218	215	u32 tmp_len = 0;
219	216
..	..	@@ -242,7 +239,7 @@
242	239	break;
243	240	}
244	241
245		- /Ctrl field, ctrl set type: sig, solic, imm, fence /
	242	+ /* Ctrl field, ctrl set type: sig, solic, imm, fence */
246	243	/* SO wait for conforming application scenarios */
247	244	ctrl->flag \|= (wr->send_flags & IB_SEND_SIGNALED ?
248	245	cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) \|
..	..	@@ -303,14 +300,13 @@
303	300	}
304	301	ctrl->flag \|= cpu_to_le32(HNS_ROCE_WQE_INLINE);
305	302	} else {
306		- /sqe num is two /
	303	+ /* sqe num is two */
307	304	for (i = 0; i < wr->num_sge; i++)
308	305	set_data_seg(dseg + i, wr->sg_list + i);
309	306
310	307	ctrl->flag \|= cpu_to_le32(wr->num_sge <<
311	308	HNS_ROCE_WQE_SGE_NUM_BIT);
312	309	}
313		- ind++;
314	310	}
315	311	}
316	312
..	..	@@ -321,8 +317,6 @@
321	317	/* Memory barrier */
322	318	wmb();
323	319
324		- sq_db.u32_4 = 0;
325		- sq_db.u32_8 = 0;
326	320	roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
327	321	SQ_DOORBELL_U32_4_SQ_HEAD_S,
328	322	(qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
..	..	@@ -334,11 +328,10 @@
334	328	SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
335	329	roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
336	330
337		- doorbell[0] = le32_to_cpu(sq_db.u32_4);
338		- doorbell[1] = le32_to_cpu(sq_db.u32_8);
	331	+ doorbell[0] = sq_db.u32_4;
	332	+ doorbell[1] = sq_db.u32_8;
339	333
340		- hns_roce_write64_k((__le32 *)doorbell, qp->sq.db_reg_l);
341		- qp->sq_next_wqe = ind;
	334	+ hns_roce_write64_k(doorbell, qp->sq.db_reg_l);
342	335	}
343	336
344	337	spin_unlock_irqrestore(&qp->sq.lock, flags);
..	..	@@ -350,22 +343,21 @@
350	343	const struct ib_recv_wr *wr,
351	344	const struct ib_recv_wr **bad_wr)
352	345	{
353		- int ret = 0;
354		- int nreq = 0;
355		- int ind = 0;
356		- int i = 0;
357		- u32 reg_val;
358		- unsigned long flags = 0;
359	346	struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
360	347	struct hns_roce_wqe_data_seg *scat = NULL;
361	348	struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
362	349	struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
363	350	struct device *dev = &hr_dev->pdev->dev;
364		- struct hns_roce_rq_db rq_db;
365		- uint32_t doorbell[2] = {0};
	351	+ struct hns_roce_rq_db rq_db = {};
	352	+ __le32 doorbell[2] = {0};
	353	+ unsigned long flags = 0;
	354	+ unsigned int wqe_idx;
	355	+ int ret = 0;
	356	+ int nreq = 0;
	357	+ int i = 0;
	358	+ u32 reg_val;
366	359
367	360	spin_lock_irqsave(&hr_qp->rq.lock, flags);
368		- ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
369	361
370	362	for (nreq = 0; wr; ++nreq, wr = wr->next) {
371	363	if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
..	..	@@ -375,6 +367,8 @@
375	367	goto out;
376	368	}
377	369
	370	+ wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
	371	+
378	372	if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
379	373	dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
380	374	wr->num_sge, hr_qp->rq.max_gs);
..	..	@@ -383,7 +377,7 @@
383	377	goto out;
384	378	}
385	379
386		- ctrl = get_recv_wqe(hr_qp, ind);
	380	+ ctrl = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
387	381
388	382	roce_set_field(ctrl->rwqe_byte_12,
389	383	RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
..	..	@@ -395,9 +389,7 @@
395	389	for (i = 0; i < wr->num_sge; i++)
396	390	set_data_seg(scat + i, wr->sg_list + i);
397	391
398		- hr_qp->rq.wrid[ind] = wr->wr_id;
399		-
400		- ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
	392	+ hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
401	393	}
402	394
403	395	out:
..	..	@@ -423,9 +415,6 @@
423	415	ROCEE_QP1C_CFG3_0_REG +
424	416	QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
425	417	} else {
426		- rq_db.u32_4 = 0;
427		- rq_db.u32_8 = 0;
428		-
429	418	roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
430	419	RQ_DOORBELL_U32_4_RQ_HEAD_S,
431	420	hr_qp->rq.head);
..	..	@@ -436,11 +425,10 @@
436	425	roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
437	426	1);
438	427
439		- doorbell[0] = le32_to_cpu(rq_db.u32_4);
440		- doorbell[1] = le32_to_cpu(rq_db.u32_8);
	428	+ doorbell[0] = rq_db.u32_4;
	429	+ doorbell[1] = rq_db.u32_8;
441	430
442		- hns_roce_write64_k((__le32 *)doorbell,
443		- hr_qp->rq.db_reg_l);
	431	+ hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
444	432	}
445	433	}
446	434	spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
..	..	@@ -460,6 +448,82 @@
460	448	roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
461	449	val = le32_to_cpu(tmp);
462	450	roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
	451	+}
	452	+
	453	+static int hns_roce_v1_set_hem(struct hns_roce_dev *hr_dev,
	454	+ struct hns_roce_hem_table *table, int obj,
	455	+ int step_idx)
	456	+{
	457	+ spinlock_t *lock = &hr_dev->bt_cmd_lock;
	458	+ struct device *dev = hr_dev->dev;
	459	+ struct hns_roce_hem_iter iter;
	460	+ void __iomem *bt_cmd;
	461	+ __le32 bt_cmd_val[2];
	462	+ __le32 bt_cmd_h = 0;
	463	+ unsigned long flags;
	464	+ __le32 bt_cmd_l;
	465	+ int ret = 0;
	466	+ u64 bt_ba;
	467	+ long end;
	468	+
	469	+ /* Find the HEM(Hardware Entry Memory) entry */
	470	+ unsigned long i = (obj & (table->num_obj - 1)) /
	471	+ (table->table_chunk_size / table->obj_size);
	472	+
	473	+ switch (table->type) {
	474	+ case HEM_TYPE_QPC:
	475	+ case HEM_TYPE_MTPT:
	476	+ case HEM_TYPE_CQC:
	477	+ case HEM_TYPE_SRQC:
	478	+ roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
	479	+ ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
	480	+ break;
	481	+ default:
	482	+ return ret;
	483	+ }
	484	+
	485	+ roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
	486	+ ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
	487	+ roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
	488	+ roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
	489	+
	490	+ /* Currently iter only a chunk */
	491	+ for (hns_roce_hem_first(table->hem[i], &iter);
	492	+ !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
	493	+ bt_ba = hns_roce_hem_addr(&iter) >> HNS_HW_PAGE_SHIFT;
	494	+
	495	+ spin_lock_irqsave(lock, flags);
	496	+
	497	+ bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
	498	+
	499	+ end = HW_SYNC_TIMEOUT_MSECS;
	500	+ while (end > 0) {
	501	+ if (!(readl(bt_cmd) >> BT_CMD_SYNC_SHIFT))
	502	+ break;
	503	+
	504	+ mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
	505	+ end -= HW_SYNC_SLEEP_TIME_INTERVAL;
	506	+ }
	507	+
	508	+ if (end <= 0) {
	509	+ dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
	510	+ spin_unlock_irqrestore(lock, flags);
	511	+ return -EBUSY;
	512	+ }
	513	+
	514	+ bt_cmd_l = cpu_to_le32(bt_ba);
	515	+ roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
	516	+ ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S,
	517	+ upper_32_bits(bt_ba));
	518	+
	519	+ bt_cmd_val[0] = bt_cmd_l;
	520	+ bt_cmd_val[1] = bt_cmd_h;
	521	+ hns_roce_write64_k(bt_cmd_val,
	522	+ hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
	523	+ spin_unlock_irqrestore(lock, flags);
	524	+ }
	525	+
	526	+ return ret;
463	527	}
464	528
465	529	static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
..	..	@@ -514,15 +578,12 @@
514	578	static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
515	579	u32 ext_sdb_alful)
516	580	{
	581	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	582	+ struct hns_roce_db_table *db = &priv->db_table;
517	583	struct device *dev = &hr_dev->pdev->dev;
518		- struct hns_roce_v1_priv *priv;
519		- struct hns_roce_db_table *db;
520	584	dma_addr_t sdb_dma_addr;
521	585	__le32 tmp;
522	586	u32 val;
523		-
524		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
525		- db = &priv->db_table;
526	587
527	588	/* Configure extend SDB threshold */
528	589	roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
..	..	@@ -549,22 +610,19 @@
549	610	roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
550	611
551	612	dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
552		- dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",
	613	+ dev_dbg(dev, "ext SDB threshold: empty: 0x%x, ful: 0x%x\n",
553	614	ext_sdb_alept, ext_sdb_alful);
554	615	}
555	616
556	617	static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
557	618	u32 ext_odb_alful)
558	619	{
	620	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	621	+ struct hns_roce_db_table *db = &priv->db_table;
559	622	struct device *dev = &hr_dev->pdev->dev;
560		- struct hns_roce_v1_priv *priv;
561		- struct hns_roce_db_table *db;
562	623	dma_addr_t odb_dma_addr;
563	624	__le32 tmp;
564	625	u32 val;
565		-
566		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
567		- db = &priv->db_table;
568	626
569	627	/* Configure extend ODB threshold */
570	628	roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
..	..	@@ -594,15 +652,12 @@
594	652	static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
595	653	u32 odb_ext_mod)
596	654	{
	655	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	656	+ struct hns_roce_db_table *db = &priv->db_table;
597	657	struct device *dev = &hr_dev->pdev->dev;
598		- struct hns_roce_v1_priv *priv;
599		- struct hns_roce_db_table *db;
600	658	dma_addr_t sdb_dma_addr;
601	659	dma_addr_t odb_dma_addr;
602	660	int ret = 0;
603		-
604		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
605		- db = &priv->db_table;
606	661
607	662	db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
608	663	if (!db->ext_db)
..	..	@@ -703,35 +758,38 @@
703	758
704	759	static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
705	760	{
	761	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	762	+ struct hns_roce_free_mr *free_mr = &priv->free_mr;
706	763	struct hns_roce_caps *caps = &hr_dev->caps;
	764	+ struct ib_device *ibdev = &hr_dev->ib_dev;
707	765	struct device *dev = &hr_dev->pdev->dev;
708	766	struct ib_cq_init_attr cq_init_attr;
709		- struct hns_roce_free_mr *free_mr;
710	767	struct ib_qp_attr attr = { 0 };
711		- struct hns_roce_v1_priv *priv;
712	768	struct hns_roce_qp *hr_qp;
713	769	struct ib_cq *cq;
714	770	struct ib_pd *pd;
715	771	union ib_gid dgid;
716		- u64 subnet_prefix;
	772	+ __be64 subnet_prefix;
717	773	int attr_mask = 0;
718		- int i, j;
719	774	int ret;
	775	+ int i, j;
720	776	u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
721	777	u8 phy_port;
722	778	u8 port = 0;
723	779	u8 sl;
724	780
725		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
726		- free_mr = &priv->free_mr;
727		-
728	781	/* Reserved cq for loop qp */
729	782	cq_init_attr.cqe = HNS_ROCE_MIN_WQE_NUM * 2;
730	783	cq_init_attr.comp_vector = 0;
731		- cq = hns_roce_ib_create_cq(&hr_dev->ib_dev, &cq_init_attr, NULL, NULL);
732		- if (IS_ERR(cq)) {
733		- dev_err(dev, "Create cq for reseved loop qp failed!");
	784	+
	785	+ cq = rdma_zalloc_drv_obj(ibdev, ib_cq);
	786	+ if (!cq)
734	787	return -ENOMEM;
	788	+
	789	+ ret = hns_roce_create_cq(cq, &cq_init_attr, NULL);
	790	+ if (ret) {
	791	+ dev_err(dev, "Create cq for reserved loop qp failed!");
	792	+ goto alloc_cq_failed;
735	793	}
736	794	free_mr->mr_free_cq = to_hr_cq(cq);
737	795	free_mr->mr_free_cq->ib_cq.device = &hr_dev->ib_dev;
..	..	@@ -741,12 +799,17 @@
741	799	free_mr->mr_free_cq->ib_cq.cq_context = NULL;
742	800	atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
743	801
744		- pd = hns_roce_alloc_pd(&hr_dev->ib_dev, NULL, NULL);
745		- if (IS_ERR(pd)) {
746		- dev_err(dev, "Create pd for reseved loop qp failed!");
	802	+ pd = rdma_zalloc_drv_obj(ibdev, ib_pd);
	803	+ if (!pd) {
747	804	ret = -ENOMEM;
748		- goto alloc_pd_failed;
	805	+ goto alloc_mem_failed;
749	806	}
	807	+
	808	+ pd->device = ibdev;
	809	+ ret = hns_roce_alloc_pd(pd, NULL);
	810	+ if (ret)
	811	+ goto alloc_pd_failed;
	812	+
750	813	free_mr->mr_free_pd = to_hr_pd(pd);
751	814	free_mr->mr_free_pd->ibpd.device = &hr_dev->ib_dev;
752	815	free_mr->mr_free_pd->ibpd.uobject = NULL;
..	..	@@ -812,7 +875,7 @@
812	875	attr.dest_qp_num = hr_qp->qpn;
813	876	memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
814	877	hr_dev->dev_addr[port],
815		- MAC_ADDR_OCTET_NUM);
	878	+ ETH_ALEN);
816	879
817	880	memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
818	881	memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
..	..	@@ -849,65 +912,58 @@
849	912	create_lp_qp_failed:
850	913	for (i -= 1; i >= 0; i--) {
851	914	hr_qp = free_mr->mr_free_qp[i];
852		- if (hns_roce_v1_destroy_qp(&hr_qp->ibqp))
	915	+ if (hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL))
853	916	dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
854	917	}
855	918
856		- if (hns_roce_dealloc_pd(pd))
857		- dev_err(dev, "Destroy pd for create_lp_qp failed!\n");
	919	+ hns_roce_dealloc_pd(pd, NULL);
858	920
859	921	alloc_pd_failed:
860		- if (hns_roce_ib_destroy_cq(cq))
861		- dev_err(dev, "Destroy cq for create_lp_qp failed!\n");
	922	+ kfree(pd);
862	923
	924	+alloc_mem_failed:
	925	+ hns_roce_destroy_cq(cq, NULL);
	926	+alloc_cq_failed:
	927	+ kfree(cq);
863	928	return ret;
864	929	}
865	930
866	931	static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
867	932	{
	933	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	934	+ struct hns_roce_free_mr *free_mr = &priv->free_mr;
868	935	struct device *dev = &hr_dev->pdev->dev;
869		- struct hns_roce_free_mr *free_mr;
870		- struct hns_roce_v1_priv *priv;
871	936	struct hns_roce_qp *hr_qp;
872	937	int ret;
873	938	int i;
874		-
875		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
876		- free_mr = &priv->free_mr;
877	939
878	940	for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
879	941	hr_qp = free_mr->mr_free_qp[i];
880	942	if (!hr_qp)
881	943	continue;
882	944
883		- ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp);
	945	+ ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL);
884	946	if (ret)
885	947	dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
886	948	i, ret);
887	949	}
888	950
889		- ret = hns_roce_ib_destroy_cq(&free_mr->mr_free_cq->ib_cq);
890		- if (ret)
891		- dev_err(dev, "Destroy cq for mr_free failed(%d)!\n", ret);
892		-
893		- ret = hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd);
894		- if (ret)
895		- dev_err(dev, "Destroy pd for mr_free failed(%d)!\n", ret);
	951	+ hns_roce_destroy_cq(&free_mr->mr_free_cq->ib_cq, NULL);
	952	+ kfree(&free_mr->mr_free_cq->ib_cq);
	953	+ hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd, NULL);
	954	+ kfree(&free_mr->mr_free_pd->ibpd);
896	955	}
897	956
898	957	static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
899	958	{
	959	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	960	+ struct hns_roce_db_table *db = &priv->db_table;
900	961	struct device *dev = &hr_dev->pdev->dev;
901		- struct hns_roce_v1_priv *priv;
902		- struct hns_roce_db_table *db;
903	962	u32 sdb_ext_mod;
904	963	u32 odb_ext_mod;
905	964	u32 sdb_evt_mod;
906	965	u32 odb_evt_mod;
907		- int ret = 0;
908		-
909		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
910		- db = &priv->db_table;
	966	+ int ret;
911	967
912	968	memset(db, 0, sizeof(*db));
913	969
..	..	@@ -954,16 +1010,12 @@
954	1010
955	1011	static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
956	1012	{
957		- struct device *dev = &hr_dev->pdev->dev;
	1013	+ long end = HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS;
	1014	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1015	+ struct hns_roce_free_mr *free_mr = &priv->free_mr;
958	1016	struct hns_roce_recreate_lp_qp_work *lp_qp_work;
959		- struct hns_roce_free_mr *free_mr;
960		- struct hns_roce_v1_priv *priv;
	1017	+ struct device *dev = &hr_dev->pdev->dev;
961	1018	struct completion comp;
962		- unsigned long end =
963		- msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies;
964		-
965		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
966		- free_mr = &priv->free_mr;
967	1019
968	1020	lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
969	1021	GFP_KERNEL);
..	..	@@ -980,10 +1032,11 @@
980	1032
981	1033	queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
982	1034
983		- while (time_before_eq(jiffies, end)) {
	1035	+ while (end > 0) {
984	1036	if (try_wait_for_completion(&comp))
985	1037	return 0;
986	1038	msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
	1039	+ end -= HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE;
987	1040	}
988	1041
989	1042	lp_qp_work->comp_flag = 0;
..	..	@@ -1021,29 +1074,21 @@
1021	1074
1022	1075	static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1023	1076	{
1024		- struct hns_roce_mr_free_work *mr_work;
1025		- struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
1026		- struct hns_roce_free_mr *free_mr;
1027		- struct hns_roce_cq *mr_free_cq;
1028		- struct hns_roce_v1_priv *priv;
1029		- struct hns_roce_dev *hr_dev;
1030		- struct hns_roce_mr *hr_mr;
1031		- struct hns_roce_qp *hr_qp;
1032		- struct device *dev;
1033	1077	unsigned long end =
1034	1078	msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1035		- int i;
1036		- int ret;
	1079	+ struct hns_roce_mr_free_work *mr_work =
	1080	+ container_of(work, struct hns_roce_mr_free_work, work);
	1081	+ struct hns_roce_dev *hr_dev = to_hr_dev(mr_work->ib_dev);
	1082	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1083	+ struct hns_roce_free_mr *free_mr = &priv->free_mr;
	1084	+ struct hns_roce_cq *mr_free_cq = free_mr->mr_free_cq;
	1085	+ struct hns_roce_mr *hr_mr = mr_work->mr;
	1086	+ struct device *dev = &hr_dev->pdev->dev;
	1087	+ struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
	1088	+ struct hns_roce_qp *hr_qp;
1037	1089	int ne = 0;
1038		-
1039		- mr_work = container_of(work, struct hns_roce_mr_free_work, work);
1040		- hr_mr = (struct hns_roce_mr *)mr_work->mr;
1041		- hr_dev = to_hr_dev(mr_work->ib_dev);
1042		- dev = &hr_dev->pdev->dev;
1043		-
1044		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1045		- free_mr = &priv->free_mr;
1046		- mr_free_cq = free_mr->mr_free_cq;
	1090	+ int ret;
	1091	+ int i;
1047	1092
1048	1093	for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
1049	1094	hr_qp = free_mr->mr_free_qp[i];
..	..	@@ -1090,26 +1135,22 @@
1090	1135	}
1091	1136
1092	1137	static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1093		- struct hns_roce_mr *mr)
	1138	+ struct hns_roce_mr mr, struct ib_udata udata)
1094	1139	{
	1140	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1141	+ struct hns_roce_free_mr *free_mr = &priv->free_mr;
	1142	+ long end = HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS;
1095	1143	struct device *dev = &hr_dev->pdev->dev;
1096	1144	struct hns_roce_mr_free_work *mr_work;
1097		- struct hns_roce_free_mr *free_mr;
1098		- struct hns_roce_v1_priv *priv;
1099		- struct completion comp;
1100		- unsigned long end =
1101		- msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1102	1145	unsigned long start = jiffies;
1103		- int npages;
	1146	+ struct completion comp;
1104	1147	int ret = 0;
1105	1148
1106		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1107		- free_mr = &priv->free_mr;
1108		-
1109	1149	if (mr->enabled) {
1110		- if (hns_roce_hw2sw_mpt(hr_dev, NULL, key_to_hw_index(mr->key)
1111		- & (hr_dev->caps.num_mtpts - 1)))
1112		- dev_warn(dev, "HW2SW_MPT failed!\n");
	1150	+ if (hns_roce_hw_destroy_mpt(hr_dev, NULL,
	1151	+ key_to_hw_index(mr->key) &
	1152	+ (hr_dev->caps.num_mtpts - 1)))
	1153	+ dev_warn(dev, "DESTROY_MPT failed!\n");
1113	1154	}
1114	1155
1115	1156	mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
..	..	@@ -1128,10 +1169,11 @@
1128	1169
1129	1170	queue_work(free_mr->free_mr_wq, &(mr_work->work));
1130	1171
1131		- while (time_before_eq(jiffies, end)) {
	1172	+ while (end > 0) {
1132	1173	if (try_wait_for_completion(&comp))
1133	1174	goto free_mr;
1134	1175	msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
	1176	+ end -= HNS_ROCE_V1_FREE_MR_WAIT_VALUE;
1135	1177	}
1136	1178
1137	1179	mr_work->comp_flag = 0;
..	..	@@ -1145,18 +1187,9 @@
1145	1187	dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1146	1188	mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1147	1189
1148		- if (mr->size != ~0ULL) {
1149		- npages = ib_umem_page_count(mr->umem);
1150		- dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1151		- mr->pbl_dma_addr);
1152		- }
1153		-
1154	1190	hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1155	1191	key_to_hw_index(mr->key), 0);
1156		-
1157		- if (mr->umem)
1158		- ib_umem_release(mr->umem);
1159		-
	1192	+ hns_roce_mtr_destroy(hr_dev, &mr->pbl_mtr);
1160	1193	kfree(mr);
1161	1194
1162	1195	return ret;
..	..	@@ -1164,12 +1197,9 @@
1164	1197
1165	1198	static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1166	1199	{
	1200	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1201	+ struct hns_roce_db_table *db = &priv->db_table;
1167	1202	struct device *dev = &hr_dev->pdev->dev;
1168		- struct hns_roce_v1_priv *priv;
1169		- struct hns_roce_db_table *db;
1170		-
1171		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1172		- db = &priv->db_table;
1173	1203
1174	1204	if (db->sdb_ext_mod) {
1175	1205	dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
..	..	@@ -1190,17 +1220,14 @@
1190	1220
1191	1221	static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1192	1222	{
1193		- int ret;
1194		- u32 val;
1195		- __le32 tmp;
1196		- int raq_shift = 0;
1197		- dma_addr_t addr;
1198		- struct hns_roce_v1_priv *priv;
1199		- struct hns_roce_raq_table *raq;
	1223	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1224	+ struct hns_roce_raq_table *raq = &priv->raq_table;
1200	1225	struct device *dev = &hr_dev->pdev->dev;
1201		-
1202		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1203		- raq = &priv->raq_table;
	1226	+ dma_addr_t addr;
	1227	+ int raq_shift;
	1228	+ __le32 tmp;
	1229	+ u32 val;
	1230	+ int ret;
1204	1231
1205	1232	raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1206	1233	if (!raq->e_raq_buf)
..	..	@@ -1214,7 +1241,7 @@
1214	1241	}
1215	1242	raq->e_raq_buf->map = addr;
1216	1243
1217		- /* Configure raq extended address. 48bit 4K align*/
	1244	+ /* Configure raq extended address. 48bit 4K align */
1218	1245	roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1219	1246
1220	1247	/* Configure raq_shift */
..	..	@@ -1280,12 +1307,9 @@
1280	1307
1281	1308	static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1282	1309	{
	1310	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1311	+ struct hns_roce_raq_table *raq = &priv->raq_table;
1283	1312	struct device *dev = &hr_dev->pdev->dev;
1284		- struct hns_roce_v1_priv *priv;
1285		- struct hns_roce_raq_table *raq;
1286		-
1287		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1288		- raq = &priv->raq_table;
1289	1313
1290	1314	dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1291	1315	raq->e_raq_buf->map);
..	..	@@ -1319,11 +1343,9 @@
1319	1343
1320	1344	static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1321	1345	{
	1346	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
1322	1347	struct device *dev = &hr_dev->pdev->dev;
1323		- struct hns_roce_v1_priv *priv;
1324	1348	int ret;
1325		-
1326		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1327	1349
1328	1350	priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1329	1351	HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
..	..	@@ -1362,10 +1384,8 @@
1362	1384
1363	1385	static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1364	1386	{
	1387	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
1365	1388	struct device *dev = &hr_dev->pdev->dev;
1366		- struct hns_roce_v1_priv *priv;
1367		-
1368		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1369	1389
1370	1390	dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1371	1391	priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
..	..	@@ -1379,12 +1399,9 @@
1379	1399
1380	1400	static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1381	1401	{
	1402	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1403	+ struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1382	1404	struct device *dev = &hr_dev->pdev->dev;
1383		- struct hns_roce_buf_list *tptr_buf;
1384		- struct hns_roce_v1_priv *priv;
1385		-
1386		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1387		- tptr_buf = &priv->tptr_table.tptr_buf;
1388	1405
1389	1406	/*
1390	1407	* This buffer will be used for CQ's tptr(tail pointer), also
..	..	@@ -1405,12 +1422,9 @@
1405	1422
1406	1423	static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1407	1424	{
	1425	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1426	+ struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1408	1427	struct device *dev = &hr_dev->pdev->dev;
1409		- struct hns_roce_buf_list *tptr_buf;
1410		- struct hns_roce_v1_priv *priv;
1411		-
1412		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1413		- tptr_buf = &priv->tptr_table.tptr_buf;
1414	1428
1415	1429	dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1416	1430	tptr_buf->buf, tptr_buf->map);
..	..	@@ -1418,13 +1432,10 @@
1418	1432
1419	1433	static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1420	1434	{
	1435	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1436	+ struct hns_roce_free_mr *free_mr = &priv->free_mr;
1421	1437	struct device *dev = &hr_dev->pdev->dev;
1422		- struct hns_roce_free_mr *free_mr;
1423		- struct hns_roce_v1_priv *priv;
1424		- int ret = 0;
1425		-
1426		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1427		- free_mr = &priv->free_mr;
	1438	+ int ret;
1428	1439
1429	1440	free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1430	1441	if (!free_mr->free_mr_wq) {
..	..	@@ -1444,11 +1455,8 @@
1444	1455
1445	1456	static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1446	1457	{
1447		- struct hns_roce_free_mr *free_mr;
1448		- struct hns_roce_v1_priv *priv;
1449		-
1450		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1451		- free_mr = &priv->free_mr;
	1458	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1459	+ struct hns_roce_free_mr *free_mr = &priv->free_mr;
1452	1460
1453	1461	flush_workqueue(free_mr->free_mr_wq);
1454	1462	destroy_workqueue(free_mr->free_mr_wq);
..	..	@@ -1505,42 +1513,10 @@
1505	1513	return ret;
1506	1514	}
1507	1515
1508		-static int hns_roce_des_qp_init(struct hns_roce_dev *hr_dev)
1509		-{
1510		- struct device *dev = &hr_dev->pdev->dev;
1511		- struct hns_roce_v1_priv *priv;
1512		- struct hns_roce_des_qp *des_qp;
1513		-
1514		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1515		- des_qp = &priv->des_qp;
1516		-
1517		- des_qp->requeue_flag = 1;
1518		- des_qp->qp_wq = create_singlethread_workqueue("hns_roce_destroy_qp");
1519		- if (!des_qp->qp_wq) {
1520		- dev_err(dev, "Create destroy qp workqueue failed!\n");
1521		- return -ENOMEM;
1522		- }
1523		-
1524		- return 0;
1525		-}
1526		-
1527		-static void hns_roce_des_qp_free(struct hns_roce_dev *hr_dev)
1528		-{
1529		- struct hns_roce_v1_priv *priv;
1530		- struct hns_roce_des_qp *des_qp;
1531		-
1532		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1533		- des_qp = &priv->des_qp;
1534		-
1535		- des_qp->requeue_flag = 0;
1536		- flush_workqueue(des_qp->qp_wq);
1537		- destroy_workqueue(des_qp->qp_wq);
1538		-}
1539		-
1540	1516	static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1541	1517	{
1542		- int i = 0;
1543	1518	struct hns_roce_caps *caps = &hr_dev->caps;
	1519	+ int i;
1544	1520
1545	1521	hr_dev->vendor_id = roce_read(hr_dev, ROCEE_VENDOR_ID_REG);
1546	1522	hr_dev->vendor_part_id = roce_read(hr_dev, ROCEE_VENDOR_PART_ID_REG);
..	..	@@ -1570,18 +1546,19 @@
1570	1546	caps->max_qp_dest_rdma = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1571	1547	caps->max_sq_desc_sz = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1572	1548	caps->max_rq_desc_sz = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1573		- caps->qpc_entry_sz = HNS_ROCE_V1_QPC_ENTRY_SIZE;
	1549	+ caps->qpc_sz = HNS_ROCE_V1_QPC_SIZE;
1574	1550	caps->irrl_entry_sz = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1575	1551	caps->cqc_entry_sz = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1576	1552	caps->mtpt_entry_sz = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1577	1553	caps->mtt_entry_sz = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1578		- caps->cq_entry_sz = HNS_ROCE_V1_CQE_ENTRY_SIZE;
	1554	+ caps->cqe_sz = HNS_ROCE_V1_CQE_SIZE;
1579	1555	caps->page_size_cap = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1580	1556	caps->reserved_lkey = 0;
1581	1557	caps->reserved_pds = 0;
1582	1558	caps->reserved_mrws = 1;
1583	1559	caps->reserved_uars = 0;
1584	1560	caps->reserved_cqs = 0;
	1561	+ caps->reserved_qps = 12; /* 2 SQP per port, six ports total 12 */
1585	1562	caps->chunk_sz = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
1586	1563
1587	1564	for (i = 0; i < caps->num_ports; i++)
..	..	@@ -1655,12 +1632,6 @@
1655	1632	goto error_failed_tptr_init;
1656	1633	}
1657	1634
1658		- ret = hns_roce_des_qp_init(hr_dev);
1659		- if (ret) {
1660		- dev_err(dev, "des qp init failed!\n");
1661		- goto error_failed_des_qp_init;
1662		- }
1663		-
1664	1635	ret = hns_roce_free_mr_init(hr_dev);
1665	1636	if (ret) {
1666	1637	dev_err(dev, "free mr init failed!\n");
..	..	@@ -1672,9 +1643,6 @@
1672	1643	return 0;
1673	1644
1674	1645	error_failed_free_mr_init:
1675		- hns_roce_des_qp_free(hr_dev);
1676		-
1677		-error_failed_des_qp_init:
1678	1646	hns_roce_tptr_free(hr_dev);
1679	1647
1680	1648	error_failed_tptr_init:
..	..	@@ -1692,7 +1660,6 @@
1692	1660	{
1693	1661	hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1694	1662	hns_roce_free_mr_free(hr_dev);
1695		- hns_roce_des_qp_free(hr_dev);
1696	1663	hns_roce_tptr_free(hr_dev);
1697	1664	hns_roce_bt_free(hr_dev);
1698	1665	hns_roce_raq_free(hr_dev);
..	..	@@ -1744,8 +1711,6 @@
1744	1711
1745	1712	writel(val, hcr + 5);
1746	1713
1747		- mmiowb();
1748		-
1749	1714	return 0;
1750	1715	}
1751	1716
..	..	@@ -1753,7 +1718,7 @@
1753	1718	unsigned long timeout)
1754	1719	{
1755	1720	u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1756		- unsigned long end = 0;
	1721	+ unsigned long end;
1757	1722	u32 status = 0;
1758	1723
1759	1724	end = msecs_to_jiffies(timeout) + jiffies;
..	..	@@ -1779,10 +1744,13 @@
1779	1744	int gid_index, const union ib_gid *gid,
1780	1745	const struct ib_gid_attr *attr)
1781	1746	{
	1747	+ unsigned long flags;
1782	1748	u32 *p = NULL;
1783		- u8 gid_idx = 0;
	1749	+ u8 gid_idx;
1784	1750
1785	1751	gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
	1752	+
	1753	+ spin_lock_irqsave(&hr_dev->iboe.lock, flags);
1786	1754
1787	1755	p = (u32 *)&gid->raw[0];
1788	1756	roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
..	..	@@ -1799,6 +1767,8 @@
1799	1767	p = (u32 *)&gid->raw[0xc];
1800	1768	roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1801	1769	(HNS_ROCE_V1_GID_NUM * gid_idx));
	1770	+
	1771	+ spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
1802	1772
1803	1773	return 0;
1804	1774	}
..	..	@@ -1861,13 +1831,15 @@
1861	1831	val);
1862	1832	}
1863	1833
1864		-static int hns_roce_v1_write_mtpt(void mb_buf, struct hns_roce_mr mr,
	1834	+static int hns_roce_v1_write_mtpt(struct hns_roce_dev hr_dev, void mb_buf,
	1835	+ struct hns_roce_mr *mr,
1865	1836	unsigned long mtpt_idx)
1866	1837	{
	1838	+ u64 pages[HNS_ROCE_MAX_INNER_MTPT_NUM] = { 0 };
	1839	+ struct ib_device *ibdev = &hr_dev->ib_dev;
1867	1840	struct hns_roce_v1_mpt_entry *mpt_entry;
1868		- struct scatterlist *sg;
1869		- u64 *pages;
1870		- int entry;
	1841	+ dma_addr_t pbl_ba;
	1842	+ int count;
1871	1843	int i;
1872	1844
1873	1845	/* MPT filled into mailbox buf */
..	..	@@ -1917,22 +1889,15 @@
1917	1889	if (mr->type == MR_TYPE_DMA)
1918	1890	return 0;
1919	1891
1920		- pages = (u64 *) __get_free_page(GFP_KERNEL);
1921		- if (!pages)
1922		- return -ENOMEM;
1923		-
1924		- i = 0;
1925		- for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
1926		- pages[i] = ((u64)sg_dma_address(sg)) >> 12;
1927		-
1928		- /* Directly record to MTPT table firstly 7 entry */
1929		- if (i >= HNS_ROCE_MAX_INNER_MTPT_NUM)
1930		- break;
1931		- i++;
	1892	+ count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
	1893	+ ARRAY_SIZE(pages), &pbl_ba);
	1894	+ if (count < 1) {
	1895	+ ibdev_err(ibdev, "failed to find PBL mtr, count = %d.", count);
	1896	+ return -ENOBUFS;
1932	1897	}
1933	1898
1934	1899	/* Register user mr */
1935		- for (i = 0; i < HNS_ROCE_MAX_INNER_MTPT_NUM; i++) {
	1900	+ for (i = 0; i < count; i++) {
1936	1901	switch (i) {
1937	1902	case 0:
1938	1903	mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
..	..	@@ -1998,21 +1963,16 @@
1998	1963	}
1999	1964	}
2000	1965
2001		- free_page((unsigned long) pages);
2002		-
2003		- mpt_entry->pbl_addr_l = cpu_to_le32((u32)(mr->pbl_dma_addr));
2004		-
	1966	+ mpt_entry->pbl_addr_l = cpu_to_le32(pbl_ba);
2005	1967	roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
2006		- MPT_BYTE_12_PBL_ADDR_H_S,
2007		- ((u32)(mr->pbl_dma_addr >> 32)));
	1968	+ MPT_BYTE_12_PBL_ADDR_H_S, upper_32_bits(pbl_ba));
2008	1969
2009	1970	return 0;
2010	1971	}
2011	1972
2012	1973	static void get_cqe(struct hns_roce_cq hr_cq, int n)
2013	1974	{
2014		- return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
2015		- n * HNS_ROCE_V1_CQE_ENTRY_SIZE);
	1975	+ return hns_roce_buf_offset(hr_cq->mtr.kmem, n * HNS_ROCE_V1_CQE_SIZE);
2016	1976	}
2017	1977
2018	1978	static void get_sw_cqe(struct hns_roce_cq hr_cq, int n)
..	..	@@ -2021,7 +1981,7 @@
2021	1981
2022	1982	/* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
2023	1983	return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
2024		- !!(n & (hr_cq->ib_cq.cqe + 1))) ? hr_cqe : NULL;
	1984	+ !!(n & hr_cq->cq_depth)) ? hr_cqe : NULL;
2025	1985	}
2026	1986
2027	1987	static struct hns_roce_cqe next_cqe_sw(struct hns_roce_cq hr_cq)
..	..	@@ -2104,19 +2064,14 @@
2104	2064
2105	2065	static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
2106	2066	struct hns_roce_cq hr_cq, void mb_buf,
2107		- u64 *mtts, dma_addr_t dma_handle, int nent,
2108		- u32 vector)
	2067	+ u64 *mtts, dma_addr_t dma_handle)
2109	2068	{
2110		- struct hns_roce_cq_context *cq_context = NULL;
2111		- struct hns_roce_buf_list *tptr_buf;
2112		- struct hns_roce_v1_priv *priv;
	2069	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	2070	+ struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
	2071	+ struct hns_roce_cq_context *cq_context = mb_buf;
2113	2072	dma_addr_t tptr_dma_addr;
2114	2073	int offset;
2115	2074
2116		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2117		- tptr_buf = &priv->tptr_table.tptr_buf;
2118		-
2119		- cq_context = mb_buf;
2120	2075	memset(cq_context, 0, sizeof(*cq_context));
2121	2076
2122	2077	/* Get the tptr for this CQ. */
..	..	@@ -2140,9 +2095,9 @@
2140	2095	roce_set_field(cq_context->cqc_byte_12,
2141	2096	CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2142	2097	CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2143		- ilog2((unsigned int)nent));
	2098	+ ilog2(hr_cq->cq_depth));
2144	2099	roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2145		- CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector);
	2100	+ CQ_CONTEXT_CQC_BYTE_12_CEQN_S, hr_cq->vector);
2146	2101
2147	2102	cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0]));
2148	2103
..	..	@@ -2183,17 +2138,12 @@
2183	2138	CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2184	2139	}
2185	2140
2186		-static int hns_roce_v1_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
2187		-{
2188		- return -EOPNOTSUPP;
2189		-}
2190		-
2191	2141	static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
2192	2142	enum ib_cq_notify_flags flags)
2193	2143	{
2194	2144	struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2195	2145	u32 notification_flag;
2196		- __le32 doorbell[2];
	2146	+ __le32 doorbell[2] = {};
2197	2147
2198	2148	notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2199	2149	IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
..	..	@@ -2325,9 +2275,10 @@
2325	2275
2326	2276	if (is_send) {
2327	2277	/* SQ conrespond to CQE */
2328		- sq_wqe = get_send_wqe(*cur_qp, roce_get_field(cqe->cqe_byte_4,
	2278	+ sq_wqe = hns_roce_get_send_wqe(*cur_qp,
	2279	+ roce_get_field(cqe->cqe_byte_4,
2329	2280	CQE_BYTE_4_WQE_INDEX_M,
2330		- CQE_BYTE_4_WQE_INDEX_S)&
	2281	+ CQE_BYTE_4_WQE_INDEX_S) &
2331	2282	((*cur_qp)->sq.wqe_cnt-1));
2332	2283	switch (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_OPCODE_MASK) {
2333	2284	case HNS_ROCE_WQE_OPCODE_SEND:
..	..	@@ -2456,29 +2407,22 @@
2456	2407	struct hns_roce_hem_table *table, int obj,
2457	2408	int step_idx)
2458	2409	{
	2410	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
2459	2411	struct device *dev = &hr_dev->pdev->dev;
2460		- struct hns_roce_v1_priv *priv;
2461		- unsigned long end = 0, flags = 0;
	2412	+ long end = HW_SYNC_TIMEOUT_MSECS;
2462	2413	__le32 bt_cmd_val[2] = {0};
	2414	+ unsigned long flags = 0;
2463	2415	void __iomem *bt_cmd;
2464	2416	u64 bt_ba = 0;
2465	2417
2466		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2467		-
2468	2418	switch (table->type) {
2469	2419	case HEM_TYPE_QPC:
2470		- roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2471		- ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
2472	2420	bt_ba = priv->bt_table.qpc_buf.map >> 12;
2473	2421	break;
2474	2422	case HEM_TYPE_MTPT:
2475		- roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2476		- ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_MTPT);
2477	2423	bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2478	2424	break;
2479	2425	case HEM_TYPE_CQC:
2480		- roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2481		- ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
2482	2426	bt_ba = priv->bt_table.cqc_buf.map >> 12;
2483	2427	break;
2484	2428	case HEM_TYPE_SRQC:
..	..	@@ -2487,6 +2431,8 @@
2487	2431	default:
2488	2432	return 0;
2489	2433	}
	2434	+ roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
	2435	+ ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
2490	2436	roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2491	2437	ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2492	2438	roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
..	..	@@ -2496,10 +2442,9 @@
2496	2442
2497	2443	bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2498	2444
2499		- end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
2500	2445	while (1) {
2501	2446	if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2502		- if (!(time_before(jiffies, end))) {
	2447	+ if (!end) {
2503	2448	dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2504	2449	spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2505	2450	flags);
..	..	@@ -2508,10 +2453,11 @@
2508	2453	} else {
2509	2454	break;
2510	2455	}
2511		- msleep(HW_SYNC_SLEEP_TIME_INTERVAL);
	2456	+ mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
	2457	+ end -= HW_SYNC_SLEEP_TIME_INTERVAL;
2512	2458	}
2513	2459
2514		- bt_cmd_val[0] = (__le32)bt_ba;
	2460	+ bt_cmd_val[0] = cpu_to_le32(bt_ba);
2515	2461	roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2516	2462	ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2517	2463	hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
..	..	@@ -2522,7 +2468,6 @@
2522	2468	}
2523	2469
2524	2470	static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2525		- struct hns_roce_mtt *mtt,
2526	2471	enum hns_roce_qp_state cur_state,
2527	2472	enum hns_roce_qp_state new_state,
2528	2473	struct hns_roce_qp_context *context,
..	..	@@ -2569,7 +2514,7 @@
2569	2514
2570	2515	struct hns_roce_cmd_mailbox *mailbox;
2571	2516	struct device *dev = &hr_dev->pdev->dev;
2572		- int ret = 0;
	2517	+ int ret;
2573	2518
2574	2519	if (cur_state >= HNS_ROCE_QP_NUM_STATE \|\|
2575	2520	new_state >= HNS_ROCE_QP_NUM_STATE \|\|
..	..	@@ -2603,6 +2548,28 @@
2603	2548	return ret;
2604	2549	}
2605	2550
	2551	+static int find_wqe_mtt(struct hns_roce_dev hr_dev, struct hns_roce_qp hr_qp,
	2552	+ u64 sq_ba, u64 rq_ba, dma_addr_t *bt_ba)
	2553	+{
	2554	+ struct ib_device *ibdev = &hr_dev->ib_dev;
	2555	+ int count;
	2556	+
	2557	+ count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, sq_ba, 1, bt_ba);
	2558	+ if (count < 1) {
	2559	+ ibdev_err(ibdev, "Failed to find SQ ba\n");
	2560	+ return -ENOBUFS;
	2561	+ }
	2562	+
	2563	+ count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, rq_ba,
	2564	+ 1, NULL);
	2565	+ if (!count) {
	2566	+ ibdev_err(ibdev, "Failed to find RQ ba\n");
	2567	+ return -ENOBUFS;
	2568	+ }
	2569	+
	2570	+ return 0;
	2571	+}
	2572	+
2606	2573	static int hns_roce_v1_m_sqp(struct ib_qp ibqp, const struct ib_qp_attr attr,
2607	2574	int attr_mask, enum ib_qp_state cur_state,
2608	2575	enum ib_qp_state new_state)
..	..	@@ -2610,25 +2577,20 @@
2610	2577	struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2611	2578	struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2612	2579	struct hns_roce_sqp_context *context;
2613		- struct device *dev = &hr_dev->pdev->dev;
2614	2580	dma_addr_t dma_handle = 0;
2615	2581	u32 __iomem *addr;
2616		- int rq_pa_start;
	2582	+ u64 sq_ba = 0;
	2583	+ u64 rq_ba = 0;
2617	2584	__le32 tmp;
2618	2585	u32 reg_val;
2619		- u64 *mtts;
2620	2586
2621	2587	context = kzalloc(sizeof(*context), GFP_KERNEL);
2622	2588	if (!context)
2623	2589	return -ENOMEM;
2624	2590
2625	2591	/* Search QP buf's MTTs */
2626		- mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2627		- hr_qp->mtt.first_seg, &dma_handle);
2628		- if (!mtts) {
2629		- dev_err(dev, "qp buf pa find failed\n");
	2592	+ if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2630	2593	goto out;
2631		- }
2632	2594
2633	2595	if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2634	2596	roce_set_field(context->qp1c_bytes_4,
..	..	@@ -2642,11 +2604,11 @@
2642	2604	roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2643	2605	QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2644	2606
2645		- context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
	2607	+ context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2646	2608	roce_set_field(context->qp1c_bytes_12,
2647	2609	QP1C_BYTES_12_SQ_RQ_BT_H_M,
2648	2610	QP1C_BYTES_12_SQ_RQ_BT_H_S,
2649		- ((u32)(dma_handle >> 32)));
	2611	+ upper_32_bits(dma_handle));
2650	2612
2651	2613	roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2652	2614	QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
..	..	@@ -2654,7 +2616,7 @@
2654	2616	QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2655	2617	roce_set_bit(context->qp1c_bytes_16,
2656	2618	QP1C_BYTES_16_SIGNALING_TYPE_S,
2657		- le32_to_cpu(hr_qp->sq_signal_bits));
	2619	+ hr_qp->sq_signal_bits);
2658	2620	roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2659	2621	1);
2660	2622	roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
..	..	@@ -2667,14 +2629,12 @@
2667	2629	roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2668	2630	QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2669	2631
2670		- rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2671		- context->cur_rq_wqe_ba_l =
2672		- cpu_to_le32((u32)(mtts[rq_pa_start]));
	2632	+ context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
2673	2633
2674	2634	roce_set_field(context->qp1c_bytes_28,
2675	2635	QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2676	2636	QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2677		- (mtts[rq_pa_start]) >> 32);
	2637	+ upper_32_bits(rq_ba));
2678	2638	roce_set_field(context->qp1c_bytes_28,
2679	2639	QP1C_BYTES_28_RQ_CUR_IDX_M,
2680	2640	QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
..	..	@@ -2688,12 +2648,12 @@
2688	2648	QP1C_BYTES_32_TX_CQ_NUM_S,
2689	2649	to_hr_cq(ibqp->send_cq)->cqn);
2690	2650
2691		- context->cur_sq_wqe_ba_l = cpu_to_le32((u32)mtts[0]);
	2651	+ context->cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
2692	2652
2693	2653	roce_set_field(context->qp1c_bytes_40,
2694	2654	QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2695	2655	QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2696		- (mtts[0]) >> 32);
	2656	+ upper_32_bits(sq_ba));
2697	2657	roce_set_field(context->qp1c_bytes_40,
2698	2658	QP1C_BYTES_40_SQ_CUR_IDX_M,
2699	2659	QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
..	..	@@ -2737,7 +2697,6 @@
2737	2697	hr_qp->rq.tail = 0;
2738	2698	hr_qp->sq.head = 0;
2739	2699	hr_qp->sq.tail = 0;
2740		- hr_qp->sq_next_wqe = 0;
2741	2700	}
2742	2701
2743	2702	kfree(context);
..	..	@@ -2746,6 +2705,28 @@
2746	2705	out:
2747	2706	kfree(context);
2748	2707	return -EINVAL;
	2708	+}
	2709	+
	2710	+static bool check_qp_state(enum ib_qp_state cur_state,
	2711	+ enum ib_qp_state new_state)
	2712	+{
	2713	+ static const bool sm[][IB_QPS_ERR + 1] = {
	2714	+ [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
	2715	+ [IB_QPS_INIT] = true },
	2716	+ [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
	2717	+ [IB_QPS_INIT] = true,
	2718	+ [IB_QPS_RTR] = true,
	2719	+ [IB_QPS_ERR] = true },
	2720	+ [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
	2721	+ [IB_QPS_RTS] = true,
	2722	+ [IB_QPS_ERR] = true },
	2723	+ [IB_QPS_RTS] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true },
	2724	+ [IB_QPS_SQD] = {},
	2725	+ [IB_QPS_SQE] = {},
	2726	+ [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true }
	2727	+ };
	2728	+
	2729	+ return sm[cur_state][new_state];
2749	2730	}
2750	2731
2751	2732	static int hns_roce_v1_m_qp(struct ib_qp ibqp, const struct ib_qp_attr attr,
..	..	@@ -2760,26 +2741,29 @@
2760	2741	dma_addr_t dma_handle_2 = 0;
2761	2742	dma_addr_t dma_handle = 0;
2762	2743	__le32 doorbell[2] = {0};
2763		- int rq_pa_start = 0;
2764	2744	u64 *mtts_2 = NULL;
2765	2745	int ret = -EINVAL;
2766		- u64 *mtts = NULL;
	2746	+ u64 sq_ba = 0;
	2747	+ u64 rq_ba = 0;
2767	2748	int port;
2768	2749	u8 port_num;
2769	2750	u8 *dmac;
2770	2751	u8 *smac;
	2752	+
	2753	+ if (!check_qp_state(cur_state, new_state)) {
	2754	+ ibdev_err(ibqp->device,
	2755	+ "not support QP(%u) status from %d to %d\n",
	2756	+ ibqp->qp_num, cur_state, new_state);
	2757	+ return -EINVAL;
	2758	+ }
2771	2759
2772	2760	context = kzalloc(sizeof(*context), GFP_KERNEL);
2773	2761	if (!context)
2774	2762	return -ENOMEM;
2775	2763
2776	2764	/* Search qp buf's mtts */
2777		- mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2778		- hr_qp->mtt.first_seg, &dma_handle);
2779		- if (mtts == NULL) {
2780		- dev_err(dev, "qp buf pa find failed\n");
	2765	+ if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2781	2766	goto out;
2782		- }
2783	2767
2784	2768	/* Search IRRL's mtts */
2785	2769	mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
..	..	@@ -2852,7 +2836,6 @@
2852	2836	roce_set_field(context->qpc_bytes_16,
2853	2837	QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2854	2838	QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2855		-
2856	2839	} else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2857	2840	roce_set_field(context->qpc_bytes_4,
2858	2841	QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
..	..	@@ -2934,11 +2917,11 @@
2934	2917
2935	2918	dmac = (u8 *)attr->ah_attr.roce.dmac;
2936	2919
2937		- context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
	2920	+ context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2938	2921	roce_set_field(context->qpc_bytes_24,
2939	2922	QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2940	2923	QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2941		- ((u32)(dma_handle >> 32)));
	2924	+ upper_32_bits(dma_handle));
2942	2925	roce_set_bit(context->qpc_bytes_24,
2943	2926	QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2944	2927	1);
..	..	@@ -2960,7 +2943,7 @@
2960	2943	1);
2961	2944	roce_set_bit(context->qpc_bytes_32,
2962	2945	QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2963		- le32_to_cpu(hr_qp->sq_signal_bits));
	2946	+ hr_qp->sq_signal_bits);
2964	2947
2965	2948	port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2966	2949	hr_qp->port;
..	..	@@ -3037,14 +3020,12 @@
3037	3020	QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
3038	3021	QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
3039	3022
3040		- rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
3041		- context->cur_rq_wqe_ba_l =
3042		- cpu_to_le32((u32)(mtts[rq_pa_start]));
	3023	+ context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
3043	3024
3044	3025	roce_set_field(context->qpc_bytes_76,
3045	3026	QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
3046	3027	QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
3047		- mtts[rq_pa_start] >> 32);
	3028	+ upper_32_bits(rq_ba));
3048	3029	roce_set_field(context->qpc_bytes_76,
3049	3030	QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
3050	3031	QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
..	..	@@ -3106,8 +3087,7 @@
3106	3087	QP_CONTEXT_QPC_BYTES_156_SL_S,
3107	3088	rdma_ah_get_sl(&attr->ah_attr));
3108	3089	hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3109		- } else if (cur_state == IB_QPS_RTR &&
3110		- new_state == IB_QPS_RTS) {
	3090	+ } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3111	3091	/* If exist optional param, return error */
3112	3092	if ((attr_mask & IB_QP_ALT_PATH) \|\|
3113	3093	(attr_mask & IB_QP_ACCESS_FLAGS) \|\|
..	..	@@ -3119,12 +3099,12 @@
3119	3099	goto out;
3120	3100	}
3121	3101
3122		- context->rx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
	3102	+ context->rx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3123	3103
3124	3104	roce_set_field(context->qpc_bytes_120,
3125	3105	QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3126	3106	QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3127		- (mtts[0]) >> 32);
	3107	+ upper_32_bits(sq_ba));
3128	3108
3129	3109	roce_set_field(context->qpc_bytes_124,
3130	3110	QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
..	..	@@ -3267,28 +3247,18 @@
3267	3247	QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3268	3248	QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3269	3249
3270		- context->tx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
	3250	+ context->tx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3271	3251
3272	3252	roce_set_field(context->qpc_bytes_188,
3273	3253	QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3274	3254	QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3275		- (mtts[0]) >> 32);
	3255	+ upper_32_bits(sq_ba));
3276	3256	roce_set_bit(context->qpc_bytes_188,
3277	3257	QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3278	3258	roce_set_field(context->qpc_bytes_188,
3279	3259	QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3280	3260	QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3281	3261	0);
3282		- } else if (!((cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) \|\|
3283		- (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) \|\|
3284		- (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) \|\|
3285		- (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) \|\|
3286		- (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) \|\|
3287		- (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) \|\|
3288		- (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) \|\|
3289		- (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR))) {
3290		- dev_err(dev, "not support this status migration\n");
3291		- goto out;
3292	3262	}
3293	3263
3294	3264	/* Every status migrate must change state */
..	..	@@ -3297,8 +3267,7 @@
3297	3267	QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3298	3268
3299	3269	/* SW pass context to HW */
3300		- ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
3301		- to_hns_roce_state(cur_state),
	3270	+ ret = hns_roce_v1_qp_modify(hr_dev, to_hns_roce_state(cur_state),
3302	3271	to_hns_roce_state(new_state), context,
3303	3272	hr_qp);
3304	3273	if (ret) {
..	..	@@ -3351,7 +3320,6 @@
3351	3320	hr_qp->rq.tail = 0;
3352	3321	hr_qp->sq.head = 0;
3353	3322	hr_qp->sq.tail = 0;
3354		- hr_qp->sq_next_wqe = 0;
3355	3323	}
3356	3324	out:
3357	3325	kfree(context);
..	..	@@ -3494,7 +3462,7 @@
3494	3462	struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3495	3463	struct device *dev = &hr_dev->pdev->dev;
3496	3464	struct hns_roce_qp_context *context;
3497		- int tmp_qp_state = 0;
	3465	+ int tmp_qp_state;
3498	3466	int ret = 0;
3499	3467	int state;
3500	3468
..	..	@@ -3605,7 +3573,7 @@
3605	3573	qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3606	3574	QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3607	3575	QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3608		- qp_attr->rnr_retry = (u8)context->rnr_retry;
	3576	+ qp_attr->rnr_retry = (u8)le32_to_cpu(context->rnr_retry);
3609	3577
3610	3578	done:
3611	3579	qp_attr->cur_qp_state = qp_attr->qp_state;
..	..	@@ -3639,372 +3607,47 @@
3639	3607	hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3640	3608	}
3641	3609
3642		-static void hns_roce_check_sdb_status(struct hns_roce_dev *hr_dev,
3643		- u32 old_send, u32 old_retry,
3644		- u32 tsp_st, u32 success_flags)
3645		-{
3646		- __le32 old_send_tmp, old_retry_tmp;
3647		- u32 sdb_retry_cnt;
3648		- u32 sdb_send_ptr;
3649		- u32 cur_cnt, old_cnt;
3650		- __le32 tmp, tmp1;
3651		- u32 send_ptr;
3652		-
3653		- sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3654		- sdb_retry_cnt = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
3655		- tmp = cpu_to_le32(sdb_send_ptr);
3656		- tmp1 = cpu_to_le32(sdb_retry_cnt);
3657		- cur_cnt = roce_get_field(tmp, ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3658		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3659		- roce_get_field(tmp1, ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3660		- ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3661		-
3662		- old_send_tmp = (__le32 *)old_send;
3663		- old_retry_tmp = (__le32 *)old_retry;
3664		- if (!roce_get_bit(*tsp_st, ROCEE_CNT_CLR_CE_CNT_CLR_CE_S)) {
3665		- old_cnt = roce_get_field(*old_send_tmp,
3666		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3667		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3668		- roce_get_field(*old_retry_tmp,
3669		- ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3670		- ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3671		- if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3672		- *success_flags = 1;
3673		- } else {
3674		- old_cnt = roce_get_field(*old_send_tmp,
3675		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3676		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S);
3677		- if (cur_cnt - old_cnt > SDB_ST_CMP_VAL) {
3678		- *success_flags = 1;
3679		- } else {
3680		- send_ptr = roce_get_field(*old_send_tmp,
3681		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3682		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3683		- roce_get_field(tmp1,
3684		- ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3685		- ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3686		- roce_set_field(*old_send_tmp,
3687		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3688		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S,
3689		- send_ptr);
3690		- }
3691		- }
3692		-}
3693		-
3694		-static int check_qp_db_process_status(struct hns_roce_dev *hr_dev,
3695		- struct hns_roce_qp *hr_qp,
3696		- u32 sdb_issue_ptr,
3697		- u32 *sdb_inv_cnt,
3698		- u32 *wait_stage)
3699		-{
3700		- struct device *dev = &hr_dev->pdev->dev;
3701		- u32 sdb_send_ptr, old_send;
3702		- __le32 sdb_issue_ptr_tmp;
3703		- __le32 sdb_send_ptr_tmp;
3704		- u32 success_flags = 0;
3705		- unsigned long end;
3706		- u32 old_retry;
3707		- u32 inv_cnt;
3708		- u32 tsp_st;
3709		- __le32 tmp;
3710		-
3711		- if (*wait_stage > HNS_ROCE_V1_DB_STAGE2 \|\|
3712		- *wait_stage < HNS_ROCE_V1_DB_STAGE1) {
3713		- dev_err(dev, "QP(0x%lx) db status wait stage(%d) error!\n",
3714		- hr_qp->qpn, *wait_stage);
3715		- return -EINVAL;
3716		- }
3717		-
3718		- /* Calculate the total timeout for the entire verification process */
3719		- end = msecs_to_jiffies(HNS_ROCE_V1_CHECK_DB_TIMEOUT_MSECS) + jiffies;
3720		-
3721		- if (*wait_stage == HNS_ROCE_V1_DB_STAGE1) {
3722		- /* Query db process status, until hw process completely */
3723		- sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3724		- while (roce_hw_index_cmp_lt(sdb_send_ptr, sdb_issue_ptr,
3725		- ROCEE_SDB_PTR_CMP_BITS)) {
3726		- if (!time_before(jiffies, end)) {
3727		- dev_dbg(dev, "QP(0x%lx) db process stage1 timeout. issue 0x%x send 0x%x.\n",
3728		- hr_qp->qpn, sdb_issue_ptr,
3729		- sdb_send_ptr);
3730		- return 0;
3731		- }
3732		-
3733		- msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3734		- sdb_send_ptr = roce_read(hr_dev,
3735		- ROCEE_SDB_SEND_PTR_REG);
3736		- }
3737		-
3738		- sdb_send_ptr_tmp = cpu_to_le32(sdb_send_ptr);
3739		- sdb_issue_ptr_tmp = cpu_to_le32(sdb_issue_ptr);
3740		- if (roce_get_field(sdb_issue_ptr_tmp,
3741		- ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M,
3742		- ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S) ==
3743		- roce_get_field(sdb_send_ptr_tmp,
3744		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3745		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)) {
3746		- old_send = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3747		- old_retry = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
3748		-
3749		- do {
3750		- tsp_st = roce_read(hr_dev, ROCEE_TSP_BP_ST_REG);
3751		- tmp = cpu_to_le32(tsp_st);
3752		- if (roce_get_bit(tmp,
3753		- ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S) == 1) {
3754		- *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3755		- return 0;
3756		- }
3757		-
3758		- if (!time_before(jiffies, end)) {
3759		- dev_dbg(dev, "QP(0x%lx) db process stage1 timeout when send ptr equals issue ptr.\n"
3760		- "issue 0x%x send 0x%x.\n",
3761		- hr_qp->qpn,
3762		- le32_to_cpu(sdb_issue_ptr_tmp),
3763		- le32_to_cpu(sdb_send_ptr_tmp));
3764		- return 0;
3765		- }
3766		-
3767		- msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3768		-
3769		- hns_roce_check_sdb_status(hr_dev, &old_send,
3770		- &old_retry, &tsp_st,
3771		- &success_flags);
3772		- } while (!success_flags);
3773		- }
3774		-
3775		- *wait_stage = HNS_ROCE_V1_DB_STAGE2;
3776		-
3777		- /* Get list pointer */
3778		- *sdb_inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3779		- dev_dbg(dev, "QP(0x%lx) db process stage2. inv cnt = 0x%x.\n",
3780		- hr_qp->qpn, *sdb_inv_cnt);
3781		- }
3782		-
3783		- if (*wait_stage == HNS_ROCE_V1_DB_STAGE2) {
3784		- /* Query db's list status, until hw reversal */
3785		- inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3786		- while (roce_hw_index_cmp_lt(inv_cnt,
3787		- *sdb_inv_cnt + SDB_INV_CNT_OFFSET,
3788		- ROCEE_SDB_CNT_CMP_BITS)) {
3789		- if (!time_before(jiffies, end)) {
3790		- dev_dbg(dev, "QP(0x%lx) db process stage2 timeout. inv cnt 0x%x.\n",
3791		- hr_qp->qpn, inv_cnt);
3792		- return 0;
3793		- }
3794		-
3795		- msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3796		- inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3797		- }
3798		-
3799		- *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3800		- }
3801		-
3802		- return 0;
3803		-}
3804		-
3805		-static int check_qp_reset_state(struct hns_roce_dev *hr_dev,
3806		- struct hns_roce_qp *hr_qp,
3807		- struct hns_roce_qp_work *qp_work_entry,
3808		- int *is_timeout)
3809		-{
3810		- struct device *dev = &hr_dev->pdev->dev;
3811		- u32 sdb_issue_ptr;
3812		- int ret;
3813		-
3814		- if (hr_qp->state != IB_QPS_RESET) {
3815		- /* Set qp to ERR, waiting for hw complete processing all dbs */
3816		- ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3817		- IB_QPS_ERR);
3818		- if (ret) {
3819		- dev_err(dev, "Modify QP(0x%lx) to ERR failed!\n",
3820		- hr_qp->qpn);
3821		- return ret;
3822		- }
3823		-
3824		- /* Record issued doorbell */
3825		- sdb_issue_ptr = roce_read(hr_dev, ROCEE_SDB_ISSUE_PTR_REG);
3826		- qp_work_entry->sdb_issue_ptr = sdb_issue_ptr;
3827		- qp_work_entry->db_wait_stage = HNS_ROCE_V1_DB_STAGE1;
3828		-
3829		- /* Query db process status, until hw process completely */
3830		- ret = check_qp_db_process_status(hr_dev, hr_qp, sdb_issue_ptr,
3831		- &qp_work_entry->sdb_inv_cnt,
3832		- &qp_work_entry->db_wait_stage);
3833		- if (ret) {
3834		- dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3835		- hr_qp->qpn);
3836		- return ret;
3837		- }
3838		-
3839		- if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK) {
3840		- qp_work_entry->sche_cnt = 0;
3841		- *is_timeout = 1;
3842		- return 0;
3843		- }
3844		-
3845		- /* Modify qp to reset before destroying qp */
3846		- ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3847		- IB_QPS_RESET);
3848		- if (ret) {
3849		- dev_err(dev, "Modify QP(0x%lx) to RST failed!\n",
3850		- hr_qp->qpn);
3851		- return ret;
3852		- }
3853		- }
3854		-
3855		- return 0;
3856		-}
3857		-
3858		-static void hns_roce_v1_destroy_qp_work_fn(struct work_struct *work)
3859		-{
3860		- struct hns_roce_qp_work *qp_work_entry;
3861		- struct hns_roce_v1_priv *priv;
3862		- struct hns_roce_dev *hr_dev;
3863		- struct hns_roce_qp *hr_qp;
3864		- struct device *dev;
3865		- unsigned long qpn;
3866		- int ret;
3867		-
3868		- qp_work_entry = container_of(work, struct hns_roce_qp_work, work);
3869		- hr_dev = to_hr_dev(qp_work_entry->ib_dev);
3870		- dev = &hr_dev->pdev->dev;
3871		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
3872		- hr_qp = qp_work_entry->qp;
3873		- qpn = hr_qp->qpn;
3874		-
3875		- dev_dbg(dev, "Schedule destroy QP(0x%lx) work.\n", qpn);
3876		-
3877		- qp_work_entry->sche_cnt++;
3878		-
3879		- /* Query db process status, until hw process completely */
3880		- ret = check_qp_db_process_status(hr_dev, hr_qp,
3881		- qp_work_entry->sdb_issue_ptr,
3882		- &qp_work_entry->sdb_inv_cnt,
3883		- &qp_work_entry->db_wait_stage);
3884		- if (ret) {
3885		- dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3886		- qpn);
3887		- return;
3888		- }
3889		-
3890		- if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK &&
3891		- priv->des_qp.requeue_flag) {
3892		- queue_work(priv->des_qp.qp_wq, work);
3893		- return;
3894		- }
3895		-
3896		- /* Modify qp to reset before destroying qp */
3897		- ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3898		- IB_QPS_RESET);
3899		- if (ret) {
3900		- dev_err(dev, "Modify QP(0x%lx) to RST failed!\n", qpn);
3901		- return;
3902		- }
3903		-
3904		- hns_roce_qp_remove(hr_dev, hr_qp);
3905		- hns_roce_qp_free(hr_dev, hr_qp);
3906		-
3907		- if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
3908		- /* RC QP, release QPN */
3909		- hns_roce_release_range_qp(hr_dev, qpn, 1);
3910		- kfree(hr_qp);
3911		- } else
3912		- kfree(hr_to_hr_sqp(hr_qp));
3913		-
3914		- kfree(qp_work_entry);
3915		-
3916		- dev_dbg(dev, "Accomplished destroy QP(0x%lx) work.\n", qpn);
3917		-}
3918		-
3919		-int hns_roce_v1_destroy_qp(struct ib_qp *ibqp)
	3610	+int hns_roce_v1_destroy_qp(struct ib_qp ibqp, struct ib_udata udata)
3920	3611	{
3921	3612	struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3922	3613	struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3923		- struct device *dev = &hr_dev->pdev->dev;
3924		- struct hns_roce_qp_work qp_work_entry;
3925		- struct hns_roce_qp_work *qp_work;
3926		- struct hns_roce_v1_priv *priv;
3927	3614	struct hns_roce_cq send_cq, recv_cq;
3928		- int is_user = !!ibqp->pd->uobject;
3929		- int is_timeout = 0;
3930	3615	int ret;
3931	3616
3932		- ret = check_qp_reset_state(hr_dev, hr_qp, &qp_work_entry, &is_timeout);
3933		- if (ret) {
3934		- dev_err(dev, "QP reset state check failed(%d)!\n", ret);
	3617	+ ret = hns_roce_v1_modify_qp(ibqp, NULL, 0, hr_qp->state, IB_QPS_RESET);
	3618	+ if (ret)
3935	3619	return ret;
3936		- }
3937	3620
3938		- send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3939		- recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
	3621	+ send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
	3622	+ recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
3940	3623
3941	3624	hns_roce_lock_cqs(send_cq, recv_cq);
3942		- if (!is_user) {
3943		- __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3944		- to_hr_srq(hr_qp->ibqp.srq) : NULL);
3945		- if (send_cq != recv_cq)
	3625	+ if (!udata) {
	3626	+ if (recv_cq)
	3627	+ __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn,
	3628	+ (hr_qp->ibqp.srq ?
	3629	+ to_hr_srq(hr_qp->ibqp.srq) :
	3630	+ NULL));
	3631	+
	3632	+ if (send_cq && send_cq != recv_cq)
3946	3633	__hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3947	3634	}
	3635	+ hns_roce_qp_remove(hr_dev, hr_qp);
3948	3636	hns_roce_unlock_cqs(send_cq, recv_cq);
3949	3637
3950		- if (!is_timeout) {
3951		- hns_roce_qp_remove(hr_dev, hr_qp);
3952		- hns_roce_qp_free(hr_dev, hr_qp);
3953		-
3954		- /* RC QP, release QPN */
3955		- if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3956		- hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3957		- }
3958		-
3959		- hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3960		-
3961		- if (is_user)
3962		- ib_umem_release(hr_qp->umem);
3963		- else {
3964		- kfree(hr_qp->sq.wrid);
3965		- kfree(hr_qp->rq.wrid);
3966		-
3967		- hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3968		- }
3969		-
3970		- if (!is_timeout) {
3971		- if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3972		- kfree(hr_qp);
3973		- else
3974		- kfree(hr_to_hr_sqp(hr_qp));
3975		- } else {
3976		- qp_work = kzalloc(sizeof(*qp_work), GFP_KERNEL);
3977		- if (!qp_work)
3978		- return -ENOMEM;
3979		-
3980		- INIT_WORK(&qp_work->work, hns_roce_v1_destroy_qp_work_fn);
3981		- qp_work->ib_dev = &hr_dev->ib_dev;
3982		- qp_work->qp = hr_qp;
3983		- qp_work->db_wait_stage = qp_work_entry.db_wait_stage;
3984		- qp_work->sdb_issue_ptr = qp_work_entry.sdb_issue_ptr;
3985		- qp_work->sdb_inv_cnt = qp_work_entry.sdb_inv_cnt;
3986		- qp_work->sche_cnt = qp_work_entry.sche_cnt;
3987		-
3988		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
3989		- queue_work(priv->des_qp.qp_wq, &qp_work->work);
3990		- dev_dbg(dev, "Begin destroy QP(0x%lx) work.\n", hr_qp->qpn);
3991		- }
	3638	+ hns_roce_qp_destroy(hr_dev, hr_qp, udata);
3992	3639
3993	3640	return 0;
3994	3641	}
3995	3642
3996		-static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq)
	3643	+static int hns_roce_v1_destroy_cq(struct ib_cq ibcq, struct ib_udata udata)
3997	3644	{
3998	3645	struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3999	3646	struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
4000	3647	struct device *dev = &hr_dev->pdev->dev;
4001	3648	u32 cqe_cnt_ori;
4002	3649	u32 cqe_cnt_cur;
4003		- u32 cq_buf_size;
4004	3650	int wait_time = 0;
4005		- int ret = 0;
4006		-
4007		- hns_roce_free_cq(hr_dev, hr_cq);
4008	3651
4009	3652	/*
4010	3653	* Before freeing cq buffer, we need to ensure that the outstanding CQE
..	..	@@ -4024,25 +3667,11 @@
4024	3667	if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
4025	3668	dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
4026	3669	hr_cq->cqn);
4027		- ret = -ETIMEDOUT;
4028	3670	break;
4029	3671	}
4030	3672	wait_time++;
4031	3673	}
4032		-
4033		- hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
4034		-
4035		- if (ibcq->uobject)
4036		- ib_umem_release(hr_cq->umem);
4037		- else {
4038		- /* Free the buff of stored cq */
4039		- cq_buf_size = (ibcq->cqe + 1) * hr_dev->caps.cq_entry_sz;
4040		- hns_roce_buf_free(hr_dev, cq_buf_size, &hr_cq->hr_buf.hr_buf);
4041		- }
4042		-
4043		- kfree(hr_cq);
4044		-
4045		- return ret;
	3674	+ return 0;
4046	3675	}
4047	3676
4048	3677	static void set_eq_cons_index_v1(struct hns_roce_eq *eq, int req_not)
..	..	@@ -4215,8 +3844,7 @@
4215	3844
4216	3845	static struct hns_roce_aeqe get_aeqe_v1(struct hns_roce_eq eq, u32 entry)
4217	3846	{
4218		- unsigned long off = (entry & (eq->entries - 1)) *
4219		- HNS_ROCE_AEQ_ENTRY_SIZE;
	3847	+ unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQE_SIZE;
4220	3848
4221	3849	return (struct hns_roce_aeqe )((u8 )
4222	3850	(eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
..	..	@@ -4240,13 +3868,13 @@
4240	3868	int event_type;
4241	3869
4242	3870	while ((aeqe = next_aeqe_sw_v1(eq))) {
4243		-
4244	3871	/* Make sure we read the AEQ entry after we have checked the
4245	3872	* ownership bit
4246	3873	*/
4247	3874	dma_rmb();
4248	3875
4249		- dev_dbg(dev, "aeqe = %p, aeqe->asyn.event_type = 0x%lx\n", aeqe,
	3876	+ dev_dbg(dev, "aeqe = %pK, aeqe->asyn.event_type = 0x%lx\n",
	3877	+ aeqe,
4250	3878	roce_get_field(aeqe->asyn,
4251	3879	HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
4252	3880	HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
..	..	@@ -4309,10 +3937,8 @@
4309	3937	eq->cons_index++;
4310	3938	aeqes_found = 1;
4311	3939
4312		- if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1) {
4313		- dev_warn(dev, "cons_index overflow, set back to 0.\n");
	3940	+ if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1)
4314	3941	eq->cons_index = 0;
4315		- }
4316	3942	}
4317	3943
4318	3944	set_eq_cons_index_v1(eq, 0);
..	..	@@ -4322,8 +3948,7 @@
4322	3948
4323	3949	static struct hns_roce_ceqe get_ceqe_v1(struct hns_roce_eq eq, u32 entry)
4324	3950	{
4325		- unsigned long off = (entry & (eq->entries - 1)) *
4326		- HNS_ROCE_CEQ_ENTRY_SIZE;
	3951	+ unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQE_SIZE;
4327	3952
4328	3953	return (struct hns_roce_ceqe )((u8 )
4329	3954	(eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
..	..	@@ -4347,7 +3972,6 @@
4347	3972	u32 cqn;
4348	3973
4349	3974	while ((ceqe = next_ceqe_sw_v1(eq))) {
4350		-
4351	3975	/* Make sure we read CEQ entry after we have checked the
4352	3976	* ownership bit
4353	3977	*/
..	..	@@ -4361,11 +3985,9 @@
4361	3985	++eq->cons_index;
4362	3986	ceqes_found = 1;
4363	3987
4364		- if (eq->cons_index > 2 * hr_dev->caps.ceqe_depth - 1) {
4365		- dev_warn(&eq->hr_dev->pdev->dev,
4366		- "cons_index overflow, set back to 0.\n");
	3988	+ if (eq->cons_index >
	3989	+ EQ_DEPTH_COEFF * hr_dev->caps.ceqe_depth - 1)
4367	3990	eq->cons_index = 0;
4368		- }
4369	3991	}
4370	3992
4371	3993	set_eq_cons_index_v1(eq, 0);
..	..	@@ -4377,7 +3999,7 @@
4377	3999	{
4378	4000	struct hns_roce_eq *eq = eq_ptr;
4379	4001	struct hns_roce_dev *hr_dev = eq->hr_dev;
4380		- int int_work = 0;
	4002	+ int int_work;
4381	4003
4382	4004	if (eq->type_flag == HNS_ROCE_CEQ)
4383	4005	/* CEQ irq routine, CEQ is pulse irq, not clear */
..	..	@@ -4575,9 +4197,9 @@
4575	4197	void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn];
4576	4198	struct device *dev = &hr_dev->pdev->dev;
4577	4199	dma_addr_t tmp_dma_addr;
4578		- u32 eqconsindx_val = 0;
4579	4200	u32 eqcuridx_val = 0;
4580		- u32 eqshift_val = 0;
	4201	+ u32 eqconsindx_val;
	4202	+ u32 eqshift_val;
4581	4203	__le32 tmp2 = 0;
4582	4204	__le32 tmp1 = 0;
4583	4205	__le32 tmp = 0;
..	..	@@ -4609,7 +4231,6 @@
4609	4231	}
4610	4232
4611	4233	eq->buf_list[i].map = tmp_dma_addr;
4612		- memset(eq->buf_list[i].buf, 0, HNS_ROCE_BA_SIZE);
4613	4234	}
4614	4235	eq->cons_index = 0;
4615	4236	roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
..	..	@@ -4697,7 +4318,7 @@
4697	4318	CEQ_REG_OFFSET * i;
4698	4319	eq->entries = hr_dev->caps.ceqe_depth;
4699	4320	eq->log_entries = ilog2(eq->entries);
4700		- eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
	4321	+ eq->eqe_size = HNS_ROCE_CEQE_SIZE;
4701	4322	} else {
4702	4323	/* AEQ */
4703	4324	eq_table->eqc_base[i] = hr_dev->reg_base +
..	..	@@ -4707,7 +4328,7 @@
4707	4328	ROCEE_CAEP_AEQE_CONS_IDX_REG;
4708	4329	eq->entries = hr_dev->caps.aeqe_depth;
4709	4330	eq->log_entries = ilog2(eq->entries);
4710		- eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
	4331	+ eq->eqe_size = HNS_ROCE_AEQE_SIZE;
4711	4332	}
4712	4333	}
4713	4334
..	..	@@ -4792,6 +4413,15 @@
4792	4413	kfree(eq_table->eq);
4793	4414	}
4794	4415
	4416	+static const struct ib_device_ops hns_roce_v1_dev_ops = {
	4417	+ .destroy_qp = hns_roce_v1_destroy_qp,
	4418	+ .poll_cq = hns_roce_v1_poll_cq,
	4419	+ .post_recv = hns_roce_v1_post_recv,
	4420	+ .post_send = hns_roce_v1_post_send,
	4421	+ .query_qp = hns_roce_v1_query_qp,
	4422	+ .req_notify_cq = hns_roce_v1_req_notify_cq,
	4423	+};
	4424	+
4795	4425	static const struct hns_roce_hw hns_roce_hw_v1 = {
4796	4426	.reset = hns_roce_v1_reset,
4797	4427	.hw_profile = hns_roce_v1_profile,
..	..	@@ -4804,7 +4434,7 @@
4804	4434	.set_mtu = hns_roce_v1_set_mtu,
4805	4435	.write_mtpt = hns_roce_v1_write_mtpt,
4806	4436	.write_cqc = hns_roce_v1_write_cqc,
4807		- .modify_cq = hns_roce_v1_modify_cq,
	4437	+ .set_hem = hns_roce_v1_set_hem,
4808	4438	.clear_hem = hns_roce_v1_clear_hem,
4809	4439	.modify_qp = hns_roce_v1_modify_qp,
4810	4440	.query_qp = hns_roce_v1_query_qp,
..	..	@@ -4817,6 +4447,7 @@
4817	4447	.destroy_cq = hns_roce_v1_destroy_cq,
4818	4448	.init_eq = hns_roce_v1_init_eq_table,
4819	4449	.cleanup_eq = hns_roce_v1_cleanup_eq_table,
	4450	+ .hns_roce_dev_ops = &hns_roce_v1_dev_ops,
4820	4451	};
4821	4452
4822	4453	static const struct of_device_id hns_roce_of_match[] = {
..	..	@@ -4831,19 +4462,13 @@
4831	4462	};
4832	4463	MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
4833	4464
4834		-static int hns_roce_node_match(struct device dev, void fwnode)
4835		-{
4836		- return dev->fwnode == fwnode;
4837		-}
4838		-
4839	4465	static struct
4840	4466	platform_device hns_roce_find_pdev(struct fwnode_handle fwnode)
4841	4467	{
4842	4468	struct device *dev;
4843	4469
4844	4470	/* get the 'device' corresponding to the matching 'fwnode' */
4845		- dev = bus_find_device(&platform_bus_type, NULL,
4846		- fwnode, hns_roce_node_match);
	4471	+ dev = bus_find_device_by_fwnode(&platform_bus_type, fwnode);
4847	4472	/* get the platform device */
4848	4473	return dev ? to_platform_device(dev) : NULL;
4849	4474	}
..	..	@@ -4854,7 +4479,6 @@
4854	4479	struct platform_device *pdev = NULL;
4855	4480	struct net_device *netdev = NULL;
4856	4481	struct device_node *net_node;
4857		- struct resource *res;
4858	4482	int port_cnt = 0;
4859	4483	u8 phy_port;
4860	4484	int ret;
..	..	@@ -4893,8 +4517,7 @@
4893	4517	}
4894	4518
4895	4519	/* get the mapped register base address */
4896		- res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
4897		- hr_dev->reg_base = devm_ioremap_resource(dev, res);
	4520	+ hr_dev->reg_base = devm_platform_ioremap_resource(hr_dev->pdev, 0);
4898	4521	if (IS_ERR(hr_dev->reg_base))
4899	4522	return PTR_ERR(hr_dev->reg_base);
4900	4523
..	..	@@ -4969,10 +4592,8 @@
4969	4592	/* fetch the interrupt numbers */
4970	4593	for (i = 0; i < HNS_ROCE_V1_MAX_IRQ_NUM; i++) {
4971	4594	hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4972		- if (hr_dev->irq[i] <= 0) {
4973		- dev_err(dev, "platform get of irq[=%d] failed!\n", i);
	4595	+ if (hr_dev->irq[i] <= 0)
4974	4596	return -EINVAL;
4975		- }
4976	4597	}
4977	4598
4978	4599	return 0;
..	..	@@ -4990,7 +4611,7 @@
4990	4611	struct hns_roce_dev *hr_dev;
4991	4612	struct device *dev = &pdev->dev;
4992	4613
4993		- hr_dev = (struct hns_roce_dev )ib_alloc_device(sizeof(hr_dev));
	4614	+ hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
4994	4615	if (!hr_dev)
4995	4616	return -ENOMEM;
4996	4617