forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-10 ee930fffee469d076998274a2ca55e13dc1efb67 
 kernel/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
....@@ -23,7 +23,11 @@
2323  *
2424  */
2525 
26
+#include <linux/delay.h>
27
+#include <linux/slab.h>
28
+
2629 #include "dm_services.h"
30
+#include "basics/dc_common.h"
2731 #include "dc.h"
2832 #include "core_types.h"
2933 #include "resource.h"
....@@ -35,35 +39,37 @@
3539 /*******************************************************************************
3640  * Private functions
3741  ******************************************************************************/
38
-void update_stream_signal(struct dc_stream_state *stream)
42
+void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink)
3943 {
40
-
41
-	struct dc_sink *dc_sink = stream->sink;
42
-
43
-	if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
44
-		stream->signal = stream->sink->link->connector_signal;
44
+	if (sink->sink_signal == SIGNAL_TYPE_NONE)
45
+		stream->signal = stream->link->connector_signal;
4546 	else
46
-		stream->signal = dc_sink->sink_signal;
47
+		stream->signal = sink->sink_signal;
4748 
4849 	if (dc_is_dvi_signal(stream->signal)) {
4950 		if (stream->ctx->dc->caps.dual_link_dvi &&
50
-		    stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK &&
51
-		    stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
51
+			(stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK &&
52
+			sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
5253 			stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
5354 		else
5455 			stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
5556 	}
5657 }
5758 
58
-static void construct(struct dc_stream_state *stream,
59
+static bool dc_stream_construct(struct dc_stream_state *stream,
5960 	struct dc_sink *dc_sink_data)
6061 {
6162 	uint32_t i = 0;
6263 
6364 	stream->sink = dc_sink_data;
64
-	stream->ctx = stream->sink->ctx;
65
-
6665 	dc_sink_retain(dc_sink_data);
66
+
67
+	stream->ctx = dc_sink_data->ctx;
68
+	stream->link = dc_sink_data->link;
69
+	stream->sink_patches = dc_sink_data->edid_caps.panel_patch;
70
+	stream->converter_disable_audio = dc_sink_data->converter_disable_audio;
71
+	stream->qs_bit = dc_sink_data->edid_caps.qs_bit;
72
+	stream->qy_bit = dc_sink_data->edid_caps.qy_bit;
6773 
6874 	/* Copy audio modes */
6975 	/* TODO - Remove this translation */
....@@ -100,15 +106,31 @@
100106 	/* EDID CAP translation for HDMI 2.0 */
101107 	stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
102108 
103
-	stream->status.link = stream->sink->link;
109
+	memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
110
+	stream->timing.dsc_cfg.num_slices_h = 0;
111
+	stream->timing.dsc_cfg.num_slices_v = 0;
112
+	stream->timing.dsc_cfg.bits_per_pixel = 128;
113
+	stream->timing.dsc_cfg.block_pred_enable = 1;
114
+	stream->timing.dsc_cfg.linebuf_depth = 9;
115
+	stream->timing.dsc_cfg.version_minor = 2;
116
+	stream->timing.dsc_cfg.ycbcr422_simple = 0;
104117 
105
-	update_stream_signal(stream);
118
+	update_stream_signal(stream, dc_sink_data);
106119 
107120 	stream->out_transfer_func = dc_create_transfer_func();
121
+	if (stream->out_transfer_func == NULL) {
122
+		dc_sink_release(dc_sink_data);
123
+		return false;
124
+	}
108125 	stream->out_transfer_func->type = TF_TYPE_BYPASS;
126
+
127
+	stream->stream_id = stream->ctx->dc_stream_id_count;
128
+	stream->ctx->dc_stream_id_count++;
129
+
130
+	return true;
109131 }
110132 
111
-static void destruct(struct dc_stream_state *stream)
133
+static void dc_stream_destruct(struct dc_stream_state *stream)
112134 {
113135 	dc_sink_release(stream->sink);
114136 	if (stream->out_transfer_func != NULL) {
....@@ -126,7 +148,7 @@
126148 {
127149 	struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount);
128150 
129
-	destruct(stream);
151
+	dc_stream_destruct(stream);
130152 	kfree(stream);
131153 }
132154 
....@@ -147,40 +169,112 @@
147169 
148170 	stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL);
149171 	if (stream == NULL)
150
-		return NULL;
172
+		goto alloc_fail;
151173 
152
-	construct(stream, sink);
174
+	if (dc_stream_construct(stream, sink) == false)
175
+		goto construct_fail;
153176 
154177 	kref_init(&stream->refcount);
155178 
156179 	return stream;
180
+
181
+construct_fail:
182
+	kfree(stream);
183
+
184
+alloc_fail:
185
+	return NULL;
157186 }
158187 
159
-struct dc_stream_status *dc_stream_get_status(
188
+struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream)
189
+{
190
+	struct dc_stream_state *new_stream;
191
+
192
+	new_stream = kmemdup(stream, sizeof(struct dc_stream_state), GFP_KERNEL);
193
+	if (!new_stream)
194
+		return NULL;
195
+
196
+	if (new_stream->sink)
197
+		dc_sink_retain(new_stream->sink);
198
+
199
+	if (new_stream->out_transfer_func)
200
+		dc_transfer_func_retain(new_stream->out_transfer_func);
201
+
202
+	new_stream->stream_id = new_stream->ctx->dc_stream_id_count;
203
+	new_stream->ctx->dc_stream_id_count++;
204
+
205
+	kref_init(&new_stream->refcount);
206
+
207
+	return new_stream;
208
+}
209
+
210
+/**
211
+ * dc_stream_get_status_from_state - Get stream status from given dc state
212
+ * @state: DC state to find the stream status in
213
+ * @stream: The stream to get the stream status for
214
+ *
215
+ * The given stream is expected to exist in the given dc state. Otherwise, NULL
216
+ * will be returned.
217
+ */
218
+struct dc_stream_status *dc_stream_get_status_from_state(
219
+	struct dc_state *state,
160220 	struct dc_stream_state *stream)
161221 {
162222 	uint8_t i;
163
-	struct dc  *dc = stream->ctx->dc;
164223 
165
-	for (i = 0; i < dc->current_state->stream_count; i++) {
166
-		if (stream == dc->current_state->streams[i])
167
-			return &dc->current_state->stream_status[i];
224
+	for (i = 0; i < state->stream_count; i++) {
225
+		if (stream == state->streams[i])
226
+			return &state->stream_status[i];
168227 	}
169228 
170229 	return NULL;
171230 }
172231 
173232 /**
174
- * Update the cursor attributes and set cursor surface address
233
+ * dc_stream_get_status() - Get current stream status of the given stream state
234
+ * @stream: The stream to get the stream status for.
235
+ *
236
+ * The given stream is expected to exist in dc->current_state. Otherwise, NULL
237
+ * will be returned.
238
+ */
239
+struct dc_stream_status *dc_stream_get_status(
240
+	struct dc_stream_state *stream)
241
+{
242
+	struct dc *dc = stream->ctx->dc;
243
+	return dc_stream_get_status_from_state(dc->current_state, stream);
244
+}
245
+
246
+#ifndef TRIM_FSFT
247
+/**
248
+ * dc_optimize_timing_for_fsft() - dc to optimize timing
249
+ */
250
+bool dc_optimize_timing_for_fsft(
251
+	struct dc_stream_state *pStream,
252
+	unsigned int max_input_rate_in_khz)
253
+{
254
+	struct dc  *dc;
255
+
256
+	dc = pStream->ctx->dc;
257
+
258
+	return (dc->hwss.optimize_timing_for_fsft &&
259
+		dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz));
260
+}
261
+#endif
262
+
263
+
264
+/**
265
+ * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address
175266  */
176267 bool dc_stream_set_cursor_attributes(
177268 	struct dc_stream_state *stream,
178269 	const struct dc_cursor_attributes *attributes)
179270 {
180271 	int i;
181
-	struct dc  *core_dc;
272
+	struct dc  *dc;
182273 	struct resource_context *res_ctx;
183274 	struct pipe_ctx *pipe_to_program = NULL;
275
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
276
+	bool reset_idle_optimizations = false;
277
+#endif
184278 
185279 	if (NULL == stream) {
186280 		dm_error("DC: dc_stream is NULL!\n");
....@@ -196,31 +290,44 @@
196290 		return false;
197291 	}
198292 
199
-	core_dc = stream->ctx->dc;
200
-	res_ctx = &core_dc->current_state->res_ctx;
293
+	dc = stream->ctx->dc;
294
+	res_ctx = &dc->current_state->res_ctx;
201295 	stream->cursor_attributes = *attributes;
296
+
297
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
298
+	/* disable idle optimizations while updating cursor */
299
+	if (dc->idle_optimizations_allowed) {
300
+		dc_allow_idle_optimizations(dc, false);
301
+		reset_idle_optimizations = true;
302
+	}
303
+
304
+#endif
202305 
203306 	for (i = 0; i < MAX_PIPES; i++) {
204307 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
205308 
206309 		if (pipe_ctx->stream != stream)
207310 			continue;
208
-		if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
209
-			continue;
210311 
211312 		if (!pipe_to_program) {
212313 			pipe_to_program = pipe_ctx;
213
-			core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
314
+			dc->hwss.cursor_lock(dc, pipe_to_program, true);
214315 		}
215316 
216
-		core_dc->hwss.set_cursor_attribute(pipe_ctx);
217
-		if (core_dc->hwss.set_cursor_sdr_white_level)
218
-			core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
317
+		dc->hwss.set_cursor_attribute(pipe_ctx);
318
+		if (dc->hwss.set_cursor_sdr_white_level)
319
+			dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
219320 	}
220321 
221322 	if (pipe_to_program)
222
-		core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
323
+		dc->hwss.cursor_lock(dc, pipe_to_program, false);
223324 
325
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
326
+	/* re-enable idle optimizations if necessary */
327
+	if (reset_idle_optimizations)
328
+		dc_allow_idle_optimizations(dc, true);
329
+
330
+#endif
224331 	return true;
225332 }
226333 
....@@ -229,9 +336,12 @@
229336 	const struct dc_cursor_position *position)
230337 {
231338 	int i;
232
-	struct dc  *core_dc;
339
+	struct dc  *dc;
233340 	struct resource_context *res_ctx;
234341 	struct pipe_ctx *pipe_to_program = NULL;
342
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
343
+	bool reset_idle_optimizations = false;
344
+#endif
235345 
236346 	if (NULL == stream) {
237347 		dm_error("DC: dc_stream is NULL!\n");
....@@ -243,8 +353,17 @@
243353 		return false;
244354 	}
245355 
246
-	core_dc = stream->ctx->dc;
247
-	res_ctx = &core_dc->current_state->res_ctx;
356
+	dc = stream->ctx->dc;
357
+	res_ctx = &dc->current_state->res_ctx;
358
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
359
+
360
+	/* disable idle optimizations if enabling cursor */
361
+	if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) {
362
+		dc_allow_idle_optimizations(dc, false);
363
+		reset_idle_optimizations = true;
364
+	}
365
+
366
+#endif
248367 	stream->cursor_position = *position;
249368 
250369 	for (i = 0; i < MAX_PIPES; i++) {
....@@ -254,29 +373,163 @@
254373 				(!pipe_ctx->plane_res.mi  && !pipe_ctx->plane_res.hubp) ||
255374 				!pipe_ctx->plane_state ||
256375 				(!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||
257
-				!pipe_ctx->plane_res.ipp)
376
+				(!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))
258377 			continue;
259378 
260379 		if (!pipe_to_program) {
261380 			pipe_to_program = pipe_ctx;
262
-			core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
381
+			dc->hwss.cursor_lock(dc, pipe_to_program, true);
263382 		}
264383 
265
-		core_dc->hwss.set_cursor_position(pipe_ctx);
384
+		dc->hwss.set_cursor_position(pipe_ctx);
266385 	}
267386 
268387 	if (pipe_to_program)
269
-		core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
388
+		dc->hwss.cursor_lock(dc, pipe_to_program, false);
270389 
390
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
391
+	/* re-enable idle optimizations if necessary */
392
+	if (reset_idle_optimizations)
393
+		dc_allow_idle_optimizations(dc, true);
394
+
395
+#endif
271396 	return true;
272397 }
273398 
399
+bool dc_stream_add_writeback(struct dc *dc,
400
+		struct dc_stream_state *stream,
401
+		struct dc_writeback_info *wb_info)
402
+{
403
+	bool isDrc = false;
404
+	int i = 0;
405
+	struct dwbc *dwb;
406
+
407
+	if (stream == NULL) {
408
+		dm_error("DC: dc_stream is NULL!\n");
409
+		return false;
410
+	}
411
+
412
+	if (wb_info == NULL) {
413
+		dm_error("DC: dc_writeback_info is NULL!\n");
414
+		return false;
415
+	}
416
+
417
+	if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) {
418
+		dm_error("DC: writeback pipe is invalid!\n");
419
+		return false;
420
+	}
421
+
422
+	wb_info->dwb_params.out_transfer_func = stream->out_transfer_func;
423
+
424
+	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
425
+	dwb->dwb_is_drc = false;
426
+
427
+	/* recalculate and apply DML parameters */
428
+
429
+	for (i = 0; i < stream->num_wb_info; i++) {
430
+		/*dynamic update*/
431
+		if (stream->writeback_info[i].wb_enabled &&
432
+			stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) {
433
+			stream->writeback_info[i] = *wb_info;
434
+			isDrc = true;
435
+		}
436
+	}
437
+
438
+	if (!isDrc) {
439
+		stream->writeback_info[stream->num_wb_info++] = *wb_info;
440
+	}
441
+
442
+	if (dc->hwss.enable_writeback) {
443
+		struct dc_stream_status *stream_status = dc_stream_get_status(stream);
444
+		struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
445
+		dwb->otg_inst = stream_status->primary_otg_inst;
446
+	}
447
+	if (IS_DIAG_DC(dc->ctx->dce_environment)) {
448
+		if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
449
+			dm_error("DC: update_bandwidth failed!\n");
450
+			return false;
451
+		}
452
+
453
+		/* enable writeback */
454
+		if (dc->hwss.enable_writeback) {
455
+			struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
456
+
457
+			if (dwb->funcs->is_enabled(dwb)) {
458
+				/* writeback pipe already enabled, only need to update */
459
+				dc->hwss.update_writeback(dc, wb_info, dc->current_state);
460
+			} else {
461
+				/* Enable writeback pipe from scratch*/
462
+				dc->hwss.enable_writeback(dc, wb_info, dc->current_state);
463
+			}
464
+		}
465
+	}
466
+	return true;
467
+}
468
+
469
+bool dc_stream_remove_writeback(struct dc *dc,
470
+		struct dc_stream_state *stream,
471
+		uint32_t dwb_pipe_inst)
472
+{
473
+	int i = 0, j = 0;
474
+	if (stream == NULL) {
475
+		dm_error("DC: dc_stream is NULL!\n");
476
+		return false;
477
+	}
478
+
479
+	if (dwb_pipe_inst >= MAX_DWB_PIPES) {
480
+		dm_error("DC: writeback pipe is invalid!\n");
481
+		return false;
482
+	}
483
+
484
+//	stream->writeback_info[dwb_pipe_inst].wb_enabled = false;
485
+	for (i = 0; i < stream->num_wb_info; i++) {
486
+		/*dynamic update*/
487
+		if (stream->writeback_info[i].wb_enabled &&
488
+			stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) {
489
+			stream->writeback_info[i].wb_enabled = false;
490
+		}
491
+	}
492
+
493
+	/* remove writeback info for disabled writeback pipes from stream */
494
+	for (i = 0, j = 0; i < stream->num_wb_info; i++) {
495
+		if (stream->writeback_info[i].wb_enabled) {
496
+			if (i != j)
497
+				/* trim the array */
498
+				stream->writeback_info[j] = stream->writeback_info[i];
499
+			j++;
500
+		}
501
+	}
502
+	stream->num_wb_info = j;
503
+
504
+	if (IS_DIAG_DC(dc->ctx->dce_environment)) {
505
+		/* recalculate and apply DML parameters */
506
+		if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
507
+			dm_error("DC: update_bandwidth failed!\n");
508
+			return false;
509
+		}
510
+
511
+		/* disable writeback */
512
+		if (dc->hwss.disable_writeback)
513
+			dc->hwss.disable_writeback(dc, dwb_pipe_inst);
514
+	}
515
+	return true;
516
+}
517
+
518
+bool dc_stream_warmup_writeback(struct dc *dc,
519
+		int num_dwb,
520
+		struct dc_writeback_info *wb_info)
521
+{
522
+	if (dc->hwss.mmhubbub_warmup)
523
+		return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info);
524
+	else
525
+		return false;
526
+}
274527 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
275528 {
276529 	uint8_t i;
277
-	struct dc  *core_dc = stream->ctx->dc;
530
+	struct dc  *dc = stream->ctx->dc;
278531 	struct resource_context *res_ctx =
279
-		&core_dc->current_state->res_ctx;
532
+		&dc->current_state->res_ctx;
280533 
281534 	for (i = 0; i < MAX_PIPES; i++) {
282535 		struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
....@@ -290,6 +543,41 @@
290543 	return 0;
291544 }
292545 
546
+bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
547
+		const uint8_t *custom_sdp_message,
548
+		unsigned int sdp_message_size)
549
+{
550
+	int i;
551
+	struct dc  *dc;
552
+	struct resource_context *res_ctx;
553
+
554
+	if (stream == NULL) {
555
+		dm_error("DC: dc_stream is NULL!\n");
556
+		return false;
557
+	}
558
+
559
+	dc = stream->ctx->dc;
560
+	res_ctx = &dc->current_state->res_ctx;
561
+
562
+	for (i = 0; i < MAX_PIPES; i++) {
563
+		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
564
+
565
+		if (pipe_ctx->stream != stream)
566
+			continue;
567
+
568
+		if (dc->hwss.send_immediate_sdp_message != NULL)
569
+			dc->hwss.send_immediate_sdp_message(pipe_ctx,
570
+								custom_sdp_message,
571
+								sdp_message_size);
572
+		else
573
+			DC_LOG_WARNING("%s:send_immediate_sdp_message not implemented on this ASIC\n",
574
+			__func__);
575
+
576
+	}
577
+
578
+	return true;
579
+}
580
+
293581 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
294582 				  uint32_t *v_blank_start,
295583 				  uint32_t *v_blank_end,
....@@ -298,9 +586,9 @@
298586 {
299587 	uint8_t i;
300588 	bool ret = false;
301
-	struct dc  *core_dc = stream->ctx->dc;
589
+	struct dc  *dc = stream->ctx->dc;
302590 	struct resource_context *res_ctx =
303
-		&core_dc->current_state->res_ctx;
591
+		&dc->current_state->res_ctx;
304592 
305593 	for (i = 0; i < MAX_PIPES; i++) {
306594 		struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
....@@ -321,6 +609,78 @@
321609 	return ret;
322610 }
323611 
612
+bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
613
+{
614
+	struct pipe_ctx *pipe = NULL;
615
+	int i;
616
+
617
+	if (!dc->hwss.dmdata_status_done)
618
+		return false;
619
+
620
+	for (i = 0; i < MAX_PIPES; i++) {
621
+		pipe = &dc->current_state->res_ctx.pipe_ctx[i];
622
+		if (pipe->stream == stream)
623
+			break;
624
+	}
625
+	/* Stream not found, by default we'll assume HUBP fetched dm data */
626
+	if (i == MAX_PIPES)
627
+		return true;
628
+
629
+	return dc->hwss.dmdata_status_done(pipe);
630
+}
631
+
632
+bool dc_stream_set_dynamic_metadata(struct dc *dc,
633
+		struct dc_stream_state *stream,
634
+		struct dc_dmdata_attributes *attr)
635
+{
636
+	struct pipe_ctx *pipe_ctx = NULL;
637
+	struct hubp *hubp;
638
+	int i;
639
+
640
+	/* Dynamic metadata is only supported on HDMI or DP */
641
+	if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal))
642
+		return false;
643
+
644
+	/* Check hardware support */
645
+	if (!dc->hwss.program_dmdata_engine)
646
+		return false;
647
+
648
+	for (i = 0; i < MAX_PIPES; i++) {
649
+		pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
650
+		if (pipe_ctx->stream == stream)
651
+			break;
652
+	}
653
+
654
+	if (i == MAX_PIPES)
655
+		return false;
656
+
657
+	hubp = pipe_ctx->plane_res.hubp;
658
+	if (hubp == NULL)
659
+		return false;
660
+
661
+	pipe_ctx->stream->dmdata_address = attr->address;
662
+
663
+	dc->hwss.program_dmdata_engine(pipe_ctx);
664
+
665
+	if (hubp->funcs->dmdata_set_attributes != NULL &&
666
+			pipe_ctx->stream->dmdata_address.quad_part != 0) {
667
+		hubp->funcs->dmdata_set_attributes(hubp, attr);
668
+	}
669
+
670
+	return true;
671
+}
672
+
673
+enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,
674
+		struct dc_state *state,
675
+		struct dc_stream_state *stream)
676
+{
677
+	if (dc->res_pool->funcs->add_dsc_to_stream_resource) {
678
+		return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream);
679
+	} else {
680
+		return DC_NO_DSC_RESOURCE;
681
+	}
682
+}
683
+
324684 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
325685 {
326686 	DC_LOG_DC(
....@@ -337,16 +697,13 @@
337697 			stream->output_color_space);
338698 	DC_LOG_DC(
339699 			"\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",
340
-			stream->timing.pix_clk_khz,
700
+			stream->timing.pix_clk_100hz / 10,
341701 			stream->timing.h_total,
342702 			stream->timing.v_total,
343703 			stream->timing.pixel_encoding,
344704 			stream->timing.display_color_depth);
345705 	DC_LOG_DC(
346
-			"\tsink name: %s, serial: %d\n",
347
-			stream->sink->edid_caps.display_name,
348
-			stream->sink->edid_caps.serial_number);
349
-	DC_LOG_DC(
350706 			"\tlink: %d\n",
351
-			stream->sink->link->link_index);
707
+			stream->link->link_index);
352708 }
709
+