forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-05-10 ee930fffee469d076998274a2ca55e13dc1efb67 
 kernel/drivers/crypto/cavium/nitrox/nitrox_dev.h
....@@ -5,92 +5,199 @@
55 #include <linux/dma-mapping.h>
66 #include <linux/interrupt.h>
77 #include <linux/pci.h>
8
+#include <linux/if.h>
89 
910 #define VERSION_LEN 32
11
+/* Maximum queues in PF mode */
12
+#define MAX_PF_QUEUES	64
13
+/* Maximum device queues */
14
+#define MAX_DEV_QUEUES (MAX_PF_QUEUES)
15
+/* Maximum UCD Blocks */
16
+#define CNN55XX_MAX_UCD_BLOCKS	8
1017 
18
+/**
19
+ * struct nitrox_cmdq - NITROX command queue
20
+ * @cmd_qlock: command queue lock
21
+ * @resp_qlock: response queue lock
22
+ * @backlog_qlock: backlog queue lock
23
+ * @ndev: NITROX device
24
+ * @response_head: submitted request list
25
+ * @backlog_head: backlog queue
26
+ * @dbell_csr_addr: doorbell register address for this queue
27
+ * @compl_cnt_csr_addr: completion count register address of the slc port
28
+ * @base: command queue base address
29
+ * @dma: dma address of the base
30
+ * @pending_count: request pending at device
31
+ * @backlog_count: backlog request count
32
+ * @write_idx: next write index for the command
33
+ * @instr_size: command size
34
+ * @qno: command queue number
35
+ * @qsize: command queue size
36
+ * @unalign_base: unaligned base address
37
+ * @unalign_dma: unaligned dma address
38
+ */
1139 struct nitrox_cmdq {
12
-	/* command queue lock */
13
-	spinlock_t cmdq_lock;
14
-	/* response list lock */
15
-	spinlock_t response_lock;
16
-	/* backlog list lock */
17
-	spinlock_t backlog_lock;
18
-
19
-	/* request submitted to chip, in progress */
20
-	struct list_head response_head;
21
-	/* hw queue full, hold in backlog list */
22
-	struct list_head backlog_head;
23
-
24
-	/* doorbell address */
25
-	u8 __iomem *dbell_csr_addr;
26
-	/* base address of the queue */
27
-	u8 *head;
40
+	spinlock_t cmd_qlock;
41
+	spinlock_t resp_qlock;
42
+	spinlock_t backlog_qlock;
2843 
2944 	struct nitrox_device *ndev;
30
-	/* flush pending backlog commands */
45
+	struct list_head response_head;
46
+	struct list_head backlog_head;
47
+
48
+	u8 __iomem *dbell_csr_addr;
49
+	u8 __iomem *compl_cnt_csr_addr;
50
+	u8 *base;
51
+	dma_addr_t dma;
52
+
3153 	struct work_struct backlog_qflush;
3254 
33
-	/* requests posted waiting for completion */
3455 	atomic_t pending_count;
35
-	/* requests in backlog queues */
3656 	atomic_t backlog_count;
3757 
3858 	int write_idx;
39
-	/* command size 32B/64B */
4059 	u8 instr_size;
4160 	u8 qno;
4261 	u32 qsize;
4362 
44
-	/* unaligned addresses */
45
-	u8 *head_unaligned;
46
-	dma_addr_t dma_unaligned;
47
-	/* dma address of the base */
48
-	dma_addr_t dma;
63
+	u8 *unalign_base;
64
+	dma_addr_t unalign_dma;
4965 };
5066 
67
+/**
68
+ * struct nitrox_hw - NITROX hardware information
69
+ * @partname: partname ex: CNN55xxx-xxx
70
+ * @fw_name: firmware version
71
+ * @freq: NITROX frequency
72
+ * @vendor_id: vendor ID
73
+ * @device_id: device ID
74
+ * @revision_id: revision ID
75
+ * @se_cores: number of symmetric cores
76
+ * @ae_cores: number of asymmetric cores
77
+ * @zip_cores: number of zip cores
78
+ */
5179 struct nitrox_hw {
52
-	/* firmware version */
53
-	char fw_name[VERSION_LEN];
80
+	char partname[IFNAMSIZ * 2];
81
+	char fw_name[CNN55XX_MAX_UCD_BLOCKS][VERSION_LEN];
5482 
83
+	int freq;
5584 	u16 vendor_id;
5685 	u16 device_id;
5786 	u8 revision_id;
5887 
59
-	/* CNN55XX cores */
6088 	u8 se_cores;
6189 	u8 ae_cores;
6290 	u8 zip_cores;
6391 };
6492 
65
-#define MAX_MSIX_VECTOR_NAME	20
93
+struct nitrox_stats {
94
+	atomic64_t posted;
95
+	atomic64_t completed;
96
+	atomic64_t dropped;
97
+};
98
+
99
+#define IRQ_NAMESZ	32
100
+
101
+struct nitrox_q_vector {
102
+	char name[IRQ_NAMESZ];
103
+	bool valid;
104
+	int ring;
105
+	struct tasklet_struct resp_tasklet;
106
+	union {
107
+		struct nitrox_cmdq *cmdq;
108
+		struct nitrox_device *ndev;
109
+	};
110
+};
111
+
112
+enum mcode_type {
113
+	MCODE_TYPE_INVALID,
114
+	MCODE_TYPE_AE,
115
+	MCODE_TYPE_SE_SSL,
116
+	MCODE_TYPE_SE_IPSEC,
117
+};
118
+
66119 /**
67
- * vectors for queues (64 AE, 64 SE and 64 ZIP) and
68
- * error condition/mailbox.
120
+ * mbox_msg - Mailbox message data
121
+ * @type: message type
122
+ * @opcode: message opcode
123
+ * @data: message data
69124  */
70
-#define MAX_MSIX_VECTORS	192
71
-
72
-struct nitrox_msix {
73
-	struct msix_entry *entries;
74
-	char **names;
75
-	DECLARE_BITMAP(irqs, MAX_MSIX_VECTORS);
76
-	u32 nr_entries;
125
+union mbox_msg {
126
+	u64 value;
127
+	struct {
128
+		u64 type: 2;
129
+		u64 opcode: 6;
130
+		u64 data: 58;
131
+	};
132
+	struct {
133
+		u64 type: 2;
134
+		u64 opcode: 6;
135
+		u64 chipid: 8;
136
+		u64 vfid: 8;
137
+	} id;
138
+	struct {
139
+		u64 type: 2;
140
+		u64 opcode: 6;
141
+		u64 count: 4;
142
+		u64 info: 40;
143
+		u64 next_se_grp: 3;
144
+		u64 next_ae_grp: 3;
145
+	} mcode_info;
77146 };
78147 
79
-struct bh_data {
80
-	/* slc port completion count address */
81
-	u8 __iomem *completion_cnt_csr_addr;
82
-
83
-	struct nitrox_cmdq *cmdq;
84
-	struct tasklet_struct resp_handler;
148
+/**
149
+ * nitrox_vfdev - NITROX VF device instance in PF
150
+ * @state: VF device state
151
+ * @vfno: VF number
152
+ * @nr_queues: number of queues enabled in VF
153
+ * @ring: ring to communicate with VF
154
+ * @msg: Mailbox message data from VF
155
+ * @mbx_resp: Mailbox counters
156
+ */
157
+struct nitrox_vfdev {
158
+	atomic_t state;
159
+	int vfno;
160
+	int nr_queues;
161
+	int ring;
162
+	union mbox_msg msg;
163
+	atomic64_t mbx_resp;
85164 };
86165 
87
-struct nitrox_bh {
88
-	struct bh_data *slc;
166
+/**
167
+ * struct nitrox_iov - SR-IOV information
168
+ * @num_vfs: number of VF(s) enabled
169
+ * @max_vf_queues: Maximum number of queues allowed for VF
170
+ * @vfdev: VF(s) devices
171
+ * @pf2vf_wq: workqueue for PF2VF communication
172
+ * @msix: MSI-X entry for PF in SR-IOV case
173
+ */
174
+struct nitrox_iov {
175
+	int num_vfs;
176
+	int max_vf_queues;
177
+	struct nitrox_vfdev *vfdev;
178
+	struct workqueue_struct *pf2vf_wq;
179
+	struct msix_entry msix;
89180 };
90181 
91
-/* NITROX-V driver state */
92
-#define NITROX_UCODE_LOADED	0
93
-#define NITROX_READY		1
182
+/*
183
+ * NITROX Device states
184
+ */
185
+enum ndev_state {
186
+	__NDEV_NOT_READY,
187
+	__NDEV_READY,
188
+	__NDEV_IN_RESET,
189
+};
190
+
191
+/* NITROX support modes for VF(s) */
192
+enum vf_mode {
193
+	__NDEV_MODE_PF,
194
+	__NDEV_MODE_VF16,
195
+	__NDEV_MODE_VF32,
196
+	__NDEV_MODE_VF64,
197
+	__NDEV_MODE_VF128,
198
+};
199
+
200
+#define __NDEV_SRIOV_BIT 0
94201 
95202 /* command queue size */
96203 #define DEFAULT_CMD_QLEN 2048
....@@ -98,7 +205,6 @@
98205 #define CMD_TIMEOUT 2000
99206 
100207 #define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev))
101
-#define PF_MODE 0
102208 
103209 #define NITROX_CSR_ADDR(ndev, offset) \
104210 	((ndev)->bar_addr + (offset))
....@@ -108,17 +214,22 @@
108214  * @list: pointer to linked list of devices
109215  * @bar_addr: iomap address
110216  * @pdev: PCI device information
111
- * @status: NITROX status
217
+ * @state: NITROX device state
218
+ * @flags: flags to indicate device the features
112219  * @timeout: Request timeout in jiffies
113220  * @refcnt: Device usage count
114221  * @idx: device index (0..N)
115222  * @node: NUMA node id attached
116223  * @qlen: Command queue length
117224  * @nr_queues: Number of command queues
225
+ * @mode: Device mode PF/VF
118226  * @ctx_pool: DMA pool for crypto context
119
- * @pkt_cmdqs: SE Command queues
120
- * @msix: MSI-X information
121
- * @bh: post processing work
227
+ * @pkt_inq: Packet input rings
228
+ * @aqmq: AQM command queues
229
+ * @qvec: MSI-X queue vectors information
230
+ * @iov: SR-IOV informatin
231
+ * @num_vecs: number of MSI-X vectors
232
+ * @stats: request statistics
122233  * @hw: hardware information
123234  * @debugfs_dir: debugfs directory
124235  */
....@@ -128,7 +239,8 @@
128239 	u8 __iomem *bar_addr;
129240 	struct pci_dev *pdev;
130241 
131
-	unsigned long status;
242
+	atomic_t state;
243
+	unsigned long flags;
132244 	unsigned long timeout;
133245 	refcount_t refcnt;
134246 
....@@ -136,13 +248,17 @@
136248 	int node;
137249 	u16 qlen;
138250 	u16 nr_queues;
251
+	enum vf_mode mode;
139252 
140253 	struct dma_pool *ctx_pool;
141
-	struct nitrox_cmdq *pkt_cmdqs;
254
+	struct nitrox_cmdq *pkt_inq;
255
+	struct nitrox_cmdq *aqmq[MAX_DEV_QUEUES] ____cacheline_aligned_in_smp;
142256 
143
-	struct nitrox_msix msix;
144
-	struct nitrox_bh bh;
257
+	struct nitrox_q_vector *qvec;
258
+	struct nitrox_iov iov;
259
+	int num_vecs;
145260 
261
+	struct nitrox_stats stats;
146262 	struct nitrox_hw hw;
147263 #if IS_ENABLED(CONFIG_DEBUG_FS)
148264 	struct dentry *debugfs_dir;
....@@ -173,9 +289,14 @@
173289 	writeq(value, (ndev->bar_addr + offset));
174290 }
175291 
176
-static inline int nitrox_ready(struct nitrox_device *ndev)
292
+static inline bool nitrox_ready(struct nitrox_device *ndev)
177293 {
178
-	return test_bit(NITROX_READY, &ndev->status);
294
+	return atomic_read(&ndev->state) == __NDEV_READY;
295
+}
296
+
297
+static inline bool nitrox_vfdev_ready(struct nitrox_vfdev *vfdev)
298
+{
299
+	return atomic_read(&vfdev->state) == __NDEV_READY;
179300 }
180301 
181302 #endif /* __NITROX_DEV_H */