~hc/RK356X_SDK_RELEASE.git

..	..	@@ -44,6 +44,11 @@
44	44	spi3 = &spi3;
45	45	spi4 = &spi4;
46	46	spi5 = &sfc;
	47	+ gpio0 = &gpio0;
	48	+ gpio1 = &gpio1;
	49	+ gpio2 = &gpio2;
	50	+ gpio3 = &gpio3;
	51	+ gpio4 = &gpio4;
47	52	};
48	53
49	54	cpus {
..	..	@@ -253,6 +258,8 @@
253	258	resets = <&cru SRST_A_USB3OTG0>;
254	259	reset-names = "usb3-otg";
255	260	dr_mode = "otg";
	261	+ phys = <&u2phy0_otg>;
	262	+ phy-names = "usb2-phy";
256	263	phy_type = "utmi_wide";
257	264	snps,dis_enblslpm_quirk;
258	265	snps,dis-u1-entry-quirk;
..	..	@@ -270,6 +277,8 @@
270	277	interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
271	278	clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
272	279	clock-names = "usbhost", "arbiter";
	280	+ phys = <&u2phy2_host>;
	281	+ phy-names = "usb2-phy";
273	282	power-domains = <&power RK3588_PD_USB>;
274	283	status = "disabled";
275	284	};
..	..	@@ -280,6 +289,8 @@
280	289	interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
281	290	clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
282	291	clock-names = "usbhost", "arbiter";
	292	+ phys = <&u2phy2_host>;
	293	+ phy-names = "usb2-phy";
283	294	power-domains = <&power RK3588_PD_USB>;
284	295	status = "disabled";
285	296	};
..	..	@@ -290,6 +301,8 @@
290	301	interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
291	302	clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
292	303	clock-names = "usbhost", "arbiter";
	304	+ phys = <&u2phy3_host>;
	305	+ phy-names = "usb2-phy";
293	306	power-domains = <&power RK3588_PD_USB>;
294	307	status = "disabled";
295	308	};
..	..	@@ -300,6 +313,8 @@
300	313	interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
301	314	clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
302	315	clock-names = "usbhost", "arbiter";
	316	+ phys = <&u2phy3_host>;
	317	+ phy-names = "usb2-phy";
303	318	power-domains = <&power RK3588_PD_USB>;
304	319	status = "disabled";
305	320	};
..	..	@@ -406,6 +421,8 @@
406	421	compatible = "rockchip,rk3588-usb2phy";
407	422	reg = <0x0 0x10>;
408	423	interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
	424	+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
	425	+ reset-names = "phy", "apb";
409	426	clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
410	427	clock-names = "phyclk";
411	428	#clock-cells = <0>;
..	..	@@ -429,6 +446,8 @@
429	446	compatible = "rockchip,rk3588-usb2phy";
430	447	reg = <0x8000 0x10>;
431	448	interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
	449	+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
	450	+ reset-names = "phy", "apb";
432	451	clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
433	452	clock-names = "phyclk";
434	453	#clock-cells = <0>;
..	..	@@ -452,6 +471,8 @@
452	471	compatible = "rockchip,rk3588-usb2phy";
453	472	reg = <0xc000 0x10>;
454	473	interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
	474	+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
	475	+ reset-names = "phy", "apb";
455	476	clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
456	477	clock-names = "phyclk";
457	478	#clock-cells = <0>;