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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/sound/pci/hda/hda_tegra.c
....@@ -1,19 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  *
34  * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms and conditions of the GNU General Public License,
7
- * version 2, as published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
14
- * You should have received a copy of the GNU General Public License
15
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16
- *
175  */
186 
197 #include <linux/clk.h>
....@@ -29,13 +17,16 @@
2917 #include <linux/moduleparam.h>
3018 #include <linux/mutex.h>
3119 #include <linux/of_device.h>
20
+#include <linux/reset.h>
3221 #include <linux/slab.h>
3322 #include <linux/time.h>
23
+#include <linux/string.h>
24
+#include <linux/pm_runtime.h>
3425 
3526 #include <sound/core.h>
3627 #include <sound/initval.h>
3728 
38
-#include "hda_codec.h"
29
+#include <sound/hda_codec.h>
3930 #include "hda_controller.h"
4031 
4132 /* Defines for Nvidia Tegra HDA support */
....@@ -62,16 +53,27 @@
6253 #define HDA_IPFS_INTR_MASK        0x188
6354 #define HDA_IPFS_EN_INTR          (1 << 16)
6455 
56
+/* FPCI */
57
+#define FPCI_DBG_CFG_2		  0x10F4
58
+#define FPCI_GCAP_NSDO_SHIFT	  18
59
+#define FPCI_GCAP_NSDO_MASK	  (0x3 << FPCI_GCAP_NSDO_SHIFT)
60
+
6561 /* max number of SDs */
6662 #define NUM_CAPTURE_SD 1
6763 #define NUM_PLAYBACK_SD 1
6864 
65
+/*
66
+ * Tegra194 does not reflect correct number of SDO lines. Below macro
67
+ * is used to update the GCAP register to workaround the issue.
68
+ */
69
+#define TEGRA194_NUM_SDO_LINES	  4
70
+
6971 struct hda_tegra {
7072 	struct azx chip;
7173 	struct device *dev;
72
-	struct clk *hda_clk;
73
-	struct clk *hda2codec_2x_clk;
74
-	struct clk *hda2hdmi_clk;
74
+	struct reset_control *reset;
75
+	struct clk_bulk_data clocks[3];
76
+	unsigned int nclocks;
7577 	void __iomem *regs;
7678 	struct work_struct probe_work;
7779 };
....@@ -85,105 +87,7 @@
8587 #define power_save	0
8688 #endif
8789 
88
-/*
89
- * DMA page allocation ops.
90
- */
91
-static int dma_alloc_pages(struct hdac_bus *bus, int type, size_t size,
92
-			   struct snd_dma_buffer *buf)
93
-{
94
-	return snd_dma_alloc_pages(type, bus->dev, size, buf);
95
-}
96
-
97
-static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
98
-{
99
-	snd_dma_free_pages(buf);
100
-}
101
-
102
-static int substream_alloc_pages(struct azx *chip,
103
-				 struct snd_pcm_substream *substream,
104
-				 size_t size)
105
-{
106
-	return snd_pcm_lib_malloc_pages(substream, size);
107
-}
108
-
109
-static int substream_free_pages(struct azx *chip,
110
-				struct snd_pcm_substream *substream)
111
-{
112
-	return snd_pcm_lib_free_pages(substream);
113
-}
114
-
115
-/*
116
- * Register access ops. Tegra HDA register access is DWORD only.
117
- */
118
-static void hda_tegra_writel(u32 value, u32 __iomem *addr)
119
-{
120
-	writel(value, addr);
121
-}
122
-
123
-static u32 hda_tegra_readl(u32 __iomem *addr)
124
-{
125
-	return readl(addr);
126
-}
127
-
128
-static void hda_tegra_writew(u16 value, u16 __iomem  *addr)
129
-{
130
-	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
131
-	void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
132
-	u32 v;
133
-
134
-	v = readl(dword_addr);
135
-	v &= ~(0xffff << shift);
136
-	v |= value << shift;
137
-	writel(v, dword_addr);
138
-}
139
-
140
-static u16 hda_tegra_readw(u16 __iomem *addr)
141
-{
142
-	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
143
-	void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
144
-	u32 v;
145
-
146
-	v = readl(dword_addr);
147
-	return (v >> shift) & 0xffff;
148
-}
149
-
150
-static void hda_tegra_writeb(u8 value, u8 __iomem *addr)
151
-{
152
-	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
153
-	void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
154
-	u32 v;
155
-
156
-	v = readl(dword_addr);
157
-	v &= ~(0xff << shift);
158
-	v |= value << shift;
159
-	writel(v, dword_addr);
160
-}
161
-
162
-static u8 hda_tegra_readb(u8 __iomem *addr)
163
-{
164
-	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
165
-	void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
166
-	u32 v;
167
-
168
-	v = readl(dword_addr);
169
-	return (v >> shift) & 0xff;
170
-}
171
-
172
-static const struct hdac_io_ops hda_tegra_io_ops = {
173
-	.reg_writel = hda_tegra_writel,
174
-	.reg_readl = hda_tegra_readl,
175
-	.reg_writew = hda_tegra_writew,
176
-	.reg_readw = hda_tegra_readw,
177
-	.reg_writeb = hda_tegra_writeb,
178
-	.reg_readb = hda_tegra_readb,
179
-	.dma_alloc_pages = dma_alloc_pages,
180
-	.dma_free_pages = dma_free_pages,
181
-};
182
-
183
-static const struct hda_controller_ops hda_tegra_ops = {
184
-	.substream_alloc_pages = substream_alloc_pages,
185
-	.substream_free_pages = substream_free_pages,
186
-};
90
+static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
18791 
18892 static void hda_tegra_init(struct hda_tegra *hda)
18993 {
....@@ -210,77 +114,92 @@
210114 	writel(v, hda->regs + HDA_IPFS_INTR_MASK);
211115 }
212116 
213
-static int hda_tegra_enable_clocks(struct hda_tegra *data)
214
-{
215
-	int rc;
216
-
217
-	rc = clk_prepare_enable(data->hda_clk);
218
-	if (rc)
219
-		return rc;
220
-	rc = clk_prepare_enable(data->hda2codec_2x_clk);
221
-	if (rc)
222
-		goto disable_hda;
223
-	rc = clk_prepare_enable(data->hda2hdmi_clk);
224
-	if (rc)
225
-		goto disable_codec_2x;
226
-
227
-	return 0;
228
-
229
-disable_codec_2x:
230
-	clk_disable_unprepare(data->hda2codec_2x_clk);
231
-disable_hda:
232
-	clk_disable_unprepare(data->hda_clk);
233
-	return rc;
234
-}
235
-
236
-#ifdef CONFIG_PM_SLEEP
237
-static void hda_tegra_disable_clocks(struct hda_tegra *data)
238
-{
239
-	clk_disable_unprepare(data->hda2hdmi_clk);
240
-	clk_disable_unprepare(data->hda2codec_2x_clk);
241
-	clk_disable_unprepare(data->hda_clk);
242
-}
243
-
244117 /*
245118  * power management
246119  */
247
-static int hda_tegra_suspend(struct device *dev)
120
+static int __maybe_unused hda_tegra_suspend(struct device *dev)
248121 {
249122 	struct snd_card *card = dev_get_drvdata(dev);
250
-	struct azx *chip = card->private_data;
251
-	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
252
-	struct hdac_bus *bus = azx_bus(chip);
123
+	int rc;
253124 
125
+	rc = pm_runtime_force_suspend(dev);
126
+	if (rc < 0)
127
+		return rc;
254128 	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
255
-
256
-	azx_stop_chip(chip);
257
-	synchronize_irq(bus->irq);
258
-	azx_enter_link_reset(chip);
259
-	hda_tegra_disable_clocks(hda);
260129 
261130 	return 0;
262131 }
263132 
264
-static int hda_tegra_resume(struct device *dev)
133
+static int __maybe_unused hda_tegra_resume(struct device *dev)
265134 {
266135 	struct snd_card *card = dev_get_drvdata(dev);
267
-	struct azx *chip = card->private_data;
268
-	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
136
+	int rc;
269137 
270
-	hda_tegra_enable_clocks(hda);
271
-
272
-	hda_tegra_init(hda);
273
-
274
-	azx_init_chip(chip, 1);
275
-
138
+	rc = pm_runtime_force_resume(dev);
139
+	if (rc < 0)
140
+		return rc;
276141 	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
277142 
278143 	return 0;
279144 }
280
-#endif /* CONFIG_PM_SLEEP */
145
+
146
+static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev)
147
+{
148
+	struct snd_card *card = dev_get_drvdata(dev);
149
+	struct azx *chip = card->private_data;
150
+	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
151
+
152
+	if (chip && chip->running) {
153
+		/* enable controller wake up event */
154
+		azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
155
+			   STATESTS_INT_MASK);
156
+
157
+		azx_stop_chip(chip);
158
+		azx_enter_link_reset(chip);
159
+	}
160
+	clk_bulk_disable_unprepare(hda->nclocks, hda->clocks);
161
+
162
+	return 0;
163
+}
164
+
165
+static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)
166
+{
167
+	struct snd_card *card = dev_get_drvdata(dev);
168
+	struct azx *chip = card->private_data;
169
+	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
170
+	int rc;
171
+
172
+	if (!chip->running) {
173
+		rc = reset_control_assert(hda->reset);
174
+		if (rc)
175
+			return rc;
176
+	}
177
+
178
+	rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks);
179
+	if (rc != 0)
180
+		return rc;
181
+	if (chip && chip->running) {
182
+		hda_tegra_init(hda);
183
+		azx_init_chip(chip, 1);
184
+		/* disable controller wake up event*/
185
+		azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
186
+			   ~STATESTS_INT_MASK);
187
+	} else {
188
+		usleep_range(10, 100);
189
+
190
+		rc = reset_control_deassert(hda->reset);
191
+		if (rc)
192
+			return rc;
193
+	}
194
+
195
+	return 0;
196
+}
281197 
282198 static const struct dev_pm_ops hda_tegra_pm = {
283199 	SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
200
+	SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
201
+			   hda_tegra_runtime_resume,
202
+			   NULL)
284203 };
285204 
286205 static int hda_tegra_dev_disconnect(struct snd_device *device)
....@@ -318,23 +237,6 @@
318237 	struct hdac_bus *bus = azx_bus(chip);
319238 	struct device *dev = hda->dev;
320239 	struct resource *res;
321
-	int err;
322
-
323
-	hda->hda_clk = devm_clk_get(dev, "hda");
324
-	if (IS_ERR(hda->hda_clk)) {
325
-		dev_err(dev, "failed to get hda clock\n");
326
-		return PTR_ERR(hda->hda_clk);
327
-	}
328
-	hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
329
-	if (IS_ERR(hda->hda2codec_2x_clk)) {
330
-		dev_err(dev, "failed to get hda2codec_2x clock\n");
331
-		return PTR_ERR(hda->hda2codec_2x_clk);
332
-	}
333
-	hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
334
-	if (IS_ERR(hda->hda2hdmi_clk)) {
335
-		dev_err(dev, "failed to get hda2hdmi clock\n");
336
-		return PTR_ERR(hda->hda2hdmi_clk);
337
-	}
338240 
339241 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
340242 	hda->regs = devm_ioremap_resource(dev, res);
....@@ -344,12 +246,6 @@
344246 	bus->remap_addr = hda->regs + HDA_BAR0;
345247 	bus->addr = res->start + HDA_BAR0;
346248 
347
-	err = hda_tegra_enable_clocks(hda);
348
-	if (err) {
349
-		dev_err(dev, "failed to get enable clocks\n");
350
-		return err;
351
-	}
352
-
353249 	hda_tegra_init(hda);
354250 
355251 	return 0;
....@@ -357,11 +253,14 @@
357253 
358254 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
359255 {
256
+	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
360257 	struct hdac_bus *bus = azx_bus(chip);
361258 	struct snd_card *card = chip->card;
362259 	int err;
363260 	unsigned short gcap;
364261 	int irq_id = platform_get_irq(pdev, 0);
262
+	const char *sname, *drv_name = "tegra-hda";
263
+	struct device_node *np = pdev->dev.of_node;
365264 
366265 	if (irq_id < 0)
367266 		return irq_id;
....@@ -379,11 +278,33 @@
379278 		return err;
380279 	}
381280 	bus->irq = irq_id;
281
+	bus->dma_stop_delay = 100;
282
+	card->sync_irq = bus->irq;
382283 
383
-	synchronize_irq(bus->irq);
284
+	/*
285
+	 * Tegra194 has 4 SDO lines and the STRIPE can be used to
286
+	 * indicate how many of the SDO lines the stream should be
287
+	 * striped. But GCAP register does not reflect the true
288
+	 * capability of HW. Below workaround helps to fix this.
289
+	 *
290
+	 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2,
291
+	 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines.
292
+	 */
293
+	if (of_device_is_compatible(np, "nvidia,tegra194-hda")) {
294
+		u32 val;
295
+
296
+		dev_info(card->dev, "Override SDO lines to %u\n",
297
+			 TEGRA194_NUM_SDO_LINES);
298
+
299
+		val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK;
300
+		val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT;
301
+		writel(val, hda->regs + FPCI_DBG_CFG_2);
302
+	}
384303 
385304 	gcap = azx_readw(chip, GCAP);
386305 	dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
306
+
307
+	chip->align_buffer_size = 1;
387308 
388309 	/* read number of streams from GCAP register instead of using
389310 	 * hardcoded value
....@@ -416,14 +337,40 @@
416337 	/* initialize chip */
417338 	azx_init_chip(chip, 1);
418339 
340
+	/*
341
+	 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with
342
+	 * 4 SDO lines due to legacy design limitation. Following
343
+	 * is, from HD Audio Specification (Revision 1.0a), used to
344
+	 * control striping of the stream across multiple SDO lines
345
+	 * for sample rates <= 48K.
346
+	 *
347
+	 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
348
+	 *
349
+	 * Due to legacy design issue it is recommended that above
350
+	 * ratio must be greater than 8. Since number of SDO lines is
351
+	 * in powers of 2, next available ratio is 16 which can be
352
+	 * used as a limiting factor here.
353
+	 */
354
+	if (of_device_is_compatible(np, "nvidia,tegra30-hda"))
355
+		chip->bus.core.sdo_limit = 16;
356
+
419357 	/* codec detection */
420358 	if (!bus->codec_mask) {
421359 		dev_err(card->dev, "no codecs found!\n");
422360 		return -ENODEV;
423361 	}
424362 
425
-	strcpy(card->driver, "tegra-hda");
426
-	strcpy(card->shortname, "tegra-hda");
363
+	/* driver name */
364
+	strncpy(card->driver, drv_name, sizeof(card->driver));
365
+	/* shortname for card */
366
+	sname = of_get_property(np, "nvidia,model", NULL);
367
+	if (!sname)
368
+		sname = drv_name;
369
+	if (strlen(sname) > sizeof(card->shortname))
370
+		dev_info(card->dev, "truncating shortname for card\n");
371
+	strncpy(card->shortname, sname, sizeof(card->shortname));
372
+
373
+	/* longname for card */
427374 	snprintf(card->longname, sizeof(card->longname),
428375 		 "%s at 0x%lx irq %i",
429376 		 card->shortname, bus->addr, bus->irq);
....@@ -441,7 +388,7 @@
441388 			    unsigned int driver_caps,
442389 			    struct hda_tegra *hda)
443390 {
444
-	static struct snd_device_ops ops = {
391
+	static const struct snd_device_ops ops = {
445392 		.dev_disconnect = hda_tegra_dev_disconnect,
446393 		.dev_free = hda_tegra_dev_free,
447394 	};
....@@ -465,11 +412,13 @@
465412 
466413 	INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
467414 
468
-	err = azx_bus_init(chip, NULL, &hda_tegra_io_ops);
415
+	err = azx_bus_init(chip, NULL);
469416 	if (err < 0)
470417 		return err;
471418 
472
-	chip->bus.needs_damn_long_delay = 1;
419
+	chip->bus.core.sync_write = 0;
420
+	chip->bus.core.needs_damn_long_delay = 1;
421
+	chip->bus.core.aligned_mmio = 1;
473422 
474423 	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
475424 	if (err < 0) {
....@@ -482,13 +431,16 @@
482431 
483432 static const struct of_device_id hda_tegra_match[] = {
484433 	{ .compatible = "nvidia,tegra30-hda" },
434
+	{ .compatible = "nvidia,tegra194-hda" },
485435 	{},
486436 };
487437 MODULE_DEVICE_TABLE(of, hda_tegra_match);
488438 
489439 static int hda_tegra_probe(struct platform_device *pdev)
490440 {
491
-	const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR;
441
+	const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
442
+					  AZX_DCAPS_PM_RUNTIME |
443
+					  AZX_DCAPS_4K_BDLE_BOUNDARY;
492444 	struct snd_card *card;
493445 	struct azx *chip;
494446 	struct hda_tegra *hda;
....@@ -507,12 +459,31 @@
507459 		return err;
508460 	}
509461 
462
+	hda->reset = devm_reset_control_array_get_exclusive(&pdev->dev);
463
+	if (IS_ERR(hda->reset)) {
464
+		err = PTR_ERR(hda->reset);
465
+		goto out_free;
466
+	}
467
+
468
+	hda->clocks[hda->nclocks++].id = "hda";
469
+	hda->clocks[hda->nclocks++].id = "hda2hdmi";
470
+	hda->clocks[hda->nclocks++].id = "hda2codec_2x";
471
+
472
+	err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks);
473
+	if (err < 0)
474
+		goto out_free;
475
+
510476 	err = hda_tegra_create(card, driver_flags, hda);
511477 	if (err < 0)
512478 		goto out_free;
513479 	card->private_data = chip;
514480 
515481 	dev_set_drvdata(&pdev->dev, card);
482
+
483
+	pm_runtime_enable(hda->dev);
484
+	if (!azx_has_pm_runtime(chip))
485
+		pm_runtime_forbid(hda->dev);
486
+
516487 	schedule_work(&hda->probe_work);
517488 
518489 	return 0;
....@@ -529,12 +500,13 @@
529500 	struct platform_device *pdev = to_platform_device(hda->dev);
530501 	int err;
531502 
503
+	pm_runtime_get_sync(hda->dev);
532504 	err = hda_tegra_first_init(chip, pdev);
533505 	if (err < 0)
534506 		goto out_free;
535507 
536508 	/* create codec instances */
537
-	err = azx_probe_codecs(chip, 0);
509
+	err = azx_probe_codecs(chip, 8);
538510 	if (err < 0)
539511 		goto out_free;
540512 
....@@ -550,12 +522,18 @@
550522 	snd_hda_set_power_save(&chip->bus, power_save * 1000);
551523 
552524  out_free:
525
+	pm_runtime_put(hda->dev);
553526 	return; /* no error return from async probe */
554527 }
555528 
556529 static int hda_tegra_remove(struct platform_device *pdev)
557530 {
558
-	return snd_card_free(dev_get_drvdata(&pdev->dev));
531
+	int ret;
532
+
533
+	ret = snd_card_free(dev_get_drvdata(&pdev->dev));
534
+	pm_runtime_disable(&pdev->dev);
535
+
536
+	return ret;
559537 }
560538 
561539 static void hda_tegra_shutdown(struct platform_device *pdev)