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| 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. |
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| 3 | 4 | * |
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| .. | .. |
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| 6 | 7 | * |
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| 7 | 8 | * Description: |
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| 8 | 9 | * Internal header file for UCC SLOW unit routines. |
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| 9 | | - * |
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| 10 | | - * This program is free software; you can redistribute it and/or modify it |
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| 11 | | - * under the terms of the GNU General Public License as published by the |
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| 12 | | - * Free Software Foundation; either version 2 of the License, or (at your |
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| 13 | | - * option) any later version. |
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| 14 | 10 | */ |
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| 15 | 11 | #ifndef __UCC_SLOW_H__ |
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| 16 | 12 | #define __UCC_SLOW_H__ |
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| .. | .. |
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| 188 | 184 | struct ucc_slow_private { |
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| 189 | 185 | struct ucc_slow_info *us_info; |
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| 190 | 186 | struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */ |
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| 191 | | - struct ucc_slow_pram *us_pram; /* a pointer to the parameter RAM */ |
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| 192 | | - u32 us_pram_offset; |
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| 187 | + struct ucc_slow_pram __iomem *us_pram; /* a pointer to the parameter RAM */ |
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| 188 | + s32 us_pram_offset; |
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| 193 | 189 | int enabled_tx; /* Whether channel is enabled for Tx (ENT) */ |
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| 194 | 190 | int enabled_rx; /* Whether channel is enabled for Rx (ENR) */ |
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| 195 | 191 | int stopped_tx; /* Whether channel has been stopped for Tx |
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| .. | .. |
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| 198 | 194 | struct list_head confQ; /* frames passed to chip waiting for tx */ |
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| 199 | 195 | u32 first_tx_bd_mask; /* mask is used in Tx routine to save status |
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| 200 | 196 | and length for first BD in a frame */ |
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| 201 | | - u32 tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */ |
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| 202 | | - u32 rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */ |
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| 203 | | - struct qe_bd *confBd; /* next BD for confirm after Tx */ |
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| 204 | | - struct qe_bd *tx_bd; /* next BD for new Tx request */ |
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| 205 | | - struct qe_bd *rx_bd; /* next BD to collect after Rx */ |
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| 197 | + s32 tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */ |
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| 198 | + s32 rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */ |
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| 199 | + struct qe_bd __iomem *confBd; /* next BD for confirm after Tx */ |
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| 200 | + struct qe_bd __iomem *tx_bd; /* next BD for new Tx request */ |
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| 201 | + struct qe_bd __iomem *rx_bd; /* next BD to collect after Rx */ |
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| 206 | 202 | void *p_rx_frame; /* accumulating receive frame */ |
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| 207 | | - u16 *p_ucce; /* a pointer to the event register in memory. |
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| 208 | | - */ |
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| 209 | | - u16 *p_uccm; /* a pointer to the mask register in memory */ |
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| 203 | + __be16 __iomem *p_ucce; /* a pointer to the event register in memory */ |
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| 204 | + __be16 __iomem *p_uccm; /* a pointer to the mask register in memory */ |
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| 210 | 205 | u16 saved_uccm; /* a saved mask for the RX Interrupt bits */ |
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| 211 | 206 | #ifdef STATISTICS |
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| 212 | 207 | u32 tx_frames; /* Transmitted frames counters */ |
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