write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/include/soc/arc/mcip.h
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@@ -1,11 +1,8 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...)
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  *
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  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #ifndef __SOC_ARC_MCIP_H
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@@ -49,7 +46,9 @@
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 #define CMD_IDU_ENABLE			0x71
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 #define CMD_IDU_DISABLE			0x72
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 #define CMD_IDU_SET_MODE		0x74
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+#define CMD_IDU_READ_MODE		0x75
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 #define CMD_IDU_SET_DEST		0x76
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+#define CMD_IDU_ACK_CIRQ		0x79
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 #define CMD_IDU_SET_MASK		0x7C
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 #define IDU_M_TRIG_LEVEL		0x0
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@@ -122,4 +121,13 @@
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 	__mcip_cmd(cmd, param);
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 }
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+/*
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+ * Read MCIP register
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+ */
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+static inline unsigned int __mcip_cmd_read(unsigned int cmd, unsigned int param)
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+{
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+	__mcip_cmd(cmd, param);
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+	return read_aux_reg(ARC_REG_MCIP_READBACK);
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+}
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+
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 #endif