write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/include/linux/rtsx_pci.h
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..
@@ -1,19 +1,7 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 /* Driver for Realtek PCI-Express card reader
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  *
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  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License as published by the
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- * Free Software Foundation; either version 2, or (at your option) any
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- * later version.
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- *
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- * This program is distributed in the hope that it will be useful, but
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- * WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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- * General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License along
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- * with this program; if not, see <http://www.gnu.org/licenses/>.
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  *
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  * Author:
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  *   Wei WANG <wei_wang@realsil.com.cn>
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@@ -110,18 +98,6 @@
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 	iowrite8(value, (pcr)->remap_addr + reg)
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 #define rtsx_pci_readb(pcr, reg) \
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 	ioread8((pcr)->remap_addr + reg)
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-
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-#define rtsx_pci_read_config_byte(pcr, where, val) \
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-	pci_read_config_byte((pcr)->pci, where, val)
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-
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-#define rtsx_pci_write_config_byte(pcr, where, val) \
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-	pci_write_config_byte((pcr)->pci, where, val)
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-
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-#define rtsx_pci_read_config_dword(pcr, where, val) \
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-	pci_read_config_dword((pcr)->pci, where, val)
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-
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-#define rtsx_pci_write_config_dword(pcr, where, val) \
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-	pci_write_config_dword((pcr)->pci, where, val)
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 #define STATE_TRANS_NONE		0
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 #define STATE_TRANS_CMD			1
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@@ -317,6 +293,8 @@
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 #define   SD30_CLK_STOP_CFG0		0x01
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 #define REG_PRE_RW_MODE			0xFD70
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 #define EN_INFINITE_MODE		0x01
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+#define REG_CRC_DUMMY_0		0xFD71
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+#define CFG_SD_POW_AUTO_PD		(1<<0)
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 #define SRCTL				0xFC13
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@@ -611,6 +589,7 @@
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 #define ASPM_FORCE_CTL			0xFE57
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 #define   FORCE_ASPM_CTL0		0x10
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+#define   FORCE_ASPM_CTL1		0x20
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 #define   FORCE_ASPM_VAL_MASK		0x03
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 #define   FORCE_ASPM_L1_EN		0x02
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 #define   FORCE_ASPM_L0_EN		0x01
..
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@@ -678,6 +657,11 @@
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 #define   RESET_PIN_WAKE		0x02
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 #define   PM_WAKE_EN			0x01
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 #define PM_CTRL4			0xFF47
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+
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+#define REG_CFG_OOBS_OFF_TIMER 0xFEA6
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+#define REG_CFG_OOBS_ON_TIMER 0xFEA7
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+#define REG_CFG_VCM_ON_TIMER 0xFEA8
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+#define REG_CFG_OOBS_POLLING 0xFEA9
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 /* Memory mapping */
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 #define SRAM_BASE			0xE600
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@@ -1053,10 +1037,6 @@
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 #define   PHY_DIG1E_RX_EN_KEEP		0x0001
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 #define PHY_DUM_REG			0x1F
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-#define PCR_ASPM_SETTING_REG1		0x160
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-#define PCR_ASPM_SETTING_REG2		0x168
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-#define PCR_ASPM_SETTING_5260		0x178
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-
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 #define PCR_SETTING_REG1		0x724
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 #define PCR_SETTING_REG2		0x814
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 #define PCR_SETTING_REG3		0x747
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@@ -1092,11 +1072,7 @@
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 	void		(*stop_cmd)(struct rtsx_pcr *pcr);
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 	void (*set_aspm)(struct rtsx_pcr *pcr, bool enable);
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-	int (*set_ltr_latency)(struct rtsx_pcr *pcr, u32 latency);
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-	int (*set_l1off_sub)(struct rtsx_pcr *pcr, u8 val);
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 	void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active);
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-	void (*full_on)(struct rtsx_pcr *pcr);
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-	void (*power_saving)(struct rtsx_pcr *pcr);
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 	void (*enable_ocp)(struct rtsx_pcr *pcr);
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 	void (*disable_ocp)(struct rtsx_pcr *pcr);
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 	void (*init_ocp)(struct rtsx_pcr *pcr);
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@@ -1107,11 +1083,6 @@
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 enum PDEV_STAT  {PDEV_STAT_IDLE, PDEV_STAT_RUN};
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-#define ASPM_L1_1_EN_MASK		BIT(3)
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-#define ASPM_L1_2_EN_MASK		BIT(2)
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-#define PM_L1_1_EN_MASK		BIT(1)
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-#define PM_L1_2_EN_MASK		BIT(0)
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-
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 #define ASPM_L1_1_EN			BIT(0)
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 #define ASPM_L1_2_EN			BIT(1)
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 #define PM_L1_1_EN				BIT(2)
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@@ -1119,13 +1090,6 @@
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 #define LTR_L1SS_PWR_GATE_EN	BIT(4)
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 #define L1_SNOOZE_TEST_EN		BIT(5)
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 #define LTR_L1SS_PWR_GATE_CHECK_CARD_EN	BIT(6)
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-
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-enum dev_aspm_mode {
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-	DEV_ASPM_DYNAMIC,
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-	DEV_ASPM_BACKDOOR,
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-	DEV_ASPM_STATIC,
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-	DEV_ASPM_DISABLE,
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-};
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 /*
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  * struct rtsx_cr_option  - card reader option
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@@ -1137,7 +1101,6 @@
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  * @ltr_active_latency: ltr mode active latency
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  * @ltr_idle_latency: ltr mode idle latency
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  * @ltr_l1off_latency: ltr mode l1off latency
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- * @dev_aspm_mode: device aspm mode
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  * @l1_snooze_delay: l1 snooze delay
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  * @ltr_l1off_sspwrgate: ltr l1off sspwrgate
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  * @ltr_l1off_snooze_sspwrgate: ltr l1off snooze sspwrgate
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@@ -1154,7 +1117,6 @@
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 	u32 ltr_active_latency;
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 	u32 ltr_idle_latency;
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 	u32 ltr_l1off_latency;
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-	enum dev_aspm_mode dev_aspm_mode;
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 	u32 l1_snooze_delay;
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 	u8 ltr_l1off_sspwrgate;
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 	u8 ltr_l1off_snooze_sspwrgate;
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@@ -1183,7 +1145,6 @@
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 struct rtsx_pcr {
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 	struct pci_dev			*pci;
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 	unsigned int			id;
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-	int				pcie_cap;
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 	struct rtsx_cr_option	option;
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 	struct rtsx_hw_param hw_param;
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@@ -1229,6 +1190,7 @@
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 #define EXTRA_CAPS_MMC_HSDDR		(1 << 3)
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 #define EXTRA_CAPS_MMC_HS200		(1 << 4)
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 #define EXTRA_CAPS_MMC_8BIT		(1 << 5)
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+#define EXTRA_CAPS_NO_MMC		(1 << 7)
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 	u32				extra_caps;
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 #define IC_VER_A			0
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@@ -1267,6 +1229,7 @@
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 	u8				dma_error_count;
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 	u8			ocp_stat;
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 	u8			ocp_stat2;
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+	u8			rtd3_en;
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 };
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1234
 
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 #define PID_524A	0x524A
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@@ -1274,6 +1237,8 @@
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 #define PID_5250	0x5250
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 #define PID_525A	0x525A
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 #define PID_5260	0x5260
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+#define PID_5261	0x5261
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+#define PID_5228	0x5228
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 #define CHK_PCI_PID(pcr, pid)		((pcr)->pci->device == (pid))
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 #define PCI_VID(pcr)			((pcr)->pci->vendor)
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@@ -1329,18 +1294,6 @@
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 static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
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 {
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 	return (u8 *)(pcr->host_cmds_ptr);
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-}
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-
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-static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr,
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-		u8 mask, u8 append)
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-{
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-	int err;
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-	u8 val;
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-
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-	err = pci_read_config_byte(pcr->pci, addr, &val);
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-	if (err < 0)
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-		return err;
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-	return pci_write_config_byte(pcr->pci, addr, (val & mask) | append);
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 }
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 static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)