| .. | .. | 
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| 222 | 222 | struct mcinfo_global *mc_global; | 
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| 223 | 223 | struct mcinfo_bank *mc_bank; | 
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| 224 | 224 | struct xen_mce m; | 
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| 225 |  | -	uint32_t i; | 
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|  | 225 | +	unsigned int i, j; | 
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| 226 | 226 |  | 
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| 227 | 227 | mic = NULL; | 
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| 228 | 228 | x86_mcinfo_lookup(&mic, mi, MC_TYPE_GLOBAL); | 
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| .. | .. | 
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| 248 | 248 | m.socketid = g_physinfo[i].mc_chipid; | 
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| 249 | 249 | m.cpu = m.extcpu = g_physinfo[i].mc_cpunr; | 
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| 250 | 250 | m.cpuvendor = (__u8)g_physinfo[i].mc_vendor; | 
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| 251 |  | -	m.mcgcap = g_physinfo[i].mc_msrvalues[__MC_MSR_MCGCAP].value; | 
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|  | 251 | +	for (j = 0; j < g_physinfo[i].mc_nmsrvals; ++j) | 
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|  | 252 | +		switch (g_physinfo[i].mc_msrvalues[j].reg) { | 
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|  | 253 | +		case MSR_IA32_MCG_CAP: | 
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|  | 254 | +			m.mcgcap = g_physinfo[i].mc_msrvalues[j].value; | 
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|  | 255 | +			break; | 
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|  | 256 | + | 
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|  | 257 | +		case MSR_PPIN: | 
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|  | 258 | +		case MSR_AMD_PPIN: | 
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|  | 259 | +			m.ppin = g_physinfo[i].mc_msrvalues[j].value; | 
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|  | 260 | +			break; | 
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|  | 261 | +		} | 
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| 252 | 262 |  | 
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| 253 | 263 | mic = NULL; | 
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| 254 | 264 | x86_mcinfo_lookup(&mic, mi, MC_TYPE_BANK); | 
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