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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/watchdog/sp5100_tco.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  *	sp5100_tco :	TCO timer driver for sp5100 chipsets
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  *
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@@ -6,12 +7,7 @@
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  *	Based on i8xx_tco.c:
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  *	(c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
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  *	Reserved.
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- *				http://www.kernelconcepts.de
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- *
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- *	This program is free software; you can redistribute it and/or
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- *	modify it under the terms of the GNU General Public License
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- *	as published by the Free Software Foundation; either version
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- *	2 of the License, or (at your option) any later version.
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+ *				https://www.kernelconcepts.de
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  *
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  *	See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
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  *	    AMD Publication 45482 "AMD SB800-Series Southbridges Register
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@@ -21,6 +17,12 @@
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  *	    AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
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  *	    AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
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  *				for AMD Family 16h Models 30h-3Fh Processors"
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+ *	    AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR)
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+ *				for AMD Family 17h Model 18h, Revision B1
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+ *				Processors (PUB)
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+ *	    AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR)
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+ *				for AMD Family 17h Model 20h, Revision A1
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+ *				Processors (PUB)
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  */
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 /*
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@@ -100,6 +102,10 @@
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 	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
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 	val |= SP5100_WDT_START_STOP_BIT;
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+	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
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+
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+	/* This must be a distinct write. */
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+	val |= SP5100_WDT_TRIGGER_BIT;
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 	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
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 	return 0;
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@@ -245,6 +251,18 @@
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 		break;
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 	case efch:
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 		dev_name = SB800_DEVNAME;
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+		/*
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+		 * On Family 17h devices, the EFCH_PM_DECODEEN_WDT_TMREN bit of
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+		 * EFCH_PM_DECODEEN not only enables the EFCH_PM_WDT_ADDR memory
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+		 * region, it also enables the watchdog itself.
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+		 */
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+		if (boot_cpu_data.x86 == 0x17) {
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+			val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
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+			if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
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+				sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN, 0xff,
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+							  EFCH_PM_DECODEEN_WDT_TMREN);
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+			}
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+		}
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 		val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
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 		if (val & EFCH_PM_DECODEEN_WDT_TMREN)
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 			mmio_addr = EFCH_PM_WDT_ADDR;
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@@ -395,9 +413,7 @@
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 	wdd->min_timeout = 1;
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 	wdd->max_timeout = 0xffff;
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-	if (watchdog_init_timeout(wdd, heartbeat, NULL))
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-		dev_info(dev, "timeout value invalid, using %d\n",
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-			 wdd->timeout);
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+	watchdog_init_timeout(wdd, heartbeat, NULL);
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 	watchdog_set_nowayout(wdd, nowayout);
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 	watchdog_stop_on_reboot(wdd);
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 	watchdog_stop_on_unregister(wdd);
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@@ -408,10 +424,8 @@
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 		return ret;
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 	ret = devm_watchdog_register_device(dev, wdd);
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-	if (ret) {
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-		dev_err(dev, "cannot register watchdog device (err=%d)\n", ret);
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+	if (ret)
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 		return ret;
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-	}
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 	/* Show module parameters */
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 	dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",