forked from ~ljy/RK356X_SDK_RELEASE
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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/drivers/usb/host/xhci-hub.c
....@@ -449,7 +449,12 @@
449449 	    cmd->status == COMP_COMMAND_RING_STOPPED) {
450450 		xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
451451 		ret = -ETIME;
452
+		goto cmd_cleanup;
452453 	}
454
+
455
+	ret = xhci_vendor_sync_dev_ctx(xhci, slot_id);
456
+	if (ret)
457
+		xhci_warn(xhci, "Sync device context failed, ret=%d\n", ret);
453458 
454459 cmd_cleanup:
455460 	xhci_free_command(xhci, cmd);
....@@ -497,8 +502,8 @@
497502 	/* Write 1 to disable the port */
498503 	writel(port_status | PORT_PE, addr);
499504 	port_status = readl(addr);
500
-	xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
501
-			wIndex, port_status);
505
+	xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
506
+		 hcd->self.busnum, wIndex + 1, port_status);
502507 }
503508 
504509 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
....@@ -547,8 +552,9 @@
547552 	/* Change bits are all write 1 to clear */
548553 	writel(port_status | status, addr);
549554 	port_status = readl(addr);
550
-	xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
551
-			port_change_bit, wIndex, port_status);
555
+
556
+	xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
557
+		 wIndex + 1, port_change_bit, port_status);
552558 }
553559 
554560 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
....@@ -567,6 +573,7 @@
567573  */
568574 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
569575 				u16 index, bool on, unsigned long *flags)
576
+	__must_hold(&xhci->lock)
570577 {
571578 	struct xhci_hub *rhub;
572579 	struct xhci_port *port;
....@@ -575,13 +582,16 @@
575582 	rhub = xhci_get_rhub(hcd);
576583 	port = rhub->ports[index];
577584 	temp = readl(port->addr);
585
+
586
+	xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
587
+		 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp);
588
+
578589 	temp = xhci_port_state_to_neutral(temp);
590
+
579591 	if (on) {
580592 		/* Power on */
581593 		writel(temp | PORT_POWER, port->addr);
582
-		temp = readl(port->addr);
583
-		xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n",
584
-						index, temp);
594
+		readl(port->addr);
585595 	} else {
586596 		/* Power off */
587597 		writel(temp & ~PORT_POWER, port->addr);
....@@ -608,12 +618,13 @@
608618 	temp |= test_mode << PORT_TEST_MODE_SHIFT;
609619 	writel(temp, port->addr + PORTPMSC);
610620 	xhci->test_mode = test_mode;
611
-	if (test_mode == TEST_FORCE_EN)
621
+	if (test_mode == USB_TEST_FORCE_ENABLE)
612622 		xhci_start(xhci);
613623 }
614624 
615625 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
616626 				u16 test_mode, u16 wIndex, unsigned long *flags)
627
+	__must_hold(&xhci->lock)
617628 {
618629 	int i, retval;
619630 
....@@ -662,7 +673,7 @@
662673 		xhci_err(xhci, "Not in test mode, do nothing.\n");
663674 		return 0;
664675 	}
665
-	if (xhci->test_mode == TEST_FORCE_EN &&
676
+	if (xhci->test_mode == USB_TEST_FORCE_ENABLE &&
666677 		!(xhci->xhc_state & XHCI_STATE_HALTED)) {
667678 		retval = xhci_halt(xhci);
668679 		if (retval)
....@@ -670,19 +681,24 @@
670681 	}
671682 	pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
672683 	xhci->test_mode = 0;
673
-	return xhci_reset(xhci);
684
+	return xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
674685 }
675686 
676687 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
677688 			 u32 link_state)
678689 {
679690 	u32 temp;
691
+	u32 portsc;
680692 
681
-	temp = readl(port->addr);
682
-	temp = xhci_port_state_to_neutral(temp);
693
+	portsc = readl(port->addr);
694
+	temp = xhci_port_state_to_neutral(portsc);
683695 	temp &= ~PORT_PLS_MASK;
684696 	temp |= PORT_LINK_STROBE | link_state;
685697 	writel(temp, port->addr);
698
+
699
+	xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
700
+		 port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
701
+		 portsc, temp);
686702 }
687703 
688704 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
....@@ -723,13 +739,6 @@
723739 		temp |= port_bit;
724740 		writel(temp, port->addr);
725741 	}
726
-}
727
-
728
-/* Updates Link Status for USB 2.1 port */
729
-static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
730
-{
731
-	if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
732
-		*status |= USB_PORT_STAT_L1;
733742 }
734743 
735744 /* Updates Link Status for super Speed port */
....@@ -814,6 +823,101 @@
814823 	}
815824 }
816825 
826
+static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
827
+					     u32 *status, u32 portsc,
828
+					     unsigned long *flags)
829
+{
830
+	struct xhci_bus_state *bus_state;
831
+	struct xhci_hcd	*xhci;
832
+	struct usb_hcd *hcd;
833
+	int slot_id;
834
+	u32 wIndex;
835
+
836
+	hcd = port->rhub->hcd;
837
+	bus_state = &port->rhub->bus_state;
838
+	xhci = hcd_to_xhci(hcd);
839
+	wIndex = port->hcd_portnum;
840
+
841
+	if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
842
+		*status = 0xffffffff;
843
+		return -EINVAL;
844
+	}
845
+	/* did port event handler already start resume timing? */
846
+	if (!bus_state->resume_done[wIndex]) {
847
+		/* If not, maybe we are in a host initated resume? */
848
+		if (test_bit(wIndex, &bus_state->resuming_ports)) {
849
+			/* Host initated resume doesn't time the resume
850
+			 * signalling using resume_done[].
851
+			 * It manually sets RESUME state, sleeps 20ms
852
+			 * and sets U0 state. This should probably be
853
+			 * changed, but not right now.
854
+			 */
855
+		} else {
856
+			/* port resume was discovered now and here,
857
+			 * start resume timing
858
+			 */
859
+			unsigned long timeout = jiffies +
860
+				msecs_to_jiffies(USB_RESUME_TIMEOUT);
861
+
862
+			set_bit(wIndex, &bus_state->resuming_ports);
863
+			bus_state->resume_done[wIndex] = timeout;
864
+			mod_timer(&hcd->rh_timer, timeout);
865
+			usb_hcd_start_port_resume(&hcd->self, wIndex);
866
+		}
867
+	/* Has resume been signalled for USB_RESUME_TIME yet? */
868
+	} else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) {
869
+		int time_left;
870
+
871
+		xhci_dbg(xhci, "resume USB2 port %d-%d\n",
872
+			 hcd->self.busnum, wIndex + 1);
873
+
874
+		bus_state->resume_done[wIndex] = 0;
875
+		clear_bit(wIndex, &bus_state->resuming_ports);
876
+
877
+		set_bit(wIndex, &bus_state->rexit_ports);
878
+
879
+		xhci_test_and_clear_bit(xhci, port, PORT_PLC);
880
+		xhci_set_link_state(xhci, port, XDEV_U0);
881
+
882
+		spin_unlock_irqrestore(&xhci->lock, *flags);
883
+		time_left = wait_for_completion_timeout(
884
+			&bus_state->rexit_done[wIndex],
885
+			msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
886
+		spin_lock_irqsave(&xhci->lock, *flags);
887
+
888
+		if (time_left) {
889
+			slot_id = xhci_find_slot_id_by_port(hcd, xhci,
890
+							    wIndex + 1);
891
+			if (!slot_id) {
892
+				xhci_dbg(xhci, "slot_id is zero\n");
893
+				*status = 0xffffffff;
894
+				return -ENODEV;
895
+			}
896
+			xhci_ring_device(xhci, slot_id);
897
+		} else {
898
+			int port_status = readl(port->addr);
899
+
900
+			xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
901
+				  hcd->self.busnum, wIndex + 1, port_status);
902
+			*status |= USB_PORT_STAT_SUSPEND;
903
+			clear_bit(wIndex, &bus_state->rexit_ports);
904
+		}
905
+
906
+		usb_hcd_end_port_resume(&hcd->self, wIndex);
907
+		bus_state->port_c_suspend |= 1 << wIndex;
908
+		bus_state->suspended_ports &= ~(1 << wIndex);
909
+	} else {
910
+		/*
911
+		 * The resume has been signaling for less than
912
+		 * USB_RESUME_TIME. Report the port status as SUSPEND,
913
+		 * let the usbcore check port status again and clear
914
+		 * resume signaling later.
915
+		 */
916
+		*status |= USB_PORT_STAT_SUSPEND;
917
+	}
918
+	return 0;
919
+}
920
+
817921 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
818922 {
819923 	u32 ext_stat = 0;
....@@ -828,6 +932,98 @@
828932 	ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
829933 
830934 	return ext_stat;
935
+}
936
+
937
+static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
938
+				      u32 portsc)
939
+{
940
+	struct xhci_bus_state *bus_state;
941
+	struct xhci_hcd	*xhci;
942
+	struct usb_hcd *hcd;
943
+	u32 link_state;
944
+	u32 portnum;
945
+
946
+	bus_state = &port->rhub->bus_state;
947
+	xhci = hcd_to_xhci(port->rhub->hcd);
948
+	hcd = port->rhub->hcd;
949
+	link_state = portsc & PORT_PLS_MASK;
950
+	portnum = port->hcd_portnum;
951
+
952
+	/* USB3 specific wPortChange bits
953
+	 *
954
+	 * Port link change with port in resume state should not be
955
+	 * reported to usbcore, as this is an internal state to be
956
+	 * handled by xhci driver. Reporting PLC to usbcore may
957
+	 * cause usbcore clearing PLC first and port change event
958
+	 * irq won't be generated.
959
+	 */
960
+
961
+	if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
962
+		*status |= USB_PORT_STAT_C_LINK_STATE << 16;
963
+	if (portsc & PORT_WRC)
964
+		*status |= USB_PORT_STAT_C_BH_RESET << 16;
965
+	if (portsc & PORT_CEC)
966
+		*status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
967
+
968
+	/* USB3 specific wPortStatus bits */
969
+	if (portsc & PORT_POWER) {
970
+		*status |= USB_SS_PORT_STAT_POWER;
971
+		/* link state handling */
972
+		if (link_state == XDEV_U0)
973
+			bus_state->suspended_ports &= ~(1 << portnum);
974
+	}
975
+
976
+	/* remote wake resume signaling complete */
977
+	if (bus_state->port_remote_wakeup & (1 << portnum) &&
978
+	    link_state != XDEV_RESUME &&
979
+	    link_state != XDEV_RECOVERY) {
980
+		bus_state->port_remote_wakeup &= ~(1 << portnum);
981
+		usb_hcd_end_port_resume(&hcd->self, portnum);
982
+	}
983
+
984
+	xhci_hub_report_usb3_link_state(xhci, status, portsc);
985
+	xhci_del_comp_mod_timer(xhci, portsc, portnum);
986
+}
987
+
988
+static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
989
+				      u32 portsc, unsigned long *flags)
990
+{
991
+	struct xhci_bus_state *bus_state;
992
+	u32 link_state;
993
+	u32 portnum;
994
+	int ret;
995
+
996
+	bus_state = &port->rhub->bus_state;
997
+	link_state = portsc & PORT_PLS_MASK;
998
+	portnum = port->hcd_portnum;
999
+
1000
+	/* USB2 wPortStatus bits */
1001
+	if (portsc & PORT_POWER) {
1002
+		*status |= USB_PORT_STAT_POWER;
1003
+
1004
+		/* link state is only valid if port is powered */
1005
+		if (link_state == XDEV_U3)
1006
+			*status |= USB_PORT_STAT_SUSPEND;
1007
+		if (link_state == XDEV_U2)
1008
+			*status |= USB_PORT_STAT_L1;
1009
+		if (link_state == XDEV_U0) {
1010
+			if (bus_state->resume_done[portnum])
1011
+				usb_hcd_end_port_resume(&port->rhub->hcd->self,
1012
+							portnum);
1013
+			bus_state->resume_done[portnum] = 0;
1014
+			clear_bit(portnum, &bus_state->resuming_ports);
1015
+			if (bus_state->suspended_ports & (1 << portnum)) {
1016
+				bus_state->suspended_ports &= ~(1 << portnum);
1017
+				bus_state->port_c_suspend |= 1 << portnum;
1018
+			}
1019
+		}
1020
+		if (link_state == XDEV_RESUME) {
1021
+			ret = xhci_handle_usb2_port_link_resume(port, status,
1022
+								portsc, flags);
1023
+			if (ret)
1024
+				return;
1025
+		}
1026
+	}
8311027 }
8321028 
8331029 /*
....@@ -847,16 +1043,14 @@
8471043 	__releases(&xhci->lock)
8481044 	__acquires(&xhci->lock)
8491045 {
850
-	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
8511046 	u32 status = 0;
852
-	int slot_id;
8531047 	struct xhci_hub *rhub;
8541048 	struct xhci_port *port;
8551049 
8561050 	rhub = xhci_get_rhub(hcd);
8571051 	port = rhub->ports[wIndex];
8581052 
859
-	/* wPortChange bits */
1053
+	/* common wPortChange bits */
8601054 	if (raw_port_status & PORT_CSC)
8611055 		status |= USB_PORT_STAT_C_CONNECTION << 16;
8621056 	if (raw_port_status & PORT_PEC)
....@@ -865,115 +1059,25 @@
8651059 		status |= USB_PORT_STAT_C_OVERCURRENT << 16;
8661060 	if ((raw_port_status & PORT_RC))
8671061 		status |= USB_PORT_STAT_C_RESET << 16;
868
-	/* USB3.0 only */
869
-	if (hcd->speed >= HCD_USB3) {
870
-		/* Port link change with port in resume state should not be
871
-		 * reported to usbcore, as this is an internal state to be
872
-		 * handled by xhci driver. Reporting PLC to usbcore may
873
-		 * cause usbcore clearing PLC first and port change event
874
-		 * irq won't be generated.
875
-		 */
876
-		if ((raw_port_status & PORT_PLC) &&
877
-			(raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
878
-			status |= USB_PORT_STAT_C_LINK_STATE << 16;
879
-		if ((raw_port_status & PORT_WRC))
880
-			status |= USB_PORT_STAT_C_BH_RESET << 16;
881
-		if ((raw_port_status & PORT_CEC))
882
-			status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
8831062 
884
-		/* USB3 remote wake resume signaling completed */
885
-		if (bus_state->port_remote_wakeup & (1 << wIndex) &&
886
-		    (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME &&
887
-		    (raw_port_status & PORT_PLS_MASK) != XDEV_RECOVERY) {
888
-			bus_state->port_remote_wakeup &= ~(1 << wIndex);
889
-			usb_hcd_end_port_resume(&hcd->self, wIndex);
890
-		}
1063
+	/* common wPortStatus bits */
1064
+	if (raw_port_status & PORT_CONNECT) {
1065
+		status |= USB_PORT_STAT_CONNECTION;
1066
+		status |= xhci_port_speed(raw_port_status);
8911067 	}
1068
+	if (raw_port_status & PORT_PE)
1069
+		status |= USB_PORT_STAT_ENABLE;
1070
+	if (raw_port_status & PORT_OC)
1071
+		status |= USB_PORT_STAT_OVERCURRENT;
1072
+	if (raw_port_status & PORT_RESET)
1073
+		status |= USB_PORT_STAT_RESET;
8921074 
893
-	if (hcd->speed < HCD_USB3) {
894
-		if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
895
-				&& (raw_port_status & PORT_POWER))
896
-			status |= USB_PORT_STAT_SUSPEND;
897
-	}
898
-	if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
899
-		!DEV_SUPERSPEED_ANY(raw_port_status) && hcd->speed < HCD_USB3) {
900
-		if ((raw_port_status & PORT_RESET) ||
901
-				!(raw_port_status & PORT_PE))
902
-			return 0xffffffff;
903
-		/* did port event handler already start resume timing? */
904
-		if (!bus_state->resume_done[wIndex]) {
905
-			/* If not, maybe we are in a host initated resume? */
906
-			if (test_bit(wIndex, &bus_state->resuming_ports)) {
907
-				/* Host initated resume doesn't time the resume
908
-				 * signalling using resume_done[].
909
-				 * It manually sets RESUME state, sleeps 20ms
910
-				 * and sets U0 state. This should probably be
911
-				 * changed, but not right now.
912
-				 */
913
-			} else {
914
-				/* port resume was discovered now and here,
915
-				 * start resume timing
916
-				 */
917
-				unsigned long timeout = jiffies +
918
-					msecs_to_jiffies(USB_RESUME_TIMEOUT);
919
-
920
-				set_bit(wIndex, &bus_state->resuming_ports);
921
-				bus_state->resume_done[wIndex] = timeout;
922
-				mod_timer(&hcd->rh_timer, timeout);
923
-				usb_hcd_start_port_resume(&hcd->self, wIndex);
924
-			}
925
-		/* Has resume been signalled for USB_RESUME_TIME yet? */
926
-		} else if (time_after_eq(jiffies,
927
-					 bus_state->resume_done[wIndex])) {
928
-			int time_left;
929
-
930
-			xhci_dbg(xhci, "Resume USB2 port %d\n",
931
-					wIndex + 1);
932
-			bus_state->resume_done[wIndex] = 0;
933
-			clear_bit(wIndex, &bus_state->resuming_ports);
934
-
935
-			set_bit(wIndex, &bus_state->rexit_ports);
936
-
937
-			xhci_test_and_clear_bit(xhci, port, PORT_PLC);
938
-			xhci_set_link_state(xhci, port, XDEV_U0);
939
-
940
-			spin_unlock_irqrestore(&xhci->lock, *flags);
941
-			time_left = wait_for_completion_timeout(
942
-					&bus_state->rexit_done[wIndex],
943
-					msecs_to_jiffies(
944
-						XHCI_MAX_REXIT_TIMEOUT_MS));
945
-			spin_lock_irqsave(&xhci->lock, *flags);
946
-
947
-			if (time_left) {
948
-				slot_id = xhci_find_slot_id_by_port(hcd,
949
-						xhci, wIndex + 1);
950
-				if (!slot_id) {
951
-					xhci_dbg(xhci, "slot_id is zero\n");
952
-					return 0xffffffff;
953
-				}
954
-				xhci_ring_device(xhci, slot_id);
955
-			} else {
956
-				int port_status = readl(port->addr);
957
-				xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
958
-						XHCI_MAX_REXIT_TIMEOUT_MS,
959
-						port_status);
960
-				status |= USB_PORT_STAT_SUSPEND;
961
-				clear_bit(wIndex, &bus_state->rexit_ports);
962
-			}
963
-
964
-			usb_hcd_end_port_resume(&hcd->self, wIndex);
965
-			bus_state->port_c_suspend |= 1 << wIndex;
966
-			bus_state->suspended_ports &= ~(1 << wIndex);
967
-		} else {
968
-			/*
969
-			 * The resume has been signaling for less than
970
-			 * USB_RESUME_TIME. Report the port status as SUSPEND,
971
-			 * let the usbcore check port status again and clear
972
-			 * resume signaling later.
973
-			 */
974
-			status |= USB_PORT_STAT_SUSPEND;
975
-		}
976
-	}
1075
+	/* USB2 and USB3 specific bits, including Port Link State */
1076
+	if (hcd->speed >= HCD_USB3)
1077
+		xhci_get_usb3_port_status(port, &status, raw_port_status);
1078
+	else
1079
+		xhci_get_usb2_port_status(port, &status, raw_port_status,
1080
+					  flags);
9771081 	/*
9781082 	 * Clear stale usb2 resume signalling variables in case port changed
9791083 	 * state during resume signalling. For example on error
....@@ -987,44 +1091,6 @@
9871091 		usb_hcd_end_port_resume(&hcd->self, wIndex);
9881092 	}
9891093 
990
-
991
-	if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
992
-	    (raw_port_status & PORT_POWER)) {
993
-		if (bus_state->suspended_ports & (1 << wIndex)) {
994
-			bus_state->suspended_ports &= ~(1 << wIndex);
995
-			if (hcd->speed < HCD_USB3)
996
-				bus_state->port_c_suspend |= 1 << wIndex;
997
-		}
998
-		bus_state->resume_done[wIndex] = 0;
999
-		clear_bit(wIndex, &bus_state->resuming_ports);
1000
-	}
1001
-	if (raw_port_status & PORT_CONNECT) {
1002
-		status |= USB_PORT_STAT_CONNECTION;
1003
-		status |= xhci_port_speed(raw_port_status);
1004
-	}
1005
-	if (raw_port_status & PORT_PE)
1006
-		status |= USB_PORT_STAT_ENABLE;
1007
-	if (raw_port_status & PORT_OC)
1008
-		status |= USB_PORT_STAT_OVERCURRENT;
1009
-	if (raw_port_status & PORT_RESET)
1010
-		status |= USB_PORT_STAT_RESET;
1011
-	if (raw_port_status & PORT_POWER) {
1012
-		if (hcd->speed >= HCD_USB3)
1013
-			status |= USB_SS_PORT_STAT_POWER;
1014
-		else
1015
-			status |= USB_PORT_STAT_POWER;
1016
-	}
1017
-	/* Update Port Link State */
1018
-	if (hcd->speed >= HCD_USB3) {
1019
-		xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
1020
-		/*
1021
-		 * Verify if all USB3 Ports Have entered U0 already.
1022
-		 * Delete Compliance Mode Timer if so.
1023
-		 */
1024
-		xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
1025
-	} else {
1026
-		xhci_hub_report_usb2_link_state(&status, raw_port_status);
1027
-	}
10281094 	if (bus_state->port_c_suspend & (1 << wIndex))
10291095 		status |= USB_PORT_STAT_C_SUSPEND << 16;
10301096 
....@@ -1051,7 +1117,7 @@
10511117 	rhub = xhci_get_rhub(hcd);
10521118 	ports = rhub->ports;
10531119 	max_ports = rhub->num_ports;
1054
-	bus_state = &xhci->bus_state[hcd_index(hcd)];
1120
+	bus_state = &rhub->bus_state;
10551121 
10561122 	spin_lock_irqsave(&xhci->lock, flags);
10571123 	switch (typeReq) {
....@@ -1100,9 +1166,8 @@
11001166 		if (status == 0xffffffff)
11011167 			goto error;
11021168 
1103
-		xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
1104
-				wIndex, temp);
1105
-		xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
1169
+		xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1170
+			 hcd->self.busnum, wIndex + 1, temp, status);
11061171 
11071172 		put_unaligned(cpu_to_le32(status), (__le32 *) buf);
11081173 		/* if USB 3.1 extended port status return additional 4 bytes */
....@@ -1158,7 +1223,8 @@
11581223 			temp = readl(ports[wIndex]->addr);
11591224 			if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
11601225 				|| (temp & PORT_PLS_MASK) >= XDEV_U3) {
1161
-				xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
1226
+				xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1227
+					  hcd->self.busnum, wIndex + 1);
11621228 				goto error;
11631229 			}
11641230 
....@@ -1186,7 +1252,8 @@
11861252 			temp = readl(ports[wIndex]->addr);
11871253 			/* Disable port */
11881254 			if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1189
-				xhci_dbg(xhci, "Disable port %d\n", wIndex);
1255
+				xhci_dbg(xhci, "Disable port %d-%d\n",
1256
+					 hcd->self.busnum, wIndex + 1);
11901257 				temp = xhci_port_state_to_neutral(temp);
11911258 				/*
11921259 				 * Clear all change bits, so that we get a new
....@@ -1202,7 +1269,8 @@
12021269 
12031270 			/* Put link in RxDetect (enable port) */
12041271 			if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1205
-				xhci_dbg(xhci, "Enable port %d\n", wIndex);
1272
+				xhci_dbg(xhci, "Enable port %d-%d\n",
1273
+					 hcd->self.busnum, wIndex + 1);
12061274 				xhci_set_link_state(xhci, ports[wIndex],
12071275 							link_state);
12081276 				temp = readl(ports[wIndex]->addr);
....@@ -1234,8 +1302,8 @@
12341302 					goto error;
12351303 				}
12361304 
1237
-				xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1238
-						wIndex);
1305
+				xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n",
1306
+					 hcd->self.busnum, wIndex + 1);
12391307 				xhci_set_link_state(xhci, ports[wIndex],
12401308 						link_state);
12411309 
....@@ -1249,11 +1317,52 @@
12491317 			}
12501318 			/* Can't set port link state above '3' (U3) */
12511319 			if (link_state > USB_SS_PORT_LS_U3) {
1252
-				xhci_warn(xhci, "Cannot set port %d link state %d\n",
1253
-					 wIndex, link_state);
1320
+				xhci_warn(xhci, "Cannot set port %d-%d link state %d\n",
1321
+					  hcd->self.busnum, wIndex + 1,
1322
+					  link_state);
12541323 				goto error;
12551324 			}
1325
+
1326
+			/*
1327
+			 * set link to U0, steps depend on current link state.
1328
+			 * U3: set link to U0 and wait for u3exit completion.
1329
+			 * U1/U2:  no PLC complete event, only set link to U0.
1330
+			 * Resume/Recovery: device initiated U0, only wait for
1331
+			 * completion
1332
+			 */
1333
+			if (link_state == USB_SS_PORT_LS_U0) {
1334
+				u32 pls = temp & PORT_PLS_MASK;
1335
+				bool wait_u0 = false;
1336
+
1337
+				/* already in U0 */
1338
+				if (pls == XDEV_U0)
1339
+					break;
1340
+				if (pls == XDEV_U3 ||
1341
+				    pls == XDEV_RESUME ||
1342
+				    pls == XDEV_RECOVERY) {
1343
+					wait_u0 = true;
1344
+					reinit_completion(&bus_state->u3exit_done[wIndex]);
1345
+				}
1346
+				if (pls <= XDEV_U3) /* U1, U2, U3 */
1347
+					xhci_set_link_state(xhci, ports[wIndex],
1348
+							    USB_SS_PORT_LS_U0);
1349
+				if (!wait_u0) {
1350
+					if (pls > XDEV_U3)
1351
+						goto error;
1352
+					break;
1353
+				}
1354
+				spin_unlock_irqrestore(&xhci->lock, flags);
1355
+				if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex],
1356
+								 msecs_to_jiffies(500)))
1357
+					xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n",
1358
+						 hcd->self.busnum, wIndex + 1);
1359
+				spin_lock_irqsave(&xhci->lock, flags);
1360
+				temp = readl(ports[wIndex]->addr);
1361
+				break;
1362
+			}
1363
+
12561364 			if (link_state == USB_SS_PORT_LS_U3) {
1365
+				int retries = 16;
12571366 				slot_id = xhci_find_slot_id_by_port(hcd, xhci,
12581367 						wIndex + 1);
12591368 				if (slot_id) {
....@@ -1264,26 +1373,18 @@
12641373 					xhci_stop_device(xhci, slot_id, 1);
12651374 					spin_lock_irqsave(&xhci->lock, flags);
12661375 				}
1267
-			}
1268
-
1269
-			xhci_set_link_state(xhci, ports[wIndex], link_state);
1270
-
1271
-			spin_unlock_irqrestore(&xhci->lock, flags);
1272
-			if (link_state == USB_SS_PORT_LS_U3) {
1273
-				int retries = 16;
1274
-
1376
+				xhci_set_link_state(xhci, ports[wIndex], USB_SS_PORT_LS_U3);
1377
+				spin_unlock_irqrestore(&xhci->lock, flags);
12751378 				while (retries--) {
12761379 					usleep_range(4000, 8000);
12771380 					temp = readl(ports[wIndex]->addr);
12781381 					if ((temp & PORT_PLS_MASK) == XDEV_U3)
12791382 						break;
12801383 				}
1281
-			}
1282
-			spin_lock_irqsave(&xhci->lock, flags);
1283
-
1284
-			temp = readl(ports[wIndex]->addr);
1285
-			if (link_state == USB_SS_PORT_LS_U3)
1384
+				spin_lock_irqsave(&xhci->lock, flags);
1385
+				temp = readl(ports[wIndex]->addr);
12861386 				bus_state->suspended_ports |= 1 << wIndex;
1387
+			}
12871388 			break;
12881389 		case USB_PORT_FEAT_POWER:
12891390 			/*
....@@ -1299,15 +1400,15 @@
12991400 			writel(temp, ports[wIndex]->addr);
13001401 
13011402 			temp = readl(ports[wIndex]->addr);
1302
-			xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1403
+			xhci_dbg(xhci, "set port reset, actual port %d-%d status  = 0x%x\n",
1404
+				 hcd->self.busnum, wIndex + 1, temp);
13031405 			break;
13041406 		case USB_PORT_FEAT_REMOTE_WAKE_MASK:
13051407 			xhci_set_remote_wake_mask(xhci, ports[wIndex],
13061408 						  wake_mask);
13071409 			temp = readl(ports[wIndex]->addr);
1308
-			xhci_dbg(xhci, "set port remote wake mask, "
1309
-					"actual port %d status  = 0x%x\n",
1310
-					wIndex, temp);
1410
+			xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status  = 0x%x\n",
1411
+				 hcd->self.busnum, wIndex + 1, temp);
13111412 			break;
13121413 		case USB_PORT_FEAT_BH_PORT_RESET:
13131414 			temp |= PORT_WR;
....@@ -1334,7 +1435,8 @@
13341435 			/* 4.19.6 Port Test Modes (USB2 Test Mode) */
13351436 			if (hcd->speed != HCD_USB2)
13361437 				goto error;
1337
-			if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1438
+			if (test_mode > USB_TEST_FORCE_ENABLE ||
1439
+			    test_mode < USB_TEST_J)
13381440 				goto error;
13391441 			retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
13401442 						      &flags);
....@@ -1392,7 +1494,7 @@
13921494 			break;
13931495 		case USB_PORT_FEAT_C_SUSPEND:
13941496 			bus_state->port_c_suspend &= ~(1 << wIndex);
1395
-			/* fall through */
1497
+			fallthrough;
13961498 		case USB_PORT_FEAT_C_RESET:
13971499 		case USB_PORT_FEAT_C_BH_PORT_RESET:
13981500 		case USB_PORT_FEAT_C_CONNECTION:
....@@ -1450,7 +1552,7 @@
14501552 	rhub = xhci_get_rhub(hcd);
14511553 	ports = rhub->ports;
14521554 	max_ports = rhub->num_ports;
1453
-	bus_state = &xhci->bus_state[hcd_index(hcd)];
1555
+	bus_state = &rhub->bus_state;
14541556 
14551557 	/* Initial status is no changes */
14561558 	retval = (max_ports + 8) / 8;
....@@ -1489,7 +1591,8 @@
14891591 			status = 1;
14901592 	}
14911593 	if (!status && !reset_change) {
1492
-		xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1594
+		xhci_dbg(xhci, "%s: stopping usb%d port polling\n",
1595
+			 __func__, hcd->self.busnum);
14931596 		clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
14941597 	}
14951598 	spin_unlock_irqrestore(&xhci->lock, flags);
....@@ -1512,7 +1615,7 @@
15121615 	rhub = xhci_get_rhub(hcd);
15131616 	ports = rhub->ports;
15141617 	max_ports = rhub->num_ports;
1515
-	bus_state = &xhci->bus_state[hcd_index(hcd)];
1618
+	bus_state = &rhub->bus_state;
15161619 	wake_enabled = hcd->self.root_hub->do_remote_wakeup;
15171620 
15181621 	spin_lock_irqsave(&xhci->lock, flags);
....@@ -1521,7 +1624,8 @@
15211624 		if (bus_state->resuming_ports ||	/* USB2 */
15221625 		    bus_state->port_remote_wakeup) {	/* USB3 */
15231626 			spin_unlock_irqrestore(&xhci->lock, flags);
1524
-			xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1627
+			xhci_dbg(xhci, "usb%d bus suspend to fail because a port is resuming\n",
1628
+				 hcd->self.busnum);
15251629 			return -EBUSY;
15261630 		}
15271631 	}
....@@ -1548,8 +1652,8 @@
15481652 			spin_unlock_irqrestore(&xhci->lock, flags);
15491653 			msleep(XHCI_PORT_POLLING_LFPS_TIME);
15501654 			spin_lock_irqsave(&xhci->lock, flags);
1551
-			xhci_dbg(xhci, "port %d polling in bus suspend, waiting\n",
1552
-				 port_index);
1655
+			xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n",
1656
+				 hcd->self.busnum, port_index + 1);
15531657 			goto retry;
15541658 		}
15551659 		/* bail out if port detected a over-current condition */
....@@ -1567,7 +1671,8 @@
15671671 				xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
15681672 				return -EBUSY;
15691673 			}
1570
-			xhci_dbg(xhci, "port %d not suspended\n", port_index);
1674
+			xhci_dbg(xhci, "port %d-%d not suspended\n",
1675
+				 hcd->self.busnum, port_index + 1);
15711676 			t2 &= ~PORT_PLS_MASK;
15721677 			t2 |= PORT_LINK_STROBE | XDEV_U3;
15731678 			set_bit(port_index, &bus_state->bus_suspended);
....@@ -1640,6 +1745,7 @@
16401745 
16411746 	return 0;
16421747 }
1748
+EXPORT_SYMBOL_GPL(xhci_bus_suspend);
16431749 
16441750 /*
16451751  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
....@@ -1685,7 +1791,7 @@
16851791 	rhub = xhci_get_rhub(hcd);
16861792 	ports = rhub->ports;
16871793 	max_ports = rhub->num_ports;
1688
-	bus_state = &xhci->bus_state[hcd_index(hcd)];
1794
+	bus_state = &rhub->bus_state;
16891795 
16901796 	if (time_before(jiffies, bus_state->next_statechange))
16911797 		msleep(5);
....@@ -1715,7 +1821,8 @@
17151821 		if ((xhci->quirks & XHCI_MISSING_CAS) &&
17161822 		    (hcd->speed >= HCD_USB3) &&
17171823 		    xhci_port_missing_cas_quirk(ports[port_index])) {
1718
-			xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1824
+			xhci_dbg(xhci, "reset stuck port %d-%d\n",
1825
+				 hcd->self.busnum, port_index + 1);
17191826 			clear_bit(port_index, &bus_state->bus_suspended);
17201827 			continue;
17211828 		}
....@@ -1762,8 +1869,8 @@
17621869 		sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
17631870 				      PORT_PLC, 10 * 1000);
17641871 		if (sret) {
1765
-			xhci_warn(xhci, "port %d resume PLC timeout\n",
1766
-				  port_index);
1872
+			xhci_warn(xhci, "port %d-%d resume PLC timeout\n",
1873
+				  hcd->self.busnum, port_index + 1);
17671874 			continue;
17681875 		}
17691876 		xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
....@@ -1783,16 +1890,14 @@
17831890 	spin_unlock_irqrestore(&xhci->lock, flags);
17841891 	return 0;
17851892 }
1893
+EXPORT_SYMBOL_GPL(xhci_bus_resume);
17861894 
17871895 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
17881896 {
1789
-	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
1790
-	struct xhci_bus_state *bus_state;
1791
-
1792
-	bus_state = &xhci->bus_state[hcd_index(hcd)];
1897
+	struct xhci_hub *rhub = xhci_get_rhub(hcd);
17931898 
17941899 	/* USB3 port wakeups are reported via usb_wakeup_notification() */
1795
-	return bus_state->resuming_ports;	/* USB2 ports only */
1900
+	return rhub->bus_state.resuming_ports;	/* USB2 ports only */
17961901 }
17971902 
17981903 #endif	/* CONFIG_PM */