forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/drivers/tty/synclink.c
....@@ -252,7 +252,6 @@
252252 
253253 	char device_name[25];		/* device instance name */
254254 
255
-	unsigned int bus_type;	/* expansion bus type (ISA,EISA,PCI) */
256255 	unsigned char bus;		/* expansion bus number (zero based) */
257256 	unsigned char function;		/* PCI device number */
258257 
....@@ -943,7 +942,7 @@
943942 	return 0;
944943 }
945944 
946
-/**
945
+/*
947946  * line discipline callback wrappers
948947  *
949948  * The wrappers maintain line discipline references
....@@ -2959,8 +2958,7 @@
29592958 	if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
29602959 		return -ENODEV;
29612960 
2962
-	if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2963
-	    (cmd != TIOCMIWAIT)) {
2961
+	if (cmd != TIOCMIWAIT) {
29642962 		if (tty_io_error(tty))
29652963 		    return -EIO;
29662964 	}
....@@ -3433,15 +3431,9 @@
34333431 	char	stat_buf[30];
34343432 	unsigned long flags;
34353433 
3436
-	if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3437
-		seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3438
-			info->device_name, info->io_base, info->irq_level,
3439
-			info->phys_memory_base, info->phys_lcr_base);
3440
-	} else {
3441
-		seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
3442
-			info->device_name, info->io_base, 
3443
-			info->irq_level, info->dma_level);
3444
-	}
3434
+	seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3435
+		info->device_name, info->io_base, info->irq_level,
3436
+		info->phys_memory_base, info->phys_lcr_base);
34453437 
34463438 	/* output current serial signal states */
34473439 	spin_lock_irqsave(&info->irq_spinlock,flags);
....@@ -3557,54 +3549,27 @@
35573549 	if ( info->max_frame_size % DMABUFFERSIZE )
35583550 		BuffersPerFrame++;
35593551 
3560
-	if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3561
-		/*
3562
-		 * The PCI adapter has 256KBytes of shared memory to use.
3563
-		 * This is 64 PAGE_SIZE buffers.
3564
-		 *
3565
-		 * The first page is used for padding at this time so the
3566
-		 * buffer list does not begin at offset 0 of the PCI
3567
-		 * adapter's shared memory.
3568
-		 *
3569
-		 * The 2nd page is used for the buffer list. A 4K buffer
3570
-		 * list can hold 128 DMA_BUFFER structures at 32 bytes
3571
-		 * each.
3572
-		 *
3573
-		 * This leaves 62 4K pages.
3574
-		 *
3575
-		 * The next N pages are used for transmit frame(s). We
3576
-		 * reserve enough 4K page blocks to hold the required
3577
-		 * number of transmit dma buffers (num_tx_dma_buffers),
3578
-		 * each of MaxFrameSize size.
3579
-		 *
3580
-		 * Of the remaining pages (62-N), determine how many can
3581
-		 * be used to receive full MaxFrameSize inbound frames
3582
-		 */
3583
-		info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3584
-		info->rx_buffer_count = 62 - info->tx_buffer_count;
3585
-	} else {
3586
-		/* Calculate the number of PAGE_SIZE buffers needed for */
3587
-		/* receive and transmit DMA buffers. */
3588
-
3589
-
3590
-		/* Calculate the number of DMA buffers necessary to */
3591
-		/* hold 7 max size receive frames and one max size transmit frame. */
3592
-		/* The receive buffer count is bumped by one so we avoid an */
3593
-		/* End of List condition if all receive buffers are used when */
3594
-		/* using linked list DMA buffers. */
3595
-
3596
-		info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3597
-		info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3598
-		
3599
-		/* 
3600
-		 * limit total TxBuffers & RxBuffers to 62 4K total 
3601
-		 * (ala PCI Allocation) 
3602
-		 */
3603
-		
3604
-		if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3605
-			info->rx_buffer_count = 62 - info->tx_buffer_count;
3606
-
3607
-	}
3552
+	/*
3553
+	 * The PCI adapter has 256KBytes of shared memory to use.  This is 64
3554
+	 * PAGE_SIZE buffers.
3555
+	 *
3556
+	 * The first page is used for padding at this time so the buffer list
3557
+	 * does not begin at offset 0 of the PCI adapter's shared memory.
3558
+	 *
3559
+	 * The 2nd page is used for the buffer list. A 4K buffer list can hold
3560
+	 * 128 DMA_BUFFER structures at 32 bytes each.
3561
+	 *
3562
+	 * This leaves 62 4K pages.
3563
+	 *
3564
+	 * The next N pages are used for transmit frame(s).  We reserve enough
3565
+	 * 4K page blocks to hold the required number of transmit dma buffers
3566
+	 * (num_tx_dma_buffers), each of MaxFrameSize size.
3567
+	 *
3568
+	 * Of the remaining pages (62-N), determine how many can be used to
3569
+	 * receive full MaxFrameSize inbound frames
3570
+	 */
3571
+	info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3572
+	info->rx_buffer_count = 62 - info->tx_buffer_count;
36083573 
36093574 	if ( debug_level >= DEBUG_LEVEL_INFO )
36103575 		printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
....@@ -3653,23 +3618,10 @@
36533618 {
36543619 	unsigned int i;
36553620 
3656
-	if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3657
-		/* PCI adapter uses shared memory. */
3658
-		info->buffer_list = info->memory_base + info->last_mem_alloc;
3659
-		info->buffer_list_phys = info->last_mem_alloc;
3660
-		info->last_mem_alloc += BUFFERLISTSIZE;
3661
-	} else {
3662
-		/* ISA adapter uses system memory. */
3663
-		/* The buffer lists are allocated as a common buffer that both */
3664
-		/* the processor and adapter can access. This allows the driver to */
3665
-		/* inspect portions of the buffer while other portions are being */
3666
-		/* updated by the adapter using Bus Master DMA. */
3667
-
3668
-		info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3669
-		if (info->buffer_list == NULL)
3670
-			return -ENOMEM;
3671
-		info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3672
-	}
3621
+	/* PCI adapter uses shared memory. */
3622
+	info->buffer_list = info->memory_base + info->last_mem_alloc;
3623
+	info->buffer_list_phys = info->last_mem_alloc;
3624
+	info->last_mem_alloc += BUFFERLISTSIZE;
36733625 
36743626 	/* We got the memory for the buffer entry lists. */
36753627 	/* Initialize the memory block to all zeros. */
....@@ -3735,9 +3687,6 @@
37353687  */
37363688 static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
37373689 {
3738
-	if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3739
-		dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3740
-		
37413690 	info->buffer_list = NULL;
37423691 	info->rx_buffer_list = NULL;
37433692 	info->tx_buffer_list = NULL;
....@@ -3763,24 +3712,13 @@
37633712 static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
37643713 {
37653714 	int i;
3766
-	u32 phys_addr;
37673715 
37683716 	/* Allocate page sized buffers for the receive buffer list */
37693717 
37703718 	for ( i = 0; i < Buffercount; i++ ) {
3771
-		if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3772
-			/* PCI adapter uses shared memory buffers. */
3773
-			BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3774
-			phys_addr = info->last_mem_alloc;
3775
-			info->last_mem_alloc += DMABUFFERSIZE;
3776
-		} else {
3777
-			/* ISA adapter uses system memory. */
3778
-			BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3779
-			if (BufferList[i].virt_addr == NULL)
3780
-				return -ENOMEM;
3781
-			phys_addr = (u32)(BufferList[i].dma_addr);
3782
-		}
3783
-		BufferList[i].phys_addr = phys_addr;
3719
+		BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3720
+		BufferList[i].phys_addr = info->last_mem_alloc;
3721
+		info->last_mem_alloc += DMABUFFERSIZE;
37843722 	}
37853723 
37863724 	return 0;
....@@ -3808,8 +3746,6 @@
38083746 	if ( BufferList ) {
38093747 		for ( i = 0 ; i < Buffercount ; i++ ) {
38103748 			if ( BufferList[i].virt_addr ) {
3811
-				if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3812
-					dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
38133749 				BufferList[i].virt_addr = NULL;
38143750 			}
38153751 		}
....@@ -4041,58 +3977,40 @@
40413977 	}
40423978 	info->irq_requested = true;
40433979 	
4044
-	if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4045
-		if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4046
-			printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4047
-				__FILE__,__LINE__,info->device_name, info->phys_memory_base);
4048
-			goto errout;
4049
-		}
4050
-		info->shared_mem_requested = true;
4051
-		if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4052
-			printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4053
-				__FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4054
-			goto errout;
4055
-		}
4056
-		info->lcr_mem_requested = true;
4057
-
4058
-		info->memory_base = ioremap_nocache(info->phys_memory_base,
4059
-								0x40000);
4060
-		if (!info->memory_base) {
4061
-			printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
4062
-				__FILE__,__LINE__,info->device_name, info->phys_memory_base );
4063
-			goto errout;
4064
-		}
4065
-		
4066
-		if ( !mgsl_memory_test(info) ) {
4067
-			printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4068
-				__FILE__,__LINE__,info->device_name, info->phys_memory_base );
4069
-			goto errout;
4070
-		}
4071
-		
4072
-		info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4073
-								PAGE_SIZE);
4074
-		if (!info->lcr_base) {
4075
-			printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
4076
-				__FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4077
-			goto errout;
4078
-		}
4079
-		info->lcr_base += info->lcr_offset;
4080
-		
4081
-	} else {
4082
-		/* claim DMA channel */
4083
-		
4084
-		if (request_dma(info->dma_level,info->device_name) < 0){
4085
-			printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
4086
-				__FILE__,__LINE__,info->device_name, info->dma_level );
4087
-			goto errout;
4088
-		}
4089
-		info->dma_requested = true;
4090
-
4091
-		/* ISA adapter uses bus master DMA */		
4092
-		set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4093
-		enable_dma(info->dma_level);
3980
+	if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
3981
+		printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
3982
+			__FILE__,__LINE__,info->device_name, info->phys_memory_base);
3983
+		goto errout;
40943984 	}
4095
-	
3985
+	info->shared_mem_requested = true;
3986
+	if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
3987
+		printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
3988
+			__FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
3989
+		goto errout;
3990
+	}
3991
+	info->lcr_mem_requested = true;
3992
+
3993
+	info->memory_base = ioremap(info->phys_memory_base, 0x40000);
3994
+	if (!info->memory_base) {
3995
+		printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
3996
+			__FILE__,__LINE__,info->device_name, info->phys_memory_base );
3997
+		goto errout;
3998
+	}
3999
+		
4000
+	if ( !mgsl_memory_test(info) ) {
4001
+		printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4002
+			__FILE__,__LINE__,info->device_name, info->phys_memory_base );
4003
+		goto errout;
4004
+	}
4005
+		
4006
+	info->lcr_base = ioremap(info->phys_lcr_base, PAGE_SIZE);
4007
+	if (!info->lcr_base) {
4008
+		printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
4009
+			__FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4010
+		goto errout;
4011
+	}
4012
+	info->lcr_base += info->lcr_offset;
4013
+		
40964014 	if ( mgsl_allocate_dma_buffers(info) < 0 ) {
40974015 		printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
40984016 			__FILE__,__LINE__,info->device_name, info->dma_level );
....@@ -4201,16 +4119,10 @@
42014119 	else if ( info->max_frame_size > 65535 )
42024120 		info->max_frame_size = 65535;
42034121 	
4204
-	if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4205
-		printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4206
-			info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4207
-			info->phys_memory_base, info->phys_lcr_base,
4208
-		     	info->max_frame_size );
4209
-	} else {
4210
-		printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4211
-			info->device_name, info->io_base, info->irq_level, info->dma_level,
4212
-		     	info->max_frame_size );
4213
-	}
4122
+	printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4123
+		info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4124
+		info->phys_memory_base, info->phys_lcr_base,
4125
+	     	info->max_frame_size );
42144126 
42154127 #if SYNCLINK_GENERIC_HDLC
42164128 	hdlcdev_init(info);
....@@ -4326,41 +4238,6 @@
43264238 	return 0;
43274239 }
43284240 
4329
-/* enumerate user specified ISA adapters
4330
- */
4331
-static void mgsl_enum_isa_devices(void)
4332
-{
4333
-	struct mgsl_struct *info;
4334
-	int i;
4335
-		
4336
-	/* Check for user specified ISA devices */
4337
-	
4338
-	for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4339
-		if ( debug_level >= DEBUG_LEVEL_INFO )
4340
-			printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4341
-				io[i], irq[i], dma[i] );
4342
-		
4343
-		info = mgsl_allocate_device();
4344
-		if ( !info ) {
4345
-			/* error allocating device instance data */
4346
-			if ( debug_level >= DEBUG_LEVEL_ERROR )
4347
-				printk( "can't allocate device instance data.\n");
4348
-			continue;
4349
-		}
4350
-		
4351
-		/* Copy user configuration info to device instance data */
4352
-		info->io_base = (unsigned int)io[i];
4353
-		info->irq_level = (unsigned int)irq[i];
4354
-		info->irq_level = irq_canonicalize(info->irq_level);
4355
-		info->dma_level = (unsigned int)dma[i];
4356
-		info->bus_type = MGSL_BUS_TYPE_ISA;
4357
-		info->io_addr_size = 16;
4358
-		info->irq_flags = 0;
4359
-		
4360
-		mgsl_add_device( info );
4361
-	}
4362
-}
4363
-
43644241 static void synclink_cleanup(void)
43654242 {
43664243 	int rc;
....@@ -4404,7 +4281,6 @@
44044281 
44054282  	printk("%s %s\n", driver_name, driver_version);
44064283 
4407
-	mgsl_enum_isa_devices();
44084284 	if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
44094285 		printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
44104286 	else
....@@ -4457,8 +4333,7 @@
44574333 	outw( Cmd + info->loopback_bits, info->io_base + CCAR );
44584334 
44594335 	/* Read to flush write to CCAR */
4460
-	if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4461
-		inw( info->io_base + CCAR );
4336
+	inw( info->io_base + CCAR );
44624337 
44634338 }	/* end of usc_RTCmd() */
44644339 
....@@ -4482,8 +4357,7 @@
44824357 	outw( Cmd + info->mbre_bit, info->io_base );
44834358 
44844359 	/* Read to flush write to DCAR */
4485
-	if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4486
-		inw( info->io_base );
4360
+	inw( info->io_base );
44874361 
44884362 }	/* end of usc_DmaCmd() */
44894363 
....@@ -4512,8 +4386,7 @@
45124386 	outw( RegValue, info->io_base );
45134387 
45144388 	/* Read to flush write to DCAR */
4515
-	if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4516
-		inw( info->io_base );
4389
+	inw( info->io_base );
45174390 
45184391 }	/* end of usc_OutDmaReg() */
45194392  
....@@ -4565,8 +4438,7 @@
45654438 	outw( RegValue, info->io_base + CCAR );
45664439 
45674440 	/* Read to flush write to CCAR */
4568
-	if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4569
-		inw( info->io_base + CCAR );
4441
+	inw( info->io_base + CCAR );
45704442 
45714443 }	/* end of usc_OutReg() */
45724444 
....@@ -4765,10 +4637,7 @@
47654637 
47664638 	RegValue = usc_InReg( info, RICR ) & 0xc0;
47674639 
4768
-	if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4769
-		usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4770
-	else
4771
-		usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4640
+	usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
47724641 
47734642 	/* Unlatch all Rx status bits and clear Rx status IRQ Pending */
47744643 
....@@ -4829,10 +4698,7 @@
48294698 	 *	0000 0000 0011 0110 = 0x0036
48304699 	 */
48314700 
4832
-	if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4833
-		usc_OutReg( info, TICR, 0x0736 );
4834
-	else								
4835
-		usc_OutReg( info, TICR, 0x1436 );
4701
+	usc_OutReg( info, TICR, 0x0736 );
48364702 
48374703 	usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
48384704 	usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
....@@ -4922,10 +4788,7 @@
49224788 		/*  DPLL is enabled. Use BRG1 to provide continuous reference clock  */
49234789 		/*  for DPLL. DPLL mode in HCR is dependent on the encoding used. */
49244790 
4925
-		if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4926
-			XtalSpeed = 11059200;
4927
-		else
4928
-			XtalSpeed = 14745600;
4791
+		XtalSpeed = 11059200;
49294792 
49304793 		if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
49314794 			DpllDivisor = 16;
....@@ -5026,12 +4889,6 @@
50264889 	info->mbre_bit = BIT8;
50274890 	outw( BIT8, info->io_base );			/* set Master Bus Enable (DCAR) */
50284891 
5029
-	if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5030
-		/* Enable DMAEN (Port 7, Bit 14) */
5031
-		/* This connects the DMA request signal to the ISA bus */
5032
-		usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5033
-	}
5034
-
50354892 	/* DMA Control Register (DCR)
50364893 	 *
50374894 	 * <15..14>	10	Priority mode = Alternating Tx/Rx
....@@ -5054,13 +4911,8 @@
50544911 	 *	0110 0000 0000 1011 = 0x600b
50554912 	 */
50564913 
5057
-	if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5058
-		/* PCI adapter does not need DMA wait state */
5059
-		usc_OutDmaReg( info, DCR, 0xa00b );
5060
-	}
5061
-	else
5062
-		usc_OutDmaReg( info, DCR, 0x800b );
5063
-
4914
+	/* PCI adapter does not need DMA wait state */
4915
+	usc_OutDmaReg( info, DCR, 0xa00b );
50644916 
50654917 	/* Receive DMA mode Register (RDMR)
50664918 	 *
....@@ -5152,12 +5004,8 @@
51525004 	 * <7..0>	0x00	Maximum number of clock cycles per bus grant
51535005 	 */
51545006 
5155
-	if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5156
-		/* don't limit bus occupancy on PCI adapter */
5157
-		usc_OutDmaReg( info, BDCR, 0x0000 );
5158
-	}
5159
-	else
5160
-		usc_OutDmaReg( info, BDCR, 0x2000 );
5007
+	/* don't limit bus occupancy on PCI adapter */
5008
+	usc_OutDmaReg( info, BDCR, 0x0000 );
51615009 
51625010 	usc_stop_transmitter(info);
51635011 	usc_stop_receiver(info);
....@@ -5198,10 +5046,7 @@
51985046 		/* Write 16-bit Time Constant for BRG0 */
51995047 		/* use clock speed if available, otherwise use 8 for diagnostics */
52005048 		if (info->params.clock_speed) {
5201
-			if (info->bus_type == MGSL_BUS_TYPE_PCI)
5202
-				usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5203
-			else
5204
-				usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5049
+			usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
52055050 		} else
52065051 			usc_OutReg(info, TC0R, (u16)8);
52075052 
....@@ -5244,10 +5089,7 @@
52445089 	u16 Tc;
52455090 
52465091 	if ( data_rate ) {
5247
-		if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5248
-			XtalSpeed = 11059200;
5249
-		else
5250
-			XtalSpeed = 14745600;
5092
+		XtalSpeed = 11059200;
52515093 
52525094 
52535095 		/* Tc = (Xtal/Speed) - 1 */
....@@ -5725,44 +5567,38 @@
57255567  */
57265568 static void usc_reset( struct mgsl_struct *info )
57275569 {
5728
-	if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5729
-		int i;
5730
-		u32 readval;
5570
+	int i;
5571
+	u32 readval;
57315572 
5732
-		/* Set BIT30 of Misc Control Register */
5733
-		/* (Local Control Register 0x50) to force reset of USC. */
5573
+	/* Set BIT30 of Misc Control Register */
5574
+	/* (Local Control Register 0x50) to force reset of USC. */
57345575 
5735
-		volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5736
-		u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5576
+	volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5577
+	u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
57375578 
5738
-		info->misc_ctrl_value |= BIT30;
5739
-		*MiscCtrl = info->misc_ctrl_value;
5579
+	info->misc_ctrl_value |= BIT30;
5580
+	*MiscCtrl = info->misc_ctrl_value;
57405581 
5741
-		/*
5742
-		 * Force at least 170ns delay before clearing 
5743
-		 * reset bit. Each read from LCR takes at least 
5744
-		 * 30ns so 10 times for 300ns to be safe.
5745
-		 */
5746
-		for(i=0;i<10;i++)
5747
-			readval = *MiscCtrl;
5582
+	/*
5583
+	 * Force at least 170ns delay before clearing reset bit.  Each read from
5584
+	 * LCR takes at least 30ns so 10 times for 300ns to be safe.
5585
+	 */
5586
+	for(i=0;i<10;i++)
5587
+		readval = *MiscCtrl;
57485588 
5749
-		info->misc_ctrl_value &= ~BIT30;
5750
-		*MiscCtrl = info->misc_ctrl_value;
5589
+	info->misc_ctrl_value &= ~BIT30;
5590
+	*MiscCtrl = info->misc_ctrl_value;
57515591 
5752
-		*LCR0BRDR = BUS_DESCRIPTOR(
5753
-			1,		// Write Strobe Hold (0-3)
5754
-			2,		// Write Strobe Delay (0-3)
5755
-			2,		// Read Strobe Delay  (0-3)
5756
-			0,		// NWDD (Write data-data) (0-3)
5757
-			4,		// NWAD (Write Addr-data) (0-31)
5758
-			0,		// NXDA (Read/Write Data-Addr) (0-3)
5759
-			0,		// NRDD (Read Data-Data) (0-3)
5760
-			5		// NRAD (Read Addr-Data) (0-31)
5761
-			);
5762
-	} else {
5763
-		/* do HW reset */
5764
-		outb( 0,info->io_base + 8 );
5765
-	}
5592
+	*LCR0BRDR = BUS_DESCRIPTOR(
5593
+		1,		// Write Strobe Hold (0-3)
5594
+		2,		// Write Strobe Delay (0-3)
5595
+		2,		// Read Strobe Delay  (0-3)
5596
+		0,		// NWDD (Write data-data) (0-3)
5597
+		4,		// NWAD (Write Addr-data) (0-31)
5598
+		0,		// NXDA (Read/Write Data-Addr) (0-3)
5599
+		0,		// NRDD (Read Data-Data) (0-3)
5600
+		5		// NRAD (Read Addr-Data) (0-31)
5601
+		);
57665602 
57675603 	info->mbre_bit = 0;
57685604 	info->loopback_bits = 0;
....@@ -6008,12 +5844,6 @@
60085844 
60095845 	usc_EnableMasterIrqBit( info );
60105846 
6011
-	if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6012
-		/* Enable INTEN (Port 6, Bit12) */
6013
-		/* This connects the IRQ request signal to the ISA bus */
6014
-		usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6015
-	}
6016
-
60175847 	if (info->params.loopback) {
60185848 		info->loopback_bits = 0x300;
60195849 		outw(0x0300, info->io_base + CCAR);
....@@ -6107,12 +5937,6 @@
61075937 {
61085938 	usc_loopback_frame( info );
61095939 	usc_set_sdlc_mode( info );
6110
-
6111
-	if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6112
-		/* Enable INTEN (Port 6, Bit12) */
6113
-		/* This connects the IRQ request signal to the ISA bus */
6114
-		usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6115
-	}
61165940 
61175941 	usc_enable_aux_clock(info, info->params.clock_speed);
61185942 
....@@ -6283,11 +6107,7 @@
62836107 		 * ClkSpeed = 921600 (ISA), 691200 (PCI)
62846108 		 */
62856109 
6286
-		if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6287
-			usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6288
-		else
6289
-			usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6290
-
6110
+		usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
62916111 		
62926112 		/*
62936113 		 * Hardware Configuration Register (HCR)
....@@ -6892,10 +6712,7 @@
68926712 
68936713 		/* Actually copy data from source buffer to DMA buffer. */
68946714 		/* Also set the data count for this individual DMA buffer. */
6895
-		if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6896
-			mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6897
-		else
6898
-			memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6715
+		mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
68996716 
69006717 		pBufEntry->count = Copycount;
69016718 
....@@ -7370,9 +7187,6 @@
73707187 	unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
73717188 	unsigned long * TestAddr;
73727189 
7373
-	if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7374
-		return true;
7375
-
73767190 	TestAddr = (unsigned long *)info->memory_base;
73777191 
73787192 	/* Test data lines with test pattern at one location. */
....@@ -7605,14 +7419,14 @@
76057419 #if SYNCLINK_GENERIC_HDLC
76067420 
76077421 /**
7608
- * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7609
- * set encoding and frame check sequence (FCS) options
7422
+ * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7423
+ * @dev:      pointer to network device structure
7424
+ * @encoding: serial encoding setting
7425
+ * @parity:   FCS setting
76107426  *
7611
- * dev       pointer to network device structure
7612
- * encoding  serial encoding setting
7613
- * parity    FCS setting
7427
+ * Set encoding and frame check sequence (FCS) options.
76147428  *
7615
- * returns 0 if success, otherwise error code
7429
+ * Return: 0 if success, otherwise error code
76167430  */
76177431 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
76187432 			  unsigned short parity)
....@@ -7654,10 +7468,9 @@
76547468 }
76557469 
76567470 /**
7657
- * called by generic HDLC layer to send frame
7658
- *
7659
- * skb  socket buffer containing HDLC frame
7660
- * dev  pointer to network device structure
7471
+ * hdlcdev_xmit - called by generic HDLC layer to send a frame
7472
+ * @skb: socket buffer containing HDLC frame
7473
+ * @dev: pointer to network device structure
76617474  */
76627475 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
76637476 				      struct net_device *dev)
....@@ -7695,12 +7508,12 @@
76957508 }
76967509 
76977510 /**
7698
- * called by network layer when interface enabled
7699
- * claim resources and initialize hardware
7511
+ * hdlcdev_open - called by network layer when interface enabled
7512
+ * @dev: pointer to network device structure
77007513  *
7701
- * dev  pointer to network device structure
7514
+ * Claim resources and initialize hardware.
77027515  *
7703
- * returns 0 if success, otherwise error code
7516
+ * Return: 0 if success, otherwise error code
77047517  */
77057518 static int hdlcdev_open(struct net_device *dev)
77067519 {
....@@ -7754,12 +7567,12 @@
77547567 }
77557568 
77567569 /**
7757
- * called by network layer when interface is disabled
7758
- * shutdown hardware and release resources
7570
+ * hdlcdev_close - called by network layer when interface is disabled
7571
+ * @dev: pointer to network device structure
77597572  *
7760
- * dev  pointer to network device structure
7573
+ * Shutdown hardware and release resources.
77617574  *
7762
- * returns 0 if success, otherwise error code
7575
+ * Return: 0 if success, otherwise error code
77637576  */
77647577 static int hdlcdev_close(struct net_device *dev)
77657578 {
....@@ -7784,13 +7597,12 @@
77847597 }
77857598 
77867599 /**
7787
- * called by network layer to process IOCTL call to network device
7600
+ * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
7601
+ * @dev: pointer to network device structure
7602
+ * @ifr: pointer to network interface request structure
7603
+ * @cmd: IOCTL command code
77887604  *
7789
- * dev  pointer to network device structure
7790
- * ifr  pointer to network interface request structure
7791
- * cmd  IOCTL command code
7792
- *
7793
- * returns 0 if success, otherwise error code
7605
+ * Return: 0 if success, otherwise error code
77947606  */
77957607 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
77967608 {
....@@ -7888,11 +7700,11 @@
78887700 }
78897701 
78907702 /**
7891
- * called by network layer when transmit timeout is detected
7703
+ * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
78927704  *
7893
- * dev  pointer to network device structure
7705
+ * @dev: pointer to network device structure
78947706  */
7895
-static void hdlcdev_tx_timeout(struct net_device *dev)
7707
+static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
78967708 {
78977709 	struct mgsl_struct *info = dev_to_port(dev);
78987710 	unsigned long flags;
....@@ -7911,10 +7723,10 @@
79117723 }
79127724 
79137725 /**
7914
- * called by device driver when transmit completes
7915
- * reenable network layer transmit if stopped
7726
+ * hdlcdev_tx_done - called by device driver when transmit completes
7727
+ * @info: pointer to device instance information
79167728  *
7917
- * info  pointer to device instance information
7729
+ * Reenable network layer transmit if stopped.
79187730  */
79197731 static void hdlcdev_tx_done(struct mgsl_struct *info)
79207732 {
....@@ -7923,12 +7735,12 @@
79237735 }
79247736 
79257737 /**
7926
- * called by device driver when frame received
7927
- * pass frame to network layer
7738
+ * hdlcdev_rx - called by device driver when frame received
7739
+ * @info: pointer to device instance information
7740
+ * @buf:  pointer to buffer contianing frame data
7741
+ * @size: count of data bytes in buf
79287742  *
7929
- * info  pointer to device instance information
7930
- * buf   pointer to buffer contianing frame data
7931
- * size  count of data bytes in buf
7743
+ * Pass frame to network layer.
79327744  */
79337745 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
79347746 {
....@@ -7964,12 +7776,12 @@
79647776 };
79657777 
79667778 /**
7967
- * called by device driver when adding device instance
7968
- * do generic HDLC initialization
7779
+ * hdlcdev_init - called by device driver when adding device instance
7780
+ * @info: pointer to device instance information
79697781  *
7970
- * info  pointer to device instance information
7782
+ * Do generic HDLC initialization.
79717783  *
7972
- * returns 0 if success, otherwise error code
7784
+ * Return: 0 if success, otherwise error code
79737785  */
79747786 static int hdlcdev_init(struct mgsl_struct *info)
79757787 {
....@@ -8013,10 +7825,10 @@
80137825 }
80147826 
80157827 /**
8016
- * called by device driver when removing device instance
8017
- * do generic HDLC cleanup
7828
+ * hdlcdev_exit - called by device driver when removing device instance
7829
+ * @info: pointer to device instance information
80187830  *
8019
- * info  pointer to device instance information
7831
+ * Do generic HDLC cleanup.
80207832  */
80217833 static void hdlcdev_exit(struct mgsl_struct *info)
80227834 {
....@@ -8058,7 +7870,6 @@
80587870 	info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
80597871 	info->phys_lcr_base &= ~(PAGE_SIZE-1);
80607872 				
8061
-	info->bus_type = MGSL_BUS_TYPE_PCI;
80627873 	info->io_addr_size = 8;
80637874 	info->irq_flags = IRQF_SHARED;
80647875