forked from ~ljy/RK356X_SDK_RELEASE
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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/drivers/tty/serial/stm32-usart.c
....@@ -8,10 +8,6 @@
88  * Inspired by st-asc.c from STMicroelectronics (c)
99  */
1010 
11
-#if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12
-#define SUPPORT_SYSRQ
13
-#endif
14
-
1511 #include <linux/clk.h>
1612 #include <linux/console.h>
1713 #include <linux/delay.h>
....@@ -24,6 +20,7 @@
2420 #include <linux/module.h>
2521 #include <linux/of.h>
2622 #include <linux/of_platform.h>
23
+#include <linux/pinctrl/consumer.h>
2724 #include <linux/platform_device.h>
2825 #include <linux/pm_runtime.h>
2926 #include <linux/pm_wakeirq.h>
....@@ -34,17 +31,18 @@
3431 #include <linux/tty_flip.h>
3532 #include <linux/tty.h>
3633 
34
+#include "serial_mctrl_gpio.h"
3735 #include "stm32-usart.h"
3836 
39
-static void stm32_stop_tx(struct uart_port *port);
40
-static void stm32_transmit_chars(struct uart_port *port);
37
+static void stm32_usart_stop_tx(struct uart_port *port);
38
+static void stm32_usart_transmit_chars(struct uart_port *port);
4139 
4240 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
4341 {
4442 	return container_of(port, struct stm32_port, port);
4543 }
4644 
47
-static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
45
+static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits)
4846 {
4947 	u32 val;
5048 
....@@ -53,7 +51,7 @@
5351 	writel_relaxed(val, port->membase + reg);
5452 }
5553 
56
-static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
54
+static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits)
5755 {
5856 	u32 val;
5957 
....@@ -62,8 +60,8 @@
6260 	writel_relaxed(val, port->membase + reg);
6361 }
6462 
65
-static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
66
-				   u32 delay_DDE, u32 baud)
63
+static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
64
+					 u32 delay_DDE, u32 baud)
6765 {
6866 	u32 rs485_deat_dedt;
6967 	u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
....@@ -71,6 +69,8 @@
7169 
7270 	*cr3 |= USART_CR3_DEM;
7371 	over8 = *cr1 & USART_CR1_OVER8;
72
+
73
+	*cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
7474 
7575 	if (over8)
7676 		rs485_deat_dedt = delay_ADE * baud * 8;
....@@ -97,16 +97,16 @@
9797 	*cr1 |= rs485_deat_dedt;
9898 }
9999 
100
-static int stm32_config_rs485(struct uart_port *port,
101
-			      struct serial_rs485 *rs485conf)
100
+static int stm32_usart_config_rs485(struct uart_port *port,
101
+				    struct serial_rs485 *rs485conf)
102102 {
103103 	struct stm32_port *stm32_port = to_stm32_port(port);
104
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
105
-	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
104
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
105
+	const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
106106 	u32 usartdiv, baud, cr1, cr3;
107107 	bool over8;
108108 
109
-	stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
109
+	stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
110110 
111111 	port->rs485 = *rs485conf;
112112 
....@@ -124,9 +124,10 @@
124124 				   << USART_BRR_04_R_SHIFT;
125125 
126126 		baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
127
-		stm32_config_reg_rs485(&cr1, &cr3,
128
-				       rs485conf->delay_rts_before_send,
129
-				       rs485conf->delay_rts_after_send, baud);
127
+		stm32_usart_config_reg_rs485(&cr1, &cr3,
128
+					     rs485conf->delay_rts_before_send,
129
+					     rs485conf->delay_rts_after_send,
130
+					     baud);
130131 
131132 		if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
132133 			cr3 &= ~USART_CR3_DEP;
....@@ -139,18 +140,19 @@
139140 		writel_relaxed(cr3, port->membase + ofs->cr3);
140141 		writel_relaxed(cr1, port->membase + ofs->cr1);
141142 	} else {
142
-		stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP);
143
-		stm32_clr_bits(port, ofs->cr1,
144
-			       USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
143
+		stm32_usart_clr_bits(port, ofs->cr3,
144
+				     USART_CR3_DEM | USART_CR3_DEP);
145
+		stm32_usart_clr_bits(port, ofs->cr1,
146
+				     USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
145147 	}
146148 
147
-	stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
149
+	stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
148150 
149151 	return 0;
150152 }
151153 
152
-static int stm32_init_rs485(struct uart_port *port,
153
-			    struct platform_device *pdev)
154
+static int stm32_usart_init_rs485(struct uart_port *port,
155
+				  struct platform_device *pdev)
154156 {
155157 	struct serial_rs485 *rs485conf = &port->rs485;
156158 
....@@ -161,16 +163,14 @@
161163 	if (!pdev->dev.of_node)
162164 		return -ENODEV;
163165 
164
-	uart_get_rs485_mode(&pdev->dev, rs485conf);
165
-
166
-	return 0;
166
+	return uart_get_rs485_mode(port);
167167 }
168168 
169
-static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
170
-			    bool threaded)
169
+static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr,
170
+				  int *last_res, bool threaded)
171171 {
172172 	struct stm32_port *stm32_port = to_stm32_port(port);
173
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
173
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
174174 	enum dma_status status;
175175 	struct dma_tx_state state;
176176 
....@@ -180,8 +180,7 @@
180180 		status = dmaengine_tx_status(stm32_port->rx_ch,
181181 					     stm32_port->rx_ch->cookie,
182182 					     &state);
183
-		if ((status == DMA_IN_PROGRESS) &&
184
-		    (*last_res != state.residue))
183
+		if (status == DMA_IN_PROGRESS && (*last_res != state.residue))
185184 			return 1;
186185 		else
187186 			return 0;
....@@ -191,11 +190,11 @@
191190 	return 0;
192191 }
193192 
194
-static unsigned long stm32_get_char(struct uart_port *port, u32 *sr,
195
-				    int *last_res)
193
+static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr,
194
+					  int *last_res)
196195 {
197196 	struct stm32_port *stm32_port = to_stm32_port(port);
198
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
197
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
199198 	unsigned long c;
200199 
201200 	if (stm32_port->rx_ch) {
....@@ -211,19 +210,19 @@
211210 	return c;
212211 }
213212 
214
-static void stm32_receive_chars(struct uart_port *port, bool threaded)
213
+static void stm32_usart_receive_chars(struct uart_port *port, bool threaded)
215214 {
216215 	struct tty_port *tport = &port->state->port;
217216 	struct stm32_port *stm32_port = to_stm32_port(port);
218
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
217
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
219218 	unsigned long c;
220219 	u32 sr;
221220 	char flag;
222221 
223
-	if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
224
-		pm_wakeup_event(tport->tty->dev, 0);
222
+	spin_lock(&port->lock);
225223 
226
-	while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
224
+	while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res,
225
+				      threaded)) {
227226 		sr |= USART_SR_DUMMY_RX;
228227 		flag = TTY_NORMAL;
229228 
....@@ -242,7 +241,7 @@
242241 			writel_relaxed(sr & USART_SR_ERR_MASK,
243242 				       port->membase + ofs->icr);
244243 
245
-		c = stm32_get_char(port, &sr, &stm32_port->last_res);
244
+		c = stm32_usart_get_char(port, &sr, &stm32_port->last_res);
246245 		port->icount.rx++;
247246 		if (sr & USART_SR_ERR_MASK) {
248247 			if (sr & USART_SR_ORE) {
....@@ -278,58 +277,86 @@
278277 	}
279278 
280279 	spin_unlock(&port->lock);
280
+
281281 	tty_flip_buffer_push(tport);
282
-	spin_lock(&port->lock);
283282 }
284283 
285
-static void stm32_tx_dma_complete(void *arg)
284
+static void stm32_usart_tx_dma_complete(void *arg)
286285 {
287286 	struct uart_port *port = arg;
288287 	struct stm32_port *stm32port = to_stm32_port(port);
289
-	struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
288
+	const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
289
+	unsigned long flags;
290290 
291
-	stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
291
+	dmaengine_terminate_async(stm32port->tx_ch);
292
+	stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
292293 	stm32port->tx_dma_busy = false;
293294 
294295 	/* Let's see if we have pending data to send */
295
-	stm32_transmit_chars(port);
296
+	spin_lock_irqsave(&port->lock, flags);
297
+	stm32_usart_transmit_chars(port);
298
+	spin_unlock_irqrestore(&port->lock, flags);
296299 }
297300 
298
-static void stm32_transmit_chars_pio(struct uart_port *port)
301
+static void stm32_usart_tx_interrupt_enable(struct uart_port *port)
299302 {
300303 	struct stm32_port *stm32_port = to_stm32_port(port);
301
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
304
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
305
+
306
+	/*
307
+	 * Enables TX FIFO threashold irq when FIFO is enabled,
308
+	 * or TX empty irq when FIFO is disabled
309
+	 */
310
+	if (stm32_port->fifoen)
311
+		stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
312
+	else
313
+		stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
314
+}
315
+
316
+static void stm32_usart_tx_interrupt_disable(struct uart_port *port)
317
+{
318
+	struct stm32_port *stm32_port = to_stm32_port(port);
319
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
320
+
321
+	if (stm32_port->fifoen)
322
+		stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
323
+	else
324
+		stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
325
+}
326
+
327
+static void stm32_usart_transmit_chars_pio(struct uart_port *port)
328
+{
329
+	struct stm32_port *stm32_port = to_stm32_port(port);
330
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
302331 	struct circ_buf *xmit = &port->state->xmit;
303
-	unsigned int isr;
304
-	int ret;
305332 
306333 	if (stm32_port->tx_dma_busy) {
307
-		stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
334
+		stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
308335 		stm32_port->tx_dma_busy = false;
309336 	}
310337 
311
-	ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
312
-						isr,
313
-						(isr & USART_SR_TXE),
314
-						10, 100000);
338
+	while (!uart_circ_empty(xmit)) {
339
+		/* Check that TDR is empty before filling FIFO */
340
+		if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
341
+			break;
342
+		writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
343
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
344
+		port->icount.tx++;
345
+	}
315346 
316
-	if (ret)
317
-		dev_err(port->dev, "tx empty not set\n");
318
-
319
-	stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
320
-
321
-	writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
322
-	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
323
-	port->icount.tx++;
347
+	/* rely on TXE irq (mask or unmask) for sending remaining data */
348
+	if (uart_circ_empty(xmit))
349
+		stm32_usart_tx_interrupt_disable(port);
350
+	else
351
+		stm32_usart_tx_interrupt_enable(port);
324352 }
325353 
326
-static void stm32_transmit_chars_dma(struct uart_port *port)
354
+static void stm32_usart_transmit_chars_dma(struct uart_port *port)
327355 {
328356 	struct stm32_port *stm32port = to_stm32_port(port);
329
-	struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
357
+	const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
330358 	struct circ_buf *xmit = &port->state->xmit;
331359 	struct dma_async_tx_descriptor *desc = NULL;
332
-	dma_cookie_t cookie;
333360 	unsigned int count, i;
334361 
335362 	if (stm32port->tx_dma_busy)
....@@ -363,88 +390,115 @@
363390 					   DMA_MEM_TO_DEV,
364391 					   DMA_PREP_INTERRUPT);
365392 
366
-	if (!desc) {
367
-		for (i = count; i > 0; i--)
368
-			stm32_transmit_chars_pio(port);
369
-		return;
370
-	}
393
+	if (!desc)
394
+		goto fallback_err;
371395 
372
-	desc->callback = stm32_tx_dma_complete;
396
+	desc->callback = stm32_usart_tx_dma_complete;
373397 	desc->callback_param = port;
374398 
375399 	/* Push current DMA TX transaction in the pending queue */
376
-	cookie = dmaengine_submit(desc);
400
+	if (dma_submit_error(dmaengine_submit(desc))) {
401
+		/* dma no yet started, safe to free resources */
402
+		dmaengine_terminate_async(stm32port->tx_ch);
403
+		goto fallback_err;
404
+	}
377405 
378406 	/* Issue pending DMA TX requests */
379407 	dma_async_issue_pending(stm32port->tx_ch);
380408 
381
-	stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
409
+	stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
382410 
383411 	xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
384412 	port->icount.tx += count;
413
+	return;
414
+
415
+fallback_err:
416
+	for (i = count; i > 0; i--)
417
+		stm32_usart_transmit_chars_pio(port);
385418 }
386419 
387
-static void stm32_transmit_chars(struct uart_port *port)
420
+static void stm32_usart_transmit_chars(struct uart_port *port)
388421 {
389422 	struct stm32_port *stm32_port = to_stm32_port(port);
390
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
423
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
391424 	struct circ_buf *xmit = &port->state->xmit;
425
+	u32 isr;
426
+	int ret;
392427 
393428 	if (port->x_char) {
394429 		if (stm32_port->tx_dma_busy)
395
-			stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
430
+			stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
431
+
432
+		/* Check that TDR is empty before filling FIFO */
433
+		ret =
434
+		readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
435
+						  isr,
436
+						  (isr & USART_SR_TXE),
437
+						  10, 1000);
438
+		if (ret)
439
+			dev_warn(port->dev, "1 character may be erased\n");
440
+
396441 		writel_relaxed(port->x_char, port->membase + ofs->tdr);
397442 		port->x_char = 0;
398443 		port->icount.tx++;
399444 		if (stm32_port->tx_dma_busy)
400
-			stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
445
+			stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
401446 		return;
402447 	}
403448 
404449 	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
405
-		stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
450
+		stm32_usart_tx_interrupt_disable(port);
406451 		return;
407452 	}
408453 
409454 	if (ofs->icr == UNDEF_REG)
410
-		stm32_clr_bits(port, ofs->isr, USART_SR_TC);
455
+		stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC);
411456 	else
412457 		writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
413458 
414459 	if (stm32_port->tx_ch)
415
-		stm32_transmit_chars_dma(port);
460
+		stm32_usart_transmit_chars_dma(port);
416461 	else
417
-		stm32_transmit_chars_pio(port);
462
+		stm32_usart_transmit_chars_pio(port);
418463 
419464 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
420465 		uart_write_wakeup(port);
421466 
422467 	if (uart_circ_empty(xmit))
423
-		stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
468
+		stm32_usart_tx_interrupt_disable(port);
424469 }
425470 
426
-static irqreturn_t stm32_interrupt(int irq, void *ptr)
471
+static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
427472 {
428473 	struct uart_port *port = ptr;
474
+	struct tty_port *tport = &port->state->port;
429475 	struct stm32_port *stm32_port = to_stm32_port(port);
430
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
476
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
431477 	u32 sr;
432
-
433
-	spin_lock(&port->lock);
434478 
435479 	sr = readl_relaxed(port->membase + ofs->isr);
436480 
437
-	if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
438
-		writel_relaxed(USART_ICR_WUCF,
481
+	if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
482
+		writel_relaxed(USART_ICR_RTOCF,
439483 			       port->membase + ofs->icr);
440484 
485
+	if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) {
486
+		/* Clear wake up flag and disable wake up interrupt */
487
+		writel_relaxed(USART_ICR_WUCF,
488
+			       port->membase + ofs->icr);
489
+		stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
490
+		if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
491
+			pm_wakeup_event(tport->tty->dev, 0);
492
+	}
493
+
441494 	if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
442
-		stm32_receive_chars(port, false);
495
+		stm32_usart_receive_chars(port, false);
443496 
444
-	if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
445
-		stm32_transmit_chars(port);
446
-
447
-	spin_unlock(&port->lock);
497
+	if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) {
498
+		spin_lock(&port->lock);
499
+		stm32_usart_transmit_chars(port);
500
+		spin_unlock(&port->lock);
501
+	}
448502 
449503 	if (stm32_port->rx_ch)
450504 		return IRQ_WAKE_THREAD;
....@@ -452,25 +506,21 @@
452506 		return IRQ_HANDLED;
453507 }
454508 
455
-static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
509
+static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr)
456510 {
457511 	struct uart_port *port = ptr;
458512 	struct stm32_port *stm32_port = to_stm32_port(port);
459513 
460
-	spin_lock(&port->lock);
461
-
462514 	if (stm32_port->rx_ch)
463
-		stm32_receive_chars(port, true);
464
-
465
-	spin_unlock(&port->lock);
515
+		stm32_usart_receive_chars(port, true);
466516 
467517 	return IRQ_HANDLED;
468518 }
469519 
470
-static unsigned int stm32_tx_empty(struct uart_port *port)
520
+static unsigned int stm32_usart_tx_empty(struct uart_port *port)
471521 {
472522 	struct stm32_port *stm32_port = to_stm32_port(port);
473
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
523
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
474524 
475525 	if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
476526 		return TIOCSER_TEMT;
....@@ -478,112 +528,168 @@
478528 	return 0;
479529 }
480530 
481
-static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
531
+static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
482532 {
483533 	struct stm32_port *stm32_port = to_stm32_port(port);
484
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
534
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
485535 
486536 	if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
487
-		stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
537
+		stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE);
488538 	else
489
-		stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
539
+		stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
540
+
541
+	mctrl_gpio_set(stm32_port->gpios, mctrl);
490542 }
491543 
492
-static unsigned int stm32_get_mctrl(struct uart_port *port)
544
+static unsigned int stm32_usart_get_mctrl(struct uart_port *port)
493545 {
546
+	struct stm32_port *stm32_port = to_stm32_port(port);
547
+	unsigned int ret;
548
+
494549 	/* This routine is used to get signals of: DCD, DSR, RI, and CTS */
495
-	return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
550
+	ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
551
+
552
+	return mctrl_gpio_get(stm32_port->gpios, &ret);
553
+}
554
+
555
+static void stm32_usart_enable_ms(struct uart_port *port)
556
+{
557
+	mctrl_gpio_enable_ms(to_stm32_port(port)->gpios);
558
+}
559
+
560
+static void stm32_usart_disable_ms(struct uart_port *port)
561
+{
562
+	mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
496563 }
497564 
498565 /* Transmit stop */
499
-static void stm32_stop_tx(struct uart_port *port)
566
+static void stm32_usart_stop_tx(struct uart_port *port)
500567 {
501568 	struct stm32_port *stm32_port = to_stm32_port(port);
502
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
569
+	struct serial_rs485 *rs485conf = &port->rs485;
503570 
504
-	stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
571
+	stm32_usart_tx_interrupt_disable(port);
572
+
573
+	if (rs485conf->flags & SER_RS485_ENABLED) {
574
+		if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
575
+			mctrl_gpio_set(stm32_port->gpios,
576
+					stm32_port->port.mctrl & ~TIOCM_RTS);
577
+		} else {
578
+			mctrl_gpio_set(stm32_port->gpios,
579
+					stm32_port->port.mctrl | TIOCM_RTS);
580
+		}
581
+	}
505582 }
506583 
507584 /* There are probably characters waiting to be transmitted. */
508
-static void stm32_start_tx(struct uart_port *port)
585
+static void stm32_usart_start_tx(struct uart_port *port)
509586 {
587
+	struct stm32_port *stm32_port = to_stm32_port(port);
588
+	struct serial_rs485 *rs485conf = &port->rs485;
510589 	struct circ_buf *xmit = &port->state->xmit;
511590 
512591 	if (uart_circ_empty(xmit) && !port->x_char)
513592 		return;
514593 
515
-	stm32_transmit_chars(port);
594
+	if (rs485conf->flags & SER_RS485_ENABLED) {
595
+		if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
596
+			mctrl_gpio_set(stm32_port->gpios,
597
+					stm32_port->port.mctrl | TIOCM_RTS);
598
+		} else {
599
+			mctrl_gpio_set(stm32_port->gpios,
600
+					stm32_port->port.mctrl & ~TIOCM_RTS);
601
+		}
602
+	}
603
+
604
+	stm32_usart_transmit_chars(port);
516605 }
517606 
518607 /* Throttle the remote when input buffer is about to overflow. */
519
-static void stm32_throttle(struct uart_port *port)
608
+static void stm32_usart_throttle(struct uart_port *port)
520609 {
521610 	struct stm32_port *stm32_port = to_stm32_port(port);
522
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
611
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
523612 	unsigned long flags;
524613 
525614 	spin_lock_irqsave(&port->lock, flags);
526
-	stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
615
+	stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
616
+	if (stm32_port->cr3_irq)
617
+		stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
618
+
527619 	spin_unlock_irqrestore(&port->lock, flags);
528620 }
529621 
530622 /* Unthrottle the remote, the input buffer can now accept data. */
531
-static void stm32_unthrottle(struct uart_port *port)
623
+static void stm32_usart_unthrottle(struct uart_port *port)
532624 {
533625 	struct stm32_port *stm32_port = to_stm32_port(port);
534
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
626
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
535627 	unsigned long flags;
536628 
537629 	spin_lock_irqsave(&port->lock, flags);
538
-	stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);
630
+	stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
631
+	if (stm32_port->cr3_irq)
632
+		stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
633
+
539634 	spin_unlock_irqrestore(&port->lock, flags);
540635 }
541636 
542637 /* Receive stop */
543
-static void stm32_stop_rx(struct uart_port *port)
638
+static void stm32_usart_stop_rx(struct uart_port *port)
544639 {
545640 	struct stm32_port *stm32_port = to_stm32_port(port);
546
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
641
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
547642 
548
-	stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
643
+	stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
644
+	if (stm32_port->cr3_irq)
645
+		stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
549646 }
550647 
551648 /* Handle breaks - ignored by us */
552
-static void stm32_break_ctl(struct uart_port *port, int break_state)
649
+static void stm32_usart_break_ctl(struct uart_port *port, int break_state)
553650 {
554651 }
555652 
556
-static int stm32_startup(struct uart_port *port)
653
+static int stm32_usart_startup(struct uart_port *port)
557654 {
558655 	struct stm32_port *stm32_port = to_stm32_port(port);
559
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
656
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
657
+	const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
560658 	const char *name = to_platform_device(port->dev)->name;
561659 	u32 val;
562660 	int ret;
563661 
564
-	ret = request_threaded_irq(port->irq, stm32_interrupt,
565
-				   stm32_threaded_interrupt,
566
-				   IRQF_NO_SUSPEND, name, port);
662
+	ret = request_threaded_irq(port->irq, stm32_usart_interrupt,
663
+				   stm32_usart_threaded_interrupt,
664
+				   IRQF_ONESHOT | IRQF_NO_SUSPEND,
665
+				   name, port);
567666 	if (ret)
568667 		return ret;
569668 
570
-	val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
571
-	if (stm32_port->fifoen)
572
-		val |= USART_CR1_FIFOEN;
573
-	stm32_set_bits(port, ofs->cr1, val);
669
+	/* RX FIFO Flush */
670
+	if (ofs->rqr != UNDEF_REG)
671
+		writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
672
+
673
+	/* RX enabling */
674
+	val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit);
675
+	stm32_usart_set_bits(port, ofs->cr1, val);
574676 
575677 	return 0;
576678 }
577679 
578
-static void stm32_shutdown(struct uart_port *port)
680
+static void stm32_usart_shutdown(struct uart_port *port)
579681 {
580682 	struct stm32_port *stm32_port = to_stm32_port(port);
581
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
582
-	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
683
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
684
+	const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
583685 	u32 val, isr;
584686 	int ret;
585687 
586
-	val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
688
+	/* Disable modem control interrupts */
689
+	stm32_usart_disable_ms(port);
690
+
691
+	val = USART_CR1_TXEIE | USART_CR1_TE;
692
+	val |= stm32_port->cr1_irq | USART_CR1_RE;
587693 	val |= BIT(cfg->uart_enable_bit);
588694 	if (stm32_port->fifoen)
589695 		val |= USART_CR1_FIFOEN;
....@@ -595,12 +701,17 @@
595701 	if (ret)
596702 		dev_err(port->dev, "transmission complete not set\n");
597703 
598
-	stm32_clr_bits(port, ofs->cr1, val);
704
+	/* flush RX & TX FIFO */
705
+	if (ofs->rqr != UNDEF_REG)
706
+		writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
707
+			       port->membase + ofs->rqr);
708
+
709
+	stm32_usart_clr_bits(port, ofs->cr1, val);
599710 
600711 	free_irq(port->irq, port);
601712 }
602713 
603
-unsigned int stm32_get_databits(struct ktermios *termios)
714
+static unsigned int stm32_usart_get_databits(struct ktermios *termios)
604715 {
605716 	unsigned int bits;
606717 
....@@ -630,12 +741,13 @@
630741 	return bits;
631742 }
632743 
633
-static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
634
-			    struct ktermios *old)
744
+static void stm32_usart_set_termios(struct uart_port *port,
745
+				    struct ktermios *termios,
746
+				    struct ktermios *old)
635747 {
636748 	struct stm32_port *stm32_port = to_stm32_port(port);
637
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
638
-	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
749
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
750
+	const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
639751 	struct serial_rs485 *rs485conf = &port->rs485;
640752 	unsigned int baud, bits;
641753 	u32 usartdiv, mantissa, fraction, oversampling;
....@@ -663,17 +775,29 @@
663775 	/* Stop serial port and reset value */
664776 	writel_relaxed(0, port->membase + ofs->cr1);
665777 
666
-	cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
778
+	/* flush RX & TX FIFO */
779
+	if (ofs->rqr != UNDEF_REG)
780
+		writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
781
+			       port->membase + ofs->rqr);
667782 
783
+	cr1 = USART_CR1_TE | USART_CR1_RE;
668784 	if (stm32_port->fifoen)
669785 		cr1 |= USART_CR1_FIFOEN;
670786 	cr2 = 0;
671
-	cr3 = 0;
787
+
788
+	/* Tx and RX FIFO configuration */
789
+	cr3 = readl_relaxed(port->membase + ofs->cr3);
790
+	cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE;
791
+	if (stm32_port->fifoen) {
792
+		cr3 &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);
793
+		cr3 |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;
794
+		cr3 |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT;
795
+	}
672796 
673797 	if (cflag & CSTOPB)
674798 		cr2 |= USART_CR2_STOP_2B;
675799 
676
-	bits = stm32_get_databits(termios);
800
+	bits = stm32_usart_get_databits(termios);
677801 	stm32_port->rdr_mask = (BIT(bits) - 1);
678802 
679803 	if (cflag & PARENB) {
....@@ -688,13 +812,41 @@
688812 	 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
689813 	 * M0 and M1 already cleared by cr1 initialization.
690814 	 */
691
-	if (bits == 9)
815
+	if (bits == 9) {
692816 		cr1 |= USART_CR1_M0;
693
-	else if ((bits == 7) && cfg->has_7bits_data)
817
+	} else if ((bits == 7) && cfg->has_7bits_data) {
694818 		cr1 |= USART_CR1_M1;
695
-	else if (bits != 8)
819
+	} else if (bits != 8) {
696820 		dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
697821 			, bits);
822
+		cflag &= ~CSIZE;
823
+		cflag |= CS8;
824
+		termios->c_cflag = cflag;
825
+		bits = 8;
826
+		if (cflag & PARENB) {
827
+			bits++;
828
+			cr1 |= USART_CR1_M0;
829
+		}
830
+	}
831
+
832
+	if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
833
+				       stm32_port->fifoen)) {
834
+		if (cflag & CSTOPB)
835
+			bits = bits + 3; /* 1 start bit + 2 stop bits */
836
+		else
837
+			bits = bits + 2; /* 1 start bit + 1 stop bit */
838
+
839
+		/* RX timeout irq to occur after last stop bit + bits */
840
+		stm32_port->cr1_irq = USART_CR1_RTOIE;
841
+		writel_relaxed(bits, port->membase + ofs->rtor);
842
+		cr2 |= USART_CR2_RTOEN;
843
+		/* Not using dma, enable fifo threshold irq */
844
+		if (!stm32_port->rx_ch)
845
+			stm32_port->cr3_irq =  USART_CR3_RXFTIE;
846
+	}
847
+
848
+	cr1 |= stm32_port->cr1_irq;
849
+	cr3 |= stm32_port->cr3_irq;
698850 
699851 	if (cflag & PARODD)
700852 		cr1 |= USART_CR1_PS;
....@@ -716,11 +868,11 @@
716868 	if (usartdiv < 16) {
717869 		oversampling = 8;
718870 		cr1 |= USART_CR1_OVER8;
719
-		stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
871
+		stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8);
720872 	} else {
721873 		oversampling = 16;
722874 		cr1 &= ~USART_CR1_OVER8;
723
-		stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
875
+		stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
724876 	}
725877 
726878 	mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
....@@ -757,9 +909,10 @@
757909 		cr3 |= USART_CR3_DMAR;
758910 
759911 	if (rs485conf->flags & SER_RS485_ENABLED) {
760
-		stm32_config_reg_rs485(&cr1, &cr3,
761
-				       rs485conf->delay_rts_before_send,
762
-				       rs485conf->delay_rts_after_send, baud);
912
+		stm32_usart_config_reg_rs485(&cr1, &cr3,
913
+					     rs485conf->delay_rts_before_send,
914
+					     rs485conf->delay_rts_after_send,
915
+					     baud);
763916 		if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
764917 			cr3 &= ~USART_CR3_DEP;
765918 			rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
....@@ -773,101 +926,127 @@
773926 		cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
774927 	}
775928 
929
+	/* Configure wake up from low power on start bit detection */
930
+	if (stm32_port->wakeirq > 0) {
931
+		cr3 &= ~USART_CR3_WUS_MASK;
932
+		cr3 |= USART_CR3_WUS_START_BIT;
933
+	}
934
+
776935 	writel_relaxed(cr3, port->membase + ofs->cr3);
777936 	writel_relaxed(cr2, port->membase + ofs->cr2);
778937 	writel_relaxed(cr1, port->membase + ofs->cr1);
779938 
780
-	stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
939
+	stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
781940 	spin_unlock_irqrestore(&port->lock, flags);
941
+
942
+	/* Handle modem control interrupts */
943
+	if (UART_ENABLE_MS(port, termios->c_cflag))
944
+		stm32_usart_enable_ms(port);
945
+	else
946
+		stm32_usart_disable_ms(port);
782947 }
783948 
784
-static const char *stm32_type(struct uart_port *port)
949
+static const char *stm32_usart_type(struct uart_port *port)
785950 {
786951 	return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
787952 }
788953 
789
-static void stm32_release_port(struct uart_port *port)
954
+static void stm32_usart_release_port(struct uart_port *port)
790955 {
791956 }
792957 
793
-static int stm32_request_port(struct uart_port *port)
958
+static int stm32_usart_request_port(struct uart_port *port)
794959 {
795960 	return 0;
796961 }
797962 
798
-static void stm32_config_port(struct uart_port *port, int flags)
963
+static void stm32_usart_config_port(struct uart_port *port, int flags)
799964 {
800965 	if (flags & UART_CONFIG_TYPE)
801966 		port->type = PORT_STM32;
802967 }
803968 
804969 static int
805
-stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
970
+stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser)
806971 {
807972 	/* No user changeable parameters */
808973 	return -EINVAL;
809974 }
810975 
811
-static void stm32_pm(struct uart_port *port, unsigned int state,
812
-		unsigned int oldstate)
976
+static void stm32_usart_pm(struct uart_port *port, unsigned int state,
977
+			   unsigned int oldstate)
813978 {
814979 	struct stm32_port *stm32port = container_of(port,
815980 			struct stm32_port, port);
816
-	struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
817
-	struct stm32_usart_config *cfg = &stm32port->info->cfg;
981
+	const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
982
+	const struct stm32_usart_config *cfg = &stm32port->info->cfg;
818983 	unsigned long flags = 0;
819984 
820985 	switch (state) {
821986 	case UART_PM_STATE_ON:
822
-		clk_prepare_enable(stm32port->clk);
987
+		pm_runtime_get_sync(port->dev);
823988 		break;
824989 	case UART_PM_STATE_OFF:
825990 		spin_lock_irqsave(&port->lock, flags);
826
-		stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
991
+		stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
827992 		spin_unlock_irqrestore(&port->lock, flags);
828
-		clk_disable_unprepare(stm32port->clk);
993
+		pm_runtime_put_sync(port->dev);
829994 		break;
830995 	}
831996 }
832997 
833998 static const struct uart_ops stm32_uart_ops = {
834
-	.tx_empty	= stm32_tx_empty,
835
-	.set_mctrl	= stm32_set_mctrl,
836
-	.get_mctrl	= stm32_get_mctrl,
837
-	.stop_tx	= stm32_stop_tx,
838
-	.start_tx	= stm32_start_tx,
839
-	.throttle	= stm32_throttle,
840
-	.unthrottle	= stm32_unthrottle,
841
-	.stop_rx	= stm32_stop_rx,
842
-	.break_ctl	= stm32_break_ctl,
843
-	.startup	= stm32_startup,
844
-	.shutdown	= stm32_shutdown,
845
-	.set_termios	= stm32_set_termios,
846
-	.pm		= stm32_pm,
847
-	.type		= stm32_type,
848
-	.release_port	= stm32_release_port,
849
-	.request_port	= stm32_request_port,
850
-	.config_port	= stm32_config_port,
851
-	.verify_port	= stm32_verify_port,
999
+	.tx_empty	= stm32_usart_tx_empty,
1000
+	.set_mctrl	= stm32_usart_set_mctrl,
1001
+	.get_mctrl	= stm32_usart_get_mctrl,
1002
+	.stop_tx	= stm32_usart_stop_tx,
1003
+	.start_tx	= stm32_usart_start_tx,
1004
+	.throttle	= stm32_usart_throttle,
1005
+	.unthrottle	= stm32_usart_unthrottle,
1006
+	.stop_rx	= stm32_usart_stop_rx,
1007
+	.enable_ms	= stm32_usart_enable_ms,
1008
+	.break_ctl	= stm32_usart_break_ctl,
1009
+	.startup	= stm32_usart_startup,
1010
+	.shutdown	= stm32_usart_shutdown,
1011
+	.set_termios	= stm32_usart_set_termios,
1012
+	.pm		= stm32_usart_pm,
1013
+	.type		= stm32_usart_type,
1014
+	.release_port	= stm32_usart_release_port,
1015
+	.request_port	= stm32_usart_request_port,
1016
+	.config_port	= stm32_usart_config_port,
1017
+	.verify_port	= stm32_usart_verify_port,
8521018 };
8531019 
854
-static int stm32_init_port(struct stm32_port *stm32port,
855
-			  struct platform_device *pdev)
1020
+static int stm32_usart_init_port(struct stm32_port *stm32port,
1021
+				 struct platform_device *pdev)
8561022 {
8571023 	struct uart_port *port = &stm32port->port;
8581024 	struct resource *res;
8591025 	int ret;
8601026 
1027
+	ret = platform_get_irq(pdev, 0);
1028
+	if (ret <= 0)
1029
+		return ret ? : -ENODEV;
1030
+
8611031 	port->iotype	= UPIO_MEM;
8621032 	port->flags	= UPF_BOOT_AUTOCONF;
8631033 	port->ops	= &stm32_uart_ops;
8641034 	port->dev	= &pdev->dev;
865
-	port->irq	= platform_get_irq(pdev, 0);
866
-	port->rs485_config = stm32_config_rs485;
1035
+	port->fifosize	= stm32port->info->cfg.fifosize;
1036
+	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
1037
+	port->irq = ret;
1038
+	port->rs485_config = stm32_usart_config_rs485;
8671039 
868
-	stm32_init_rs485(port, pdev);
1040
+	ret = stm32_usart_init_rs485(port, pdev);
1041
+	if (ret)
1042
+		return ret;
8691043 
870
-	stm32port->wakeirq = platform_get_irq(pdev, 1);
1044
+	if (stm32port->info->cfg.has_wakeup) {
1045
+		stm32port->wakeirq = platform_get_irq_optional(pdev, 1);
1046
+		if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO)
1047
+			return stm32port->wakeirq ? : -ENODEV;
1048
+	}
1049
+
8711050 	stm32port->fifoen = stm32port->info->cfg.has_fifo;
8721051 
8731052 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
....@@ -889,14 +1068,35 @@
8891068 
8901069 	stm32port->port.uartclk = clk_get_rate(stm32port->clk);
8911070 	if (!stm32port->port.uartclk) {
892
-		clk_disable_unprepare(stm32port->clk);
8931071 		ret = -EINVAL;
1072
+		goto err_clk;
8941073 	}
1074
+
1075
+	stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1076
+	if (IS_ERR(stm32port->gpios)) {
1077
+		ret = PTR_ERR(stm32port->gpios);
1078
+		goto err_clk;
1079
+	}
1080
+
1081
+	/* Both CTS/RTS gpios and "st,hw-flow-ctrl" should not be specified */
1082
+	if (stm32port->hw_flow_control) {
1083
+		if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) ||
1084
+		    mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) {
1085
+			dev_err(&pdev->dev, "Conflicting RTS/CTS config\n");
1086
+			ret = -EINVAL;
1087
+			goto err_clk;
1088
+		}
1089
+	}
1090
+
1091
+	return ret;
1092
+
1093
+err_clk:
1094
+	clk_disable_unprepare(stm32port->clk);
8951095 
8961096 	return ret;
8971097 }
8981098 
899
-static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
1099
+static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev)
9001100 {
9011101 	struct device_node *np = pdev->dev.of_node;
9021102 	int id;
....@@ -913,9 +1113,12 @@
9131113 	if (WARN_ON(id >= STM32_MAX_PORTS))
9141114 		return NULL;
9151115 
916
-	stm32_ports[id].hw_flow_control = of_property_read_bool(np,
917
-							"st,hw-flow-ctrl");
1116
+	stm32_ports[id].hw_flow_control =
1117
+		of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ ||
1118
+		of_property_read_bool (np, "uart-has-rtscts");
9181119 	stm32_ports[id].port.line = id;
1120
+	stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
1121
+	stm32_ports[id].cr3_irq = 0;
9191122 	stm32_ports[id].last_res = RX_BUF_L;
9201123 	return &stm32_ports[id];
9211124 }
....@@ -931,16 +1134,22 @@
9311134 MODULE_DEVICE_TABLE(of, stm32_match);
9321135 #endif
9331136 
934
-static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
935
-				 struct platform_device *pdev)
1137
+static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port,
1138
+				       struct platform_device *pdev)
9361139 {
937
-	struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1140
+	const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
9381141 	struct uart_port *port = &stm32port->port;
9391142 	struct device *dev = &pdev->dev;
9401143 	struct dma_slave_config config;
9411144 	struct dma_async_tx_descriptor *desc = NULL;
942
-	dma_cookie_t cookie;
9431145 	int ret;
1146
+
1147
+	/*
1148
+	 * Using DMA and threaded handler for the console could lead to
1149
+	 * deadlocks.
1150
+	 */
1151
+	if (uart_console(port))
1152
+		return -ENODEV;
9441153 
9451154 	/* Request DMA RX channel */
9461155 	stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
....@@ -949,8 +1158,8 @@
9491158 		return -ENODEV;
9501159 	}
9511160 	stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
952
-						 &stm32port->rx_dma_buf,
953
-						 GFP_KERNEL);
1161
+					       &stm32port->rx_dma_buf,
1162
+					       GFP_KERNEL);
9541163 	if (!stm32port->rx_buf) {
9551164 		ret = -ENOMEM;
9561165 		goto alloc_err;
....@@ -984,7 +1193,11 @@
9841193 	desc->callback_param = NULL;
9851194 
9861195 	/* Push current DMA transaction in the pending queue */
987
-	cookie = dmaengine_submit(desc);
1196
+	ret = dma_submit_error(dmaengine_submit(desc));
1197
+	if (ret) {
1198
+		dmaengine_terminate_sync(stm32port->rx_ch);
1199
+		goto config_err;
1200
+	}
9881201 
9891202 	/* Issue pending DMA requests */
9901203 	dma_async_issue_pending(stm32port->rx_ch);
....@@ -1003,10 +1216,10 @@
10031216 	return ret;
10041217 }
10051218 
1006
-static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
1007
-				 struct platform_device *pdev)
1219
+static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port,
1220
+				       struct platform_device *pdev)
10081221 {
1009
-	struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1222
+	const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
10101223 	struct uart_port *port = &stm32port->port;
10111224 	struct device *dev = &pdev->dev;
10121225 	struct dma_slave_config config;
....@@ -1021,8 +1234,8 @@
10211234 		return -ENODEV;
10221235 	}
10231236 	stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1024
-						 &stm32port->tx_dma_buf,
1025
-						 GFP_KERNEL);
1237
+					       &stm32port->tx_dma_buf,
1238
+					       GFP_KERNEL);
10261239 	if (!stm32port->tx_buf) {
10271240 		ret = -ENOMEM;
10281241 		goto alloc_err;
....@@ -1054,27 +1267,24 @@
10541267 	return ret;
10551268 }
10561269 
1057
-static int stm32_serial_probe(struct platform_device *pdev)
1270
+static int stm32_usart_serial_probe(struct platform_device *pdev)
10581271 {
1059
-	const struct of_device_id *match;
10601272 	struct stm32_port *stm32port;
10611273 	int ret;
10621274 
1063
-	stm32port = stm32_of_get_stm32_port(pdev);
1275
+	stm32port = stm32_usart_of_get_port(pdev);
10641276 	if (!stm32port)
10651277 		return -ENODEV;
10661278 
1067
-	match = of_match_device(stm32_match, &pdev->dev);
1068
-	if (match && match->data)
1069
-		stm32port->info = (struct stm32_usart_info *)match->data;
1070
-	else
1279
+	stm32port->info = of_device_get_match_data(&pdev->dev);
1280
+	if (!stm32port->info)
10711281 		return -EINVAL;
10721282 
1073
-	ret = stm32_init_port(stm32port, pdev);
1283
+	ret = stm32_usart_init_port(stm32port, pdev);
10741284 	if (ret)
10751285 		return ret;
10761286 
1077
-	if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) {
1287
+	if (stm32port->wakeirq > 0) {
10781288 		ret = device_init_wakeup(&pdev->dev, true);
10791289 		if (ret)
10801290 			goto err_uninit;
....@@ -1087,28 +1297,58 @@
10871297 		device_set_wakeup_enable(&pdev->dev, false);
10881298 	}
10891299 
1090
-	ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1091
-	if (ret)
1092
-		goto err_wirq;
1093
-
1094
-	ret = stm32_of_dma_rx_probe(stm32port, pdev);
1300
+	ret = stm32_usart_of_dma_rx_probe(stm32port, pdev);
10951301 	if (ret)
10961302 		dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
10971303 
1098
-	ret = stm32_of_dma_tx_probe(stm32port, pdev);
1304
+	ret = stm32_usart_of_dma_tx_probe(stm32port, pdev);
10991305 	if (ret)
11001306 		dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
11011307 
11021308 	platform_set_drvdata(pdev, &stm32port->port);
11031309 
1310
+	pm_runtime_get_noresume(&pdev->dev);
1311
+	pm_runtime_set_active(&pdev->dev);
1312
+	pm_runtime_enable(&pdev->dev);
1313
+
1314
+	ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1315
+	if (ret)
1316
+		goto err_port;
1317
+
1318
+	pm_runtime_put_sync(&pdev->dev);
1319
+
11041320 	return 0;
11051321 
1106
-err_wirq:
1107
-	if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
1322
+err_port:
1323
+	pm_runtime_disable(&pdev->dev);
1324
+	pm_runtime_set_suspended(&pdev->dev);
1325
+	pm_runtime_put_noidle(&pdev->dev);
1326
+
1327
+	if (stm32port->rx_ch) {
1328
+		dmaengine_terminate_async(stm32port->rx_ch);
1329
+		dma_release_channel(stm32port->rx_ch);
1330
+	}
1331
+
1332
+	if (stm32port->rx_dma_buf)
1333
+		dma_free_coherent(&pdev->dev,
1334
+				  RX_BUF_L, stm32port->rx_buf,
1335
+				  stm32port->rx_dma_buf);
1336
+
1337
+	if (stm32port->tx_ch) {
1338
+		dmaengine_terminate_async(stm32port->tx_ch);
1339
+		dma_release_channel(stm32port->tx_ch);
1340
+	}
1341
+
1342
+	if (stm32port->tx_dma_buf)
1343
+		dma_free_coherent(&pdev->dev,
1344
+				  TX_BUF_L, stm32port->tx_buf,
1345
+				  stm32port->tx_dma_buf);
1346
+
1347
+	if (stm32port->wakeirq > 0)
11081348 		dev_pm_clear_wake_irq(&pdev->dev);
11091349 
11101350 err_nowup:
1111
-	if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
1351
+	if (stm32port->wakeirq > 0)
11121352 		device_init_wakeup(&pdev->dev, false);
11131353 
11141354 err_uninit:
....@@ -1117,49 +1357,61 @@
11171357 	return ret;
11181358 }
11191359 
1120
-static int stm32_serial_remove(struct platform_device *pdev)
1360
+static int stm32_usart_serial_remove(struct platform_device *pdev)
11211361 {
11221362 	struct uart_port *port = platform_get_drvdata(pdev);
11231363 	struct stm32_port *stm32_port = to_stm32_port(port);
1124
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1125
-	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1364
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1365
+	int err;
11261366 
1127
-	stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1367
+	pm_runtime_get_sync(&pdev->dev);
1368
+	err = uart_remove_one_port(&stm32_usart_driver, port);
1369
+	if (err)
1370
+		return(err);
11281371 
1129
-	if (stm32_port->rx_ch)
1372
+	pm_runtime_disable(&pdev->dev);
1373
+	pm_runtime_set_suspended(&pdev->dev);
1374
+	pm_runtime_put_noidle(&pdev->dev);
1375
+
1376
+	stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1377
+
1378
+	if (stm32_port->rx_ch) {
1379
+		dmaengine_terminate_async(stm32_port->rx_ch);
11301380 		dma_release_channel(stm32_port->rx_ch);
1381
+	}
11311382 
11321383 	if (stm32_port->rx_dma_buf)
11331384 		dma_free_coherent(&pdev->dev,
11341385 				  RX_BUF_L, stm32_port->rx_buf,
11351386 				  stm32_port->rx_dma_buf);
11361387 
1137
-	stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1388
+	stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
11381389 
1139
-	if (stm32_port->tx_ch)
1390
+	if (stm32_port->tx_ch) {
1391
+		dmaengine_terminate_async(stm32_port->tx_ch);
11401392 		dma_release_channel(stm32_port->tx_ch);
1393
+	}
11411394 
11421395 	if (stm32_port->tx_dma_buf)
11431396 		dma_free_coherent(&pdev->dev,
11441397 				  TX_BUF_L, stm32_port->tx_buf,
11451398 				  stm32_port->tx_dma_buf);
11461399 
1147
-	if (cfg->has_wakeup && stm32_port->wakeirq >= 0) {
1400
+	if (stm32_port->wakeirq > 0) {
11481401 		dev_pm_clear_wake_irq(&pdev->dev);
11491402 		device_init_wakeup(&pdev->dev, false);
11501403 	}
11511404 
11521405 	clk_disable_unprepare(stm32_port->clk);
11531406 
1154
-	return uart_remove_one_port(&stm32_usart_driver, port);
1407
+	return 0;
11551408 }
11561409 
1157
-
11581410 #ifdef CONFIG_SERIAL_STM32_CONSOLE
1159
-static void stm32_console_putchar(struct uart_port *port, int ch)
1411
+static void stm32_usart_console_putchar(struct uart_port *port, int ch)
11601412 {
11611413 	struct stm32_port *stm32_port = to_stm32_port(port);
1162
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1414
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
11631415 
11641416 	while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
11651417 		cpu_relax();
....@@ -1167,12 +1419,13 @@
11671419 	writel_relaxed(ch, port->membase + ofs->tdr);
11681420 }
11691421 
1170
-static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
1422
+static void stm32_usart_console_write(struct console *co, const char *s,
1423
+				      unsigned int cnt)
11711424 {
11721425 	struct uart_port *port = &stm32_ports[co->index].port;
11731426 	struct stm32_port *stm32_port = to_stm32_port(port);
1174
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1175
-	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1427
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1428
+	const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
11761429 	unsigned long flags;
11771430 	u32 old_cr1, new_cr1;
11781431 	int locked = 1;
....@@ -1191,7 +1444,7 @@
11911444 	new_cr1 |=  USART_CR1_TE | BIT(cfg->uart_enable_bit);
11921445 	writel_relaxed(new_cr1, port->membase + ofs->cr1);
11931446 
1194
-	uart_console_write(port, s, cnt, stm32_console_putchar);
1447
+	uart_console_write(port, s, cnt, stm32_usart_console_putchar);
11951448 
11961449 	/* Restore interrupt state */
11971450 	writel_relaxed(old_cr1, port->membase + ofs->cr1);
....@@ -1201,7 +1454,7 @@
12011454 	local_irq_restore(flags);
12021455 }
12031456 
1204
-static int stm32_console_setup(struct console *co, char *options)
1457
+static int stm32_usart_console_setup(struct console *co, char *options)
12051458 {
12061459 	struct stm32_port *stm32port;
12071460 	int baud = 9600;
....@@ -1220,7 +1473,7 @@
12201473 	 * this to be called during the uart port registration when the
12211474 	 * driver gets probed and the port should be mapped at that point.
12221475 	 */
1223
-	if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1476
+	if (stm32port->port.mapbase == 0 || !stm32port->port.membase)
12241477 		return -ENXIO;
12251478 
12261479 	if (options)
....@@ -1232,8 +1485,8 @@
12321485 static struct console stm32_console = {
12331486 	.name		= STM32_SERIAL_NAME,
12341487 	.device		= uart_console_device,
1235
-	.write		= stm32_console_write,
1236
-	.setup		= stm32_console_setup,
1488
+	.write		= stm32_usart_console_write,
1489
+	.setup		= stm32_usart_console_setup,
12371490 	.flags		= CON_PRINTBUFFER,
12381491 	.index		= -1,
12391492 	.data		= &stm32_usart_driver,
....@@ -1254,63 +1507,97 @@
12541507 	.cons		= STM32_SERIAL_CONSOLE,
12551508 };
12561509 
1257
-#ifdef CONFIG_PM_SLEEP
1258
-static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable)
1510
+static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
1511
+							bool enable)
12591512 {
12601513 	struct stm32_port *stm32_port = to_stm32_port(port);
1261
-	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1262
-	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1263
-	u32 val;
1514
+	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
12641515 
1265
-	if (!cfg->has_wakeup || stm32_port->wakeirq < 0)
1516
+	if (stm32_port->wakeirq <= 0)
12661517 		return;
12671518 
1519
+	/*
1520
+	 * Enable low-power wake-up and wake-up irq if argument is set to
1521
+	 * "enable", disable low-power wake-up and wake-up irq otherwise
1522
+	 */
12681523 	if (enable) {
1269
-		stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1270
-		stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1271
-		val = readl_relaxed(port->membase + ofs->cr3);
1272
-		val &= ~USART_CR3_WUS_MASK;
1273
-		/* Enable Wake up interrupt from low power on start bit */
1274
-		val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1275
-		writel_relaxed(val, port->membase + ofs->cr3);
1276
-		stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1524
+		stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);
1525
+		stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE);
12771526 	} else {
1278
-		stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1527
+		stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1528
+		stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
12791529 	}
12801530 }
12811531 
1282
-static int stm32_serial_suspend(struct device *dev)
1532
+static int __maybe_unused stm32_usart_serial_suspend(struct device *dev)
12831533 {
12841534 	struct uart_port *port = dev_get_drvdata(dev);
12851535 
12861536 	uart_suspend_port(&stm32_usart_driver, port);
12871537 
12881538 	if (device_may_wakeup(dev))
1289
-		stm32_serial_enable_wakeup(port, true);
1539
+		stm32_usart_serial_en_wakeup(port, true);
12901540 	else
1291
-		stm32_serial_enable_wakeup(port, false);
1541
+		stm32_usart_serial_en_wakeup(port, false);
1542
+
1543
+	/*
1544
+	 * When "no_console_suspend" is enabled, keep the pinctrl default state
1545
+	 * and rely on bootloader stage to restore this state upon resume.
1546
+	 * Otherwise, apply the idle or sleep states depending on wakeup
1547
+	 * capabilities.
1548
+	 */
1549
+	if (console_suspend_enabled || !uart_console(port)) {
1550
+		if (device_may_wakeup(dev))
1551
+			pinctrl_pm_select_idle_state(dev);
1552
+		else
1553
+			pinctrl_pm_select_sleep_state(dev);
1554
+	}
12921555 
12931556 	return 0;
12941557 }
12951558 
1296
-static int stm32_serial_resume(struct device *dev)
1559
+static int __maybe_unused stm32_usart_serial_resume(struct device *dev)
12971560 {
12981561 	struct uart_port *port = dev_get_drvdata(dev);
12991562 
1563
+	pinctrl_pm_select_default_state(dev);
1564
+
13001565 	if (device_may_wakeup(dev))
1301
-		stm32_serial_enable_wakeup(port, false);
1566
+		stm32_usart_serial_en_wakeup(port, false);
13021567 
13031568 	return uart_resume_port(&stm32_usart_driver, port);
13041569 }
1305
-#endif /* CONFIG_PM_SLEEP */
1570
+
1571
+static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev)
1572
+{
1573
+	struct uart_port *port = dev_get_drvdata(dev);
1574
+	struct stm32_port *stm32port = container_of(port,
1575
+			struct stm32_port, port);
1576
+
1577
+	clk_disable_unprepare(stm32port->clk);
1578
+
1579
+	return 0;
1580
+}
1581
+
1582
+static int __maybe_unused stm32_usart_runtime_resume(struct device *dev)
1583
+{
1584
+	struct uart_port *port = dev_get_drvdata(dev);
1585
+	struct stm32_port *stm32port = container_of(port,
1586
+			struct stm32_port, port);
1587
+
1588
+	return clk_prepare_enable(stm32port->clk);
1589
+}
13061590 
13071591 static const struct dev_pm_ops stm32_serial_pm_ops = {
1308
-	SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1592
+	SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend,
1593
+			   stm32_usart_runtime_resume, NULL)
1594
+	SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend,
1595
+				stm32_usart_serial_resume)
13091596 };
13101597 
13111598 static struct platform_driver stm32_serial_driver = {
1312
-	.probe		= stm32_serial_probe,
1313
-	.remove		= stm32_serial_remove,
1599
+	.probe		= stm32_usart_serial_probe,
1600
+	.remove		= stm32_usart_serial_remove,
13141601 	.driver	= {
13151602 		.name	= DRIVER_NAME,
13161603 		.pm	= &stm32_serial_pm_ops,
....@@ -1318,7 +1605,7 @@
13181605 	},
13191606 };
13201607 
1321
-static int __init usart_init(void)
1608
+static int __init stm32_usart_init(void)
13221609 {
13231610 	static char banner[] __initdata = "STM32 USART driver initialized";
13241611 	int ret;
....@@ -1336,14 +1623,14 @@
13361623 	return ret;
13371624 }
13381625 
1339
-static void __exit usart_exit(void)
1626
+static void __exit stm32_usart_exit(void)
13401627 {
13411628 	platform_driver_unregister(&stm32_serial_driver);
13421629 	uart_unregister_driver(&stm32_usart_driver);
13431630 }
13441631 
1345
-module_init(usart_init);
1346
-module_exit(usart_exit);
1632
+module_init(stm32_usart_init);
1633
+module_exit(stm32_usart_exit);
13471634 
13481635 MODULE_ALIAS("platform:" DRIVER_NAME);
13491636 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");