forked from ~ljy/RK356X_SDK_RELEASE
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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/drivers/tty/serial/imx.c
....@@ -8,10 +8,6 @@
88  * Copyright (C) 2004 Pengutronix
99  */
1010 
11
-#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12
-#define SUPPORT_SYSRQ
13
-#endif
14
-
1511 #include <linux/module.h>
1612 #include <linux/ioport.h>
1713 #include <linux/init.h>
....@@ -24,6 +20,8 @@
2420 #include <linux/serial.h>
2521 #include <linux/clk.h>
2622 #include <linux/delay.h>
23
+#include <linux/ktime.h>
24
+#include <linux/pinctrl/consumer.h>
2725 #include <linux/rational.h>
2826 #include <linux/slab.h>
2927 #include <linux/of.h>
....@@ -191,6 +189,13 @@
191189 	enum imx_uart_type devtype;
192190 };
193191 
192
+enum imx_tx_state {
193
+	OFF,
194
+	WAIT_AFTER_RTS,
195
+	SEND,
196
+	WAIT_AFTER_SEND,
197
+};
198
+
194199 struct imx_port {
195200 	struct uart_port	port;
196201 	struct timer_list	timer;
....@@ -198,6 +203,8 @@
198203 	unsigned int		have_rtscts:1;
199204 	unsigned int		have_rtsgpio:1;
200205 	unsigned int		dte_mode:1;
206
+	unsigned int		inverted_tx:1;
207
+	unsigned int		inverted_rx:1;
201208 	struct clk		*clk_ipg;
202209 	struct clk		*clk_per;
203210 	const struct imx_uart_data *devdata;
....@@ -225,6 +232,10 @@
225232 	unsigned int		dma_tx_nents;
226233 	unsigned int            saved_reg[10];
227234 	bool			context_saved;
235
+
236
+	enum imx_tx_state	tx_state;
237
+	struct hrtimer		trigger_start_tx;
238
+	struct hrtimer		trigger_stop_tx;
228239 };
229240 
230241 struct imx_port_ucrs {
....@@ -362,7 +373,7 @@
362373 /*
363374  * Save and restore functions for UCR1, UCR2 and UCR3 registers
364375  */
365
-#if defined(CONFIG_SERIAL_IMX_CONSOLE)
376
+#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
366377 static void imx_uart_ucrs_save(struct imx_port *sport,
367378 			       struct imx_port_ucrs *ucr)
368379 {
....@@ -387,8 +398,7 @@
387398 {
388399 	*ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
389400 
390
-	sport->port.mctrl |= TIOCM_RTS;
391
-	mctrl_gpio_set(sport->gpios, sport->port.mctrl);
401
+	mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
392402 }
393403 
394404 /* called with port.lock taken and irqs caller dependent */
....@@ -397,14 +407,16 @@
397407 	*ucr2 &= ~UCR2_CTSC;
398408 	*ucr2 |= UCR2_CTS;
399409 
400
-	sport->port.mctrl &= ~TIOCM_RTS;
401
-	mctrl_gpio_set(sport->gpios, sport->port.mctrl);
410
+	mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
402411 }
403412 
404
-/* called with port.lock taken and irqs caller dependent */
405
-static void imx_uart_rts_auto(struct imx_port *sport, u32 *ucr2)
413
+static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
406414 {
407
-	*ucr2 |= UCR2_CTSC;
415
+       long sec = msec / MSEC_PER_SEC;
416
+       long nsec = (msec % MSEC_PER_SEC) * 1000000;
417
+       ktime_t t = ktime_set(sec, nsec);
418
+
419
+       hrtimer_start(hrt, t, HRTIMER_MODE_REL);
408420 }
409421 
410422 /* called with port.lock taken and irqs off */
....@@ -434,7 +446,10 @@
434446 static void imx_uart_stop_tx(struct uart_port *port)
435447 {
436448 	struct imx_port *sport = (struct imx_port *)port;
437
-	u32 ucr1;
449
+	u32 ucr1, ucr4, usr2;
450
+
451
+	if (sport->tx_state == OFF)
452
+		return;
438453 
439454 	/*
440455 	 * We are maybe in the SMP context, so if the DMA TX thread is running
....@@ -444,23 +459,46 @@
444459 		return;
445460 
446461 	ucr1 = imx_uart_readl(sport, UCR1);
447
-	imx_uart_writel(sport, ucr1 & ~UCR1_TXMPTYEN, UCR1);
462
+	imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
448463 
449
-	/* in rs485 mode disable transmitter if shifter is empty */
450
-	if (port->rs485.flags & SER_RS485_ENABLED &&
451
-	    imx_uart_readl(sport, USR2) & USR2_TXDC) {
452
-		u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4;
453
-		if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
454
-			imx_uart_rts_active(sport, &ucr2);
455
-		else
456
-			imx_uart_rts_inactive(sport, &ucr2);
457
-		imx_uart_writel(sport, ucr2, UCR2);
464
+	usr2 = imx_uart_readl(sport, USR2);
465
+	if (!(usr2 & USR2_TXDC)) {
466
+		/* The shifter is still busy, so retry once TC triggers */
467
+		return;
468
+	}
458469 
459
-		imx_uart_start_rx(port);
470
+	ucr4 = imx_uart_readl(sport, UCR4);
471
+	ucr4 &= ~UCR4_TCEN;
472
+	imx_uart_writel(sport, ucr4, UCR4);
460473 
461
-		ucr4 = imx_uart_readl(sport, UCR4);
462
-		ucr4 &= ~UCR4_TCEN;
463
-		imx_uart_writel(sport, ucr4, UCR4);
474
+	/* in rs485 mode disable transmitter */
475
+	if (port->rs485.flags & SER_RS485_ENABLED) {
476
+		if (sport->tx_state == SEND) {
477
+			sport->tx_state = WAIT_AFTER_SEND;
478
+			start_hrtimer_ms(&sport->trigger_stop_tx,
479
+					 port->rs485.delay_rts_after_send);
480
+			return;
481
+		}
482
+
483
+		if (sport->tx_state == WAIT_AFTER_RTS ||
484
+		    sport->tx_state == WAIT_AFTER_SEND) {
485
+			u32 ucr2;
486
+
487
+			hrtimer_try_to_cancel(&sport->trigger_start_tx);
488
+
489
+			ucr2 = imx_uart_readl(sport, UCR2);
490
+			if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
491
+				imx_uart_rts_active(sport, &ucr2);
492
+			else
493
+				imx_uart_rts_inactive(sport, &ucr2);
494
+			imx_uart_writel(sport, ucr2, UCR2);
495
+
496
+			imx_uart_start_rx(port);
497
+
498
+			sport->tx_state = OFF;
499
+		}
500
+	} else {
501
+		sport->tx_state = OFF;
464502 	}
465503 }
466504 
....@@ -468,18 +506,21 @@
468506 static void imx_uart_stop_rx(struct uart_port *port)
469507 {
470508 	struct imx_port *sport = (struct imx_port *)port;
471
-	u32 ucr1, ucr2;
509
+	u32 ucr1, ucr2, ucr4;
472510 
473511 	ucr1 = imx_uart_readl(sport, UCR1);
474512 	ucr2 = imx_uart_readl(sport, UCR2);
513
+	ucr4 = imx_uart_readl(sport, UCR4);
475514 
476515 	if (sport->dma_is_enabled) {
477516 		ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
478517 	} else {
479518 		ucr1 &= ~UCR1_RRDYEN;
480519 		ucr2 &= ~UCR2_ATEN;
520
+		ucr4 &= ~UCR4_OREN;
481521 	}
482522 	imx_uart_writel(sport, ucr1, UCR1);
523
+	imx_uart_writel(sport, ucr4, UCR4);
483524 
484525 	ucr2 &= ~UCR2_RXEN;
485526 	imx_uart_writel(sport, ucr2, UCR2);
....@@ -522,7 +563,7 @@
522563 		 * and the TX IRQ is disabled.
523564 		 **/
524565 		ucr1 = imx_uart_readl(sport, UCR1);
525
-		ucr1 &= ~UCR1_TXMPTYEN;
566
+		ucr1 &= ~UCR1_TRDYEN;
526567 		if (sport->dma_is_txing) {
527568 			ucr1 |= UCR1_TXDMAEN;
528569 			imx_uart_writel(sport, ucr1, UCR1);
....@@ -658,33 +699,55 @@
658699 	if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
659700 		return;
660701 
702
+	/*
703
+	 * We cannot simply do nothing here if sport->tx_state == SEND already
704
+	 * because UCR1_TXMPTYEN might already have been cleared in
705
+	 * imx_uart_stop_tx(), but tx_state is still SEND.
706
+	 */
707
+
661708 	if (port->rs485.flags & SER_RS485_ENABLED) {
662
-		u32 ucr2;
709
+		if (sport->tx_state == OFF) {
710
+			u32 ucr2 = imx_uart_readl(sport, UCR2);
711
+			if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
712
+				imx_uart_rts_active(sport, &ucr2);
713
+			else
714
+				imx_uart_rts_inactive(sport, &ucr2);
715
+			imx_uart_writel(sport, ucr2, UCR2);
663716 
664
-		ucr2 = imx_uart_readl(sport, UCR2);
665
-		if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
666
-			imx_uart_rts_active(sport, &ucr2);
667
-		else
668
-			imx_uart_rts_inactive(sport, &ucr2);
669
-		imx_uart_writel(sport, ucr2, UCR2);
717
+			if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
718
+				imx_uart_stop_rx(port);
670719 
671
-		if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
672
-			imx_uart_stop_rx(port);
673
-
674
-		/*
675
-		 * Enable transmitter and shifter empty irq only if DMA is off.
676
-		 * In the DMA case this is done in the tx-callback.
677
-		 */
678
-		if (!sport->dma_is_enabled) {
679
-			u32 ucr4 = imx_uart_readl(sport, UCR4);
680
-			ucr4 |= UCR4_TCEN;
681
-			imx_uart_writel(sport, ucr4, UCR4);
720
+			sport->tx_state = WAIT_AFTER_RTS;
721
+			start_hrtimer_ms(&sport->trigger_start_tx,
722
+					 port->rs485.delay_rts_before_send);
723
+			return;
682724 		}
725
+
726
+		if (sport->tx_state == WAIT_AFTER_SEND
727
+		    || sport->tx_state == WAIT_AFTER_RTS) {
728
+
729
+			hrtimer_try_to_cancel(&sport->trigger_stop_tx);
730
+
731
+			/*
732
+			 * Enable transmitter and shifter empty irq only if DMA
733
+			 * is off.  In the DMA case this is done in the
734
+			 * tx-callback.
735
+			 */
736
+			if (!sport->dma_is_enabled) {
737
+				u32 ucr4 = imx_uart_readl(sport, UCR4);
738
+				ucr4 |= UCR4_TCEN;
739
+				imx_uart_writel(sport, ucr4, UCR4);
740
+			}
741
+
742
+			sport->tx_state = SEND;
743
+		}
744
+	} else {
745
+		sport->tx_state = SEND;
683746 	}
684747 
685748 	if (!sport->dma_is_enabled) {
686749 		ucr1 = imx_uart_readl(sport, UCR1);
687
-		imx_uart_writel(sport, ucr1 | UCR1_TXMPTYEN, UCR1);
750
+		imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
688751 	}
689752 
690753 	if (sport->dma_is_enabled) {
....@@ -693,7 +756,7 @@
693756 			 * disable TX DMA to let TX interrupt to send X-char */
694757 			ucr1 = imx_uart_readl(sport, UCR1);
695758 			ucr1 &= ~UCR1_TXDMAEN;
696
-			ucr1 |= UCR1_TXMPTYEN;
759
+			ucr1 |= UCR1_TRDYEN;
697760 			imx_uart_writel(sport, ucr1, UCR1);
698761 			return;
699762 		}
....@@ -705,42 +768,48 @@
705768 	}
706769 }
707770 
708
-static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
771
+static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
709772 {
710773 	struct imx_port *sport = dev_id;
711774 	u32 usr1;
712
-	unsigned long flags;
713
-
714
-	spin_lock_irqsave(&sport->port.lock, flags);
715775 
716776 	imx_uart_writel(sport, USR1_RTSD, USR1);
717777 	usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
718778 	uart_handle_cts_change(&sport->port, !!usr1);
719779 	wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
720780 
721
-	spin_unlock_irqrestore(&sport->port.lock, flags);
722781 	return IRQ_HANDLED;
782
+}
783
+
784
+static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
785
+{
786
+	struct imx_port *sport = dev_id;
787
+	irqreturn_t ret;
788
+
789
+	spin_lock(&sport->port.lock);
790
+
791
+	ret = __imx_uart_rtsint(irq, dev_id);
792
+
793
+	spin_unlock(&sport->port.lock);
794
+
795
+	return ret;
723796 }
724797 
725798 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
726799 {
727800 	struct imx_port *sport = dev_id;
728
-	unsigned long flags;
729801 
730
-	spin_lock_irqsave(&sport->port.lock, flags);
802
+	spin_lock(&sport->port.lock);
731803 	imx_uart_transmit_buffer(sport);
732
-	spin_unlock_irqrestore(&sport->port.lock, flags);
804
+	spin_unlock(&sport->port.lock);
733805 	return IRQ_HANDLED;
734806 }
735807 
736
-static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
808
+static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
737809 {
738810 	struct imx_port *sport = dev_id;
739811 	unsigned int rx, flg, ignored = 0;
740812 	struct tty_port *port = &sport->port.state->port;
741
-	unsigned long flags;
742
-
743
-	spin_lock_irqsave(&sport->port.lock, flags);
744813 
745814 	while (imx_uart_readl(sport, USR2) & USR2_RDR) {
746815 		u32 usr2;
....@@ -787,9 +856,7 @@
787856 			if (rx & URXD_OVRRUN)
788857 				flg = TTY_OVERRUN;
789858 
790
-#ifdef SUPPORT_SYSRQ
791859 			sport->port.sysrq = 0;
792
-#endif
793860 		}
794861 
795862 		if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
....@@ -800,9 +867,23 @@
800867 	}
801868 
802869 out:
803
-	spin_unlock_irqrestore(&sport->port.lock, flags);
804870 	tty_flip_buffer_push(port);
871
+
805872 	return IRQ_HANDLED;
873
+}
874
+
875
+static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
876
+{
877
+	struct imx_port *sport = dev_id;
878
+	irqreturn_t ret;
879
+
880
+	spin_lock(&sport->port.lock);
881
+
882
+	ret = __imx_uart_rxint(irq, dev_id);
883
+
884
+	spin_unlock(&sport->port.lock);
885
+
886
+	return ret;
806887 }
807888 
808889 static void imx_uart_clear_rx_errors(struct imx_port *sport);
....@@ -862,6 +943,14 @@
862943 	struct imx_port *sport = dev_id;
863944 	unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
864945 	irqreturn_t ret = IRQ_NONE;
946
+	unsigned long flags = 0;
947
+
948
+	/*
949
+	 * IRQs might not be disabled upon entering this interrupt handler,
950
+	 * e.g. when interrupt handlers are forced to be threaded. To support
951
+	 * this scenario as well, disable IRQs when acquiring the spinlock.
952
+	 */
953
+	spin_lock_irqsave(&sport->port.lock, flags);
865954 
866955 	usr1 = imx_uart_readl(sport, USR1);
867956 	usr2 = imx_uart_readl(sport, USR2);
....@@ -882,7 +971,7 @@
882971 		usr1 &= ~USR1_RRDY;
883972 	if ((ucr2 & UCR2_ATEN) == 0)
884973 		usr1 &= ~USR1_AGTIM;
885
-	if ((ucr1 & UCR1_TXMPTYEN) == 0)
974
+	if ((ucr1 & UCR1_TRDYEN) == 0)
886975 		usr1 &= ~USR1_TRDY;
887976 	if ((ucr4 & UCR4_TCEN) == 0)
888977 		usr2 &= ~USR2_TXDC;
....@@ -896,29 +985,27 @@
896985 		usr2 &= ~USR2_ORE;
897986 
898987 	if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
899
-		imx_uart_rxint(irq, dev_id);
988
+		imx_uart_writel(sport, USR1_AGTIM, USR1);
989
+
990
+		__imx_uart_rxint(irq, dev_id);
900991 		ret = IRQ_HANDLED;
901992 	}
902993 
903994 	if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
904
-		imx_uart_txint(irq, dev_id);
995
+		imx_uart_transmit_buffer(sport);
905996 		ret = IRQ_HANDLED;
906997 	}
907998 
908999 	if (usr1 & USR1_DTRD) {
909
-		unsigned long flags;
910
-
9111000 		imx_uart_writel(sport, USR1_DTRD, USR1);
9121001 
913
-		spin_lock_irqsave(&sport->port.lock, flags);
9141002 		imx_uart_mctrl_check(sport);
915
-		spin_unlock_irqrestore(&sport->port.lock, flags);
9161003 
9171004 		ret = IRQ_HANDLED;
9181005 	}
9191006 
9201007 	if (usr1 & USR1_RTSD) {
921
-		imx_uart_rtsint(irq, dev_id);
1008
+		__imx_uart_rtsint(irq, dev_id);
9221009 		ret = IRQ_HANDLED;
9231010 	}
9241011 
....@@ -932,6 +1019,8 @@
9321019 		imx_uart_writel(sport, USR2_ORE, USR2);
9331020 		ret = IRQ_HANDLED;
9341021 	}
1022
+
1023
+	spin_unlock_irqrestore(&sport->port.lock, flags);
9351024 
9361025 	return ret;
9371026 }
....@@ -973,10 +1062,22 @@
9731062 	if (!(port->rs485.flags & SER_RS485_ENABLED)) {
9741063 		u32 ucr2;
9751064 
1065
+		/*
1066
+		 * Turn off autoRTS if RTS is lowered and restore autoRTS
1067
+		 * setting if RTS is raised.
1068
+		 */
9761069 		ucr2 = imx_uart_readl(sport, UCR2);
9771070 		ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
978
-		if (mctrl & TIOCM_RTS)
979
-			ucr2 |= UCR2_CTS | UCR2_CTSC;
1071
+		if (mctrl & TIOCM_RTS) {
1072
+			ucr2 |= UCR2_CTS;
1073
+			/*
1074
+			 * UCR2_IRTS is unset if and only if the port is
1075
+			 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1076
+			 * to get the state to restore to.
1077
+			 */
1078
+			if (!(ucr2 & UCR2_IRTS))
1079
+				ucr2 |= UCR2_CTSC;
1080
+		}
9801081 		imx_uart_writel(sport, ucr2, UCR2);
9811082 	}
9821083 
....@@ -1031,8 +1132,6 @@
10311132 		mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
10321133 	}
10331134 }
1034
-
1035
-#define RX_BUF_SIZE	(PAGE_SIZE)
10361135 
10371136 /*
10381137  * There are two kinds of RX DMA interrupts(such as in the MX6Q):
....@@ -1116,7 +1215,8 @@
11161215 }
11171216 
11181217 /* RX DMA buffer periods */
1119
-#define RX_DMA_PERIODS 4
1218
+#define RX_DMA_PERIODS	16
1219
+#define RX_BUF_SIZE	(RX_DMA_PERIODS * PAGE_SIZE / 4)
11201220 
11211221 static int imx_uart_start_rx_dma(struct imx_port *sport)
11221222 {
....@@ -1172,7 +1272,6 @@
11721272 			sport->port.icount.buf_overrun++;
11731273 		tty_flip_buffer_push(port);
11741274 	} else {
1175
-		dev_err(sport->port.dev, "DMA transaction error.\n");
11761275 		if (usr1 & USR1_FRAMERR) {
11771276 			sport->port.icount.frame++;
11781277 			imx_uart_writel(sport, USR1_FRAMERR, USR1);
....@@ -1316,7 +1415,7 @@
13161415 	int retval, i;
13171416 	unsigned long flags;
13181417 	int dma_is_inited = 0;
1319
-	u32 ucr1, ucr2, ucr4;
1418
+	u32 ucr1, ucr2, ucr3, ucr4;
13201419 
13211420 	retval = clk_prepare_enable(sport->clk_per);
13221421 	if (retval)
....@@ -1368,10 +1467,28 @@
13681467 
13691468 	imx_uart_writel(sport, ucr1, UCR1);
13701469 
1371
-	ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN;
1372
-	if (!sport->dma_is_enabled)
1470
+	ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1471
+	if (!dma_is_inited)
13731472 		ucr4 |= UCR4_OREN;
1473
+	if (sport->inverted_rx)
1474
+		ucr4 |= UCR4_INVR;
13741475 	imx_uart_writel(sport, ucr4, UCR4);
1476
+
1477
+	ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1478
+	/*
1479
+	 * configure tx polarity before enabling tx
1480
+	 */
1481
+	if (sport->inverted_tx)
1482
+		ucr3 |= UCR3_INVT;
1483
+
1484
+	if (!imx_uart_is_imx1(sport)) {
1485
+		ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1486
+
1487
+		if (sport->dte_mode)
1488
+			/* disable broken interrupts */
1489
+			ucr3 &= ~(UCR3_RI | UCR3_DCD);
1490
+	}
1491
+	imx_uart_writel(sport, ucr3, UCR3);
13751492 
13761493 	ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
13771494 	ucr2 |= (UCR2_RXEN | UCR2_TXEN);
....@@ -1384,20 +1501,6 @@
13841501 	if (!imx_uart_is_imx1(sport))
13851502 		ucr2 &= ~UCR2_RTSEN;
13861503 	imx_uart_writel(sport, ucr2, UCR2);
1387
-
1388
-	if (!imx_uart_is_imx1(sport)) {
1389
-		u32 ucr3;
1390
-
1391
-		ucr3 = imx_uart_readl(sport, UCR3);
1392
-
1393
-		ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1394
-
1395
-		if (sport->dte_mode)
1396
-			/* disable broken interrupts */
1397
-			ucr3 &= ~(UCR3_RI | UCR3_DCD);
1398
-
1399
-		imx_uart_writel(sport, ucr3, UCR3);
1400
-	}
14011504 
14021505 	/*
14031506 	 * Enable modem status interrupts
....@@ -1456,10 +1559,6 @@
14561559 	ucr2 = imx_uart_readl(sport, UCR2);
14571560 	ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
14581561 	imx_uart_writel(sport, ucr2, UCR2);
1459
-
1460
-	ucr4 = imx_uart_readl(sport, UCR4);
1461
-	ucr4 &= ~UCR4_OREN;
1462
-	imx_uart_writel(sport, ucr4, UCR4);
14631562 	spin_unlock_irqrestore(&sport->port.lock, flags);
14641563 
14651564 	/*
....@@ -1472,10 +1571,15 @@
14721571 	 */
14731572 
14741573 	spin_lock_irqsave(&sport->port.lock, flags);
1475
-	ucr1 = imx_uart_readl(sport, UCR1);
1476
-	ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
14771574 
1575
+	ucr1 = imx_uart_readl(sport, UCR1);
1576
+	ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
14781577 	imx_uart_writel(sport, ucr1, UCR1);
1578
+
1579
+	ucr4 = imx_uart_readl(sport, UCR4);
1580
+	ucr4 &= ~UCR4_TCEN;
1581
+	imx_uart_writel(sport, ucr4, UCR4);
1582
+
14791583 	spin_unlock_irqrestore(&sport->port.lock, flags);
14801584 
14811585 	clk_disable_unprepare(sport->clk_per);
....@@ -1540,11 +1644,11 @@
15401644 {
15411645 	struct imx_port *sport = (struct imx_port *)port;
15421646 	unsigned long flags;
1543
-	u32 ucr2, old_ucr1, old_ucr2, ufcr;
1647
+	u32 ucr2, old_ucr2, ufcr;
15441648 	unsigned int baud, quot;
15451649 	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
15461650 	unsigned long div;
1547
-	unsigned long num, denom;
1651
+	unsigned long num, denom, old_ubir, old_ubmr;
15481652 	uint64_t tdiv64;
15491653 
15501654 	/*
....@@ -1567,41 +1671,42 @@
15671671 
15681672 	spin_lock_irqsave(&sport->port.lock, flags);
15691673 
1674
+	/*
1675
+	 * Read current UCR2 and save it for future use, then clear all the bits
1676
+	 * except those we will or may need to preserve.
1677
+	 */
1678
+	old_ucr2 = imx_uart_readl(sport, UCR2);
1679
+	ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1680
+
1681
+	ucr2 |= UCR2_SRST | UCR2_IRTS;
15701682 	if ((termios->c_cflag & CSIZE) == CS8)
1571
-		ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1572
-	else
1573
-		ucr2 = UCR2_SRST | UCR2_IRTS;
1683
+		ucr2 |= UCR2_WS;
15741684 
1575
-	if (termios->c_cflag & CRTSCTS) {
1576
-		if (sport->have_rtscts) {
1577
-			ucr2 &= ~UCR2_IRTS;
1685
+	if (!sport->have_rtscts)
1686
+		termios->c_cflag &= ~CRTSCTS;
15781687 
1579
-			if (port->rs485.flags & SER_RS485_ENABLED) {
1580
-				/*
1581
-				 * RTS is mandatory for rs485 operation, so keep
1582
-				 * it under manual control and keep transmitter
1583
-				 * disabled.
1584
-				 */
1585
-				if (port->rs485.flags &
1586
-				    SER_RS485_RTS_AFTER_SEND)
1587
-					imx_uart_rts_active(sport, &ucr2);
1588
-				else
1589
-					imx_uart_rts_inactive(sport, &ucr2);
1590
-			} else {
1591
-				imx_uart_rts_auto(sport, &ucr2);
1592
-			}
1593
-		} else {
1594
-			termios->c_cflag &= ~CRTSCTS;
1595
-		}
1596
-	} else if (port->rs485.flags & SER_RS485_ENABLED) {
1597
-		/* disable transmitter */
1688
+	if (port->rs485.flags & SER_RS485_ENABLED) {
1689
+		/*
1690
+		 * RTS is mandatory for rs485 operation, so keep
1691
+		 * it under manual control and keep transmitter
1692
+		 * disabled.
1693
+		 */
15981694 		if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
15991695 			imx_uart_rts_active(sport, &ucr2);
16001696 		else
16011697 			imx_uart_rts_inactive(sport, &ucr2);
1698
+
1699
+	} else if (termios->c_cflag & CRTSCTS) {
1700
+		/*
1701
+		 * Only let receiver control RTS output if we were not requested
1702
+		 * to have RTS inactive (which then should take precedence).
1703
+		 */
1704
+		if (ucr2 & UCR2_CTS)
1705
+			ucr2 |= UCR2_CTSC;
16021706 	}
16031707 
1604
-
1708
+	if (termios->c_cflag & CRTSCTS)
1709
+		ucr2 &= ~UCR2_IRTS;
16051710 	if (termios->c_cflag & CSTOPB)
16061711 		ucr2 |= UCR2_STPB;
16071712 	if (termios->c_cflag & PARENB) {
....@@ -1640,23 +1745,6 @@
16401745 	 */
16411746 	uart_update_timeout(port, termios->c_cflag, baud);
16421747 
1643
-	/*
1644
-	 * disable interrupts and drain transmitter
1645
-	 */
1646
-	old_ucr1 = imx_uart_readl(sport, UCR1);
1647
-	imx_uart_writel(sport,
1648
-			old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1649
-			UCR1);
1650
-	old_ucr2 = imx_uart_readl(sport, UCR2);
1651
-	imx_uart_writel(sport, old_ucr2 & ~UCR2_ATEN, UCR2);
1652
-
1653
-	while (!(imx_uart_readl(sport, USR2) & USR2_TXDC))
1654
-		barrier();
1655
-
1656
-	/* then, disable everything */
1657
-	imx_uart_writel(sport, old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN | UCR2_ATEN), UCR2);
1658
-	old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1659
-
16601748 	/* custom-baudrate handling */
16611749 	div = sport->port.uartclk / (baud * 16);
16621750 	if (baud == 38400 && quot != div)
....@@ -1684,17 +1772,27 @@
16841772 	ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
16851773 	imx_uart_writel(sport, ufcr, UFCR);
16861774 
1687
-	imx_uart_writel(sport, num, UBIR);
1688
-	imx_uart_writel(sport, denom, UBMR);
1775
+	/*
1776
+	 *  Two registers below should always be written both and in this
1777
+	 *  particular order. One consequence is that we need to check if any of
1778
+	 *  them changes and then update both. We do need the check for change
1779
+	 *  as even writing the same values seem to "restart"
1780
+	 *  transmission/receiving logic in the hardware, that leads to data
1781
+	 *  breakage even when rate doesn't in fact change. E.g., user switches
1782
+	 *  RTS/CTS handshake and suddenly gets broken bytes.
1783
+	 */
1784
+	old_ubir = imx_uart_readl(sport, UBIR);
1785
+	old_ubmr = imx_uart_readl(sport, UBMR);
1786
+	if (old_ubir != num || old_ubmr != denom) {
1787
+		imx_uart_writel(sport, num, UBIR);
1788
+		imx_uart_writel(sport, denom, UBMR);
1789
+	}
16891790 
16901791 	if (!imx_uart_is_imx1(sport))
16911792 		imx_uart_writel(sport, sport->port.uartclk / div / 1000,
16921793 				IMX21_ONEMS);
16931794 
1694
-	imx_uart_writel(sport, old_ucr1, UCR1);
1695
-
1696
-	/* set the parity, stop bits and data size */
1697
-	imx_uart_writel(sport, ucr2 | old_ucr2, UCR2);
1795
+	imx_uart_writel(sport, ucr2, UCR2);
16981796 
16991797 	if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
17001798 		imx_uart_enable_ms(&sport->port);
....@@ -1782,7 +1880,7 @@
17821880 		ucr1 |= IMX1_UCR1_UARTCLKEN;
17831881 
17841882 	ucr1 |= UCR1_UARTEN;
1785
-	ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1883
+	ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
17861884 
17871885 	ucr2 |= UCR2_RXEN;
17881886 	ucr2 &= ~UCR2_ATEN;
....@@ -1834,10 +1932,6 @@
18341932 {
18351933 	struct imx_port *sport = (struct imx_port *)port;
18361934 	u32 ucr2;
1837
-
1838
-	/* unimplemented */
1839
-	rs485conf->delay_rts_before_send = 0;
1840
-	rs485conf->delay_rts_after_send = 0;
18411935 
18421936 	/* RTS is required to control the transmitter */
18431937 	if (!sport->have_rtscts && !sport->have_rtsgpio)
....@@ -1893,7 +1987,7 @@
18931987 
18941988 static struct imx_port *imx_uart_ports[UART_NR];
18951989 
1896
-#ifdef CONFIG_SERIAL_IMX_CONSOLE
1990
+#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
18971991 static void imx_uart_console_putchar(struct uart_port *port, int ch)
18981992 {
18991993 	struct imx_port *sport = (struct imx_port *)port;
....@@ -1932,7 +2026,7 @@
19322026 	if (imx_uart_is_imx1(sport))
19332027 		ucr1 |= IMX1_UCR1_UARTCLKEN;
19342028 	ucr1 |= UCR1_UARTEN;
1935
-	ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2029
+	ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
19362030 
19372031 	imx_uart_writel(sport, ucr1, UCR1);
19382032 
....@@ -1956,7 +2050,7 @@
19562050  * If the port was already initialised (eg, by a boot loader),
19572051  * try to determine the current setup.
19582052  */
1959
-static void __init
2053
+static void
19602054 imx_uart_console_get_options(struct imx_port *sport, int *baud,
19612055 			     int *parity, int *bits)
19622056 {
....@@ -2010,12 +2104,12 @@
20102104 		}
20112105 
20122106 		if (*baud != baud_raw)
2013
-			pr_info("Console IMX rounded baud rate from %d to %d\n",
2107
+			dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
20142108 				baud_raw, *baud);
20152109 	}
20162110 }
20172111 
2018
-static int __init
2112
+static int
20192113 imx_uart_console_setup(struct console *co, char *options)
20202114 {
20212115 	struct imx_port *sport;
....@@ -2076,39 +2170,6 @@
20762170 
20772171 #define IMX_CONSOLE	&imx_uart_console
20782172 
2079
-#ifdef CONFIG_OF
2080
-static void imx_uart_console_early_putchar(struct uart_port *port, int ch)
2081
-{
2082
-	struct imx_port *sport = (struct imx_port *)port;
2083
-
2084
-	while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL)
2085
-		cpu_relax();
2086
-
2087
-	imx_uart_writel(sport, ch, URTX0);
2088
-}
2089
-
2090
-static void imx_uart_console_early_write(struct console *con, const char *s,
2091
-					 unsigned count)
2092
-{
2093
-	struct earlycon_device *dev = con->data;
2094
-
2095
-	uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar);
2096
-}
2097
-
2098
-static int __init
2099
-imx_console_early_setup(struct earlycon_device *dev, const char *opt)
2100
-{
2101
-	if (!dev->port.membase)
2102
-		return -ENODEV;
2103
-
2104
-	dev->con->write = imx_uart_console_early_write;
2105
-
2106
-	return 0;
2107
-}
2108
-OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
2109
-OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
2110
-#endif
2111
-
21122173 #else
21132174 #define IMX_CONSOLE	NULL
21142175 #endif
....@@ -2156,6 +2217,12 @@
21562217 	if (of_get_property(np, "rts-gpios", NULL))
21572218 		sport->have_rtsgpio = 1;
21582219 
2220
+	if (of_get_property(np, "fsl,inverted-tx", NULL))
2221
+		sport->inverted_tx = 1;
2222
+
2223
+	if (of_get_property(np, "fsl,inverted-rx", NULL))
2224
+		sport->inverted_rx = 1;
2225
+
21592226 	return 0;
21602227 }
21612228 #else
....@@ -2179,6 +2246,32 @@
21792246 
21802247 	if (pdata->flags & IMXUART_HAVE_RTSCTS)
21812248 		sport->have_rtscts = 1;
2249
+}
2250
+
2251
+static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2252
+{
2253
+	struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2254
+	unsigned long flags;
2255
+
2256
+	spin_lock_irqsave(&sport->port.lock, flags);
2257
+	if (sport->tx_state == WAIT_AFTER_RTS)
2258
+		imx_uart_start_tx(&sport->port);
2259
+	spin_unlock_irqrestore(&sport->port.lock, flags);
2260
+
2261
+	return HRTIMER_NORESTART;
2262
+}
2263
+
2264
+static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2265
+{
2266
+	struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2267
+	unsigned long flags;
2268
+
2269
+	spin_lock_irqsave(&sport->port.lock, flags);
2270
+	if (sport->tx_state == WAIT_AFTER_SEND)
2271
+		imx_uart_stop_tx(&sport->port);
2272
+	spin_unlock_irqrestore(&sport->port.lock, flags);
2273
+
2274
+	return HRTIMER_NORESTART;
21822275 }
21832276 
21842277 static int imx_uart_probe(struct platform_device *pdev)
....@@ -2212,8 +2305,10 @@
22122305 		return PTR_ERR(base);
22132306 
22142307 	rxirq = platform_get_irq(pdev, 0);
2215
-	txirq = platform_get_irq(pdev, 1);
2216
-	rtsirq = platform_get_irq(pdev, 2);
2308
+	if (rxirq < 0)
2309
+		return rxirq;
2310
+	txirq = platform_get_irq_optional(pdev, 1);
2311
+	rtsirq = platform_get_irq_optional(pdev, 2);
22172312 
22182313 	sport->port.dev = &pdev->dev;
22192314 	sport->port.mapbase = res->start;
....@@ -2222,6 +2317,7 @@
22222317 	sport->port.iotype = UPIO_MEM;
22232318 	sport->port.irq = rxirq;
22242319 	sport->port.fifosize = 32;
2320
+	sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
22252321 	sport->port.ops = &imx_uart_pops;
22262322 	sport->port.rs485_config = imx_uart_rs485_config;
22272323 	sport->port.flags = UPF_BOOT_AUTOCONF;
....@@ -2261,7 +2357,11 @@
22612357 	sport->ucr4 = readl(sport->port.membase + UCR4);
22622358 	sport->ufcr = readl(sport->port.membase + UFCR);
22632359 
2264
-	uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
2360
+	ret = uart_get_rs485_mode(&sport->port);
2361
+	if (ret) {
2362
+		clk_disable_unprepare(sport->clk_ipg);
2363
+		return ret;
2364
+	}
22652365 
22662366 	if (sport->port.rs485.flags & SER_RS485_ENABLED &&
22672367 	    (!sport->have_rtscts && !sport->have_rtsgpio))
....@@ -2279,12 +2379,9 @@
22792379 		dev_err(&pdev->dev,
22802380 			"low-active RTS not possible when receiver is off, enabling receiver\n");
22812381 
2282
-	imx_uart_rs485_config(&sport->port, &sport->port.rs485);
2283
-
22842382 	/* Disable interrupts before requesting them */
22852383 	ucr1 = imx_uart_readl(sport, UCR1);
2286
-	ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2287
-		 UCR1_TXMPTYEN | UCR1_RTSDEN);
2384
+	ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
22882385 	imx_uart_writel(sport, ucr1, UCR1);
22892386 
22902387 	if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
....@@ -2319,6 +2416,11 @@
23192416 	}
23202417 
23212418 	clk_disable_unprepare(sport->clk_ipg);
2419
+
2420
+	hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2421
+	hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2422
+	sport->trigger_start_tx.function = imx_trigger_start_tx;
2423
+	sport->trigger_stop_tx.function = imx_trigger_stop_tx;
23222424 
23232425 	/*
23242426 	 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
....@@ -2373,8 +2475,13 @@
23732475 
23742476 static void imx_uart_restore_context(struct imx_port *sport)
23752477 {
2376
-	if (!sport->context_saved)
2478
+	unsigned long flags;
2479
+
2480
+	spin_lock_irqsave(&sport->port.lock, flags);
2481
+	if (!sport->context_saved) {
2482
+		spin_unlock_irqrestore(&sport->port.lock, flags);
23772483 		return;
2484
+	}
23782485 
23792486 	imx_uart_writel(sport, sport->saved_reg[4], UFCR);
23802487 	imx_uart_writel(sport, sport->saved_reg[5], UESC);
....@@ -2387,11 +2494,15 @@
23872494 	imx_uart_writel(sport, sport->saved_reg[2], UCR3);
23882495 	imx_uart_writel(sport, sport->saved_reg[3], UCR4);
23892496 	sport->context_saved = false;
2497
+	spin_unlock_irqrestore(&sport->port.lock, flags);
23902498 }
23912499 
23922500 static void imx_uart_save_context(struct imx_port *sport)
23932501 {
2502
+	unsigned long flags;
2503
+
23942504 	/* Save necessary regs */
2505
+	spin_lock_irqsave(&sport->port.lock, flags);
23952506 	sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
23962507 	sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
23972508 	sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
....@@ -2403,6 +2514,7 @@
24032514 	sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
24042515 	sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
24052516 	sport->context_saved = true;
2517
+	spin_unlock_irqrestore(&sport->port.lock, flags);
24062518 }
24072519 
24082520 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
....@@ -2436,6 +2548,8 @@
24362548 
24372549 	clk_disable(sport->clk_ipg);
24382550 
2551
+	pinctrl_pm_select_sleep_state(dev);
2552
+
24392553 	return 0;
24402554 }
24412555 
....@@ -2443,6 +2557,8 @@
24432557 {
24442558 	struct imx_port *sport = dev_get_drvdata(dev);
24452559 	int ret;
2560
+
2561
+	pinctrl_pm_select_default_state(dev);
24462562 
24472563 	ret = clk_enable(sport->clk_ipg);
24482564 	if (ret)
....@@ -2510,6 +2626,7 @@
25102626 	.suspend_noirq = imx_uart_suspend_noirq,
25112627 	.resume_noirq = imx_uart_resume_noirq,
25122628 	.freeze_noirq = imx_uart_suspend_noirq,
2629
+	.thaw_noirq = imx_uart_resume_noirq,
25132630 	.restore_noirq = imx_uart_resume_noirq,
25142631 	.suspend = imx_uart_suspend,
25152632 	.resume = imx_uart_resume,