~hc/RK356X_SDK_RELEASE.git

..	..	@@ -5,10 +5,6 @@
5	5	* Copyright 2012-2014 Freescale Semiconductor, Inc.
6	6	*/
7	7
8		-#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
9		-#define SUPPORT_SYSRQ
10		-#endif
11		-
12	8	#include <linux/clk.h>
13	9	#include <linux/console.h>
14	10	#include <linux/dma-mapping.h>
..	..	@@ -214,6 +210,7 @@
214	210	#define UARTFIFO_TXSIZE_OFF 4
215	211	#define UARTFIFO_RXFE 0x00000008
216	212	#define UARTFIFO_RXSIZE_OFF 0
	213	+#define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0))
217	214
218	215	#define UARTWATER_COUNT_MASK 0xff
219	216	#define UARTWATER_TXCNT_OFF 8
..	..	@@ -232,9 +229,19 @@
232	229	/* IMX lpuart has four extra unused regs located at the beginning */
233	230	#define IMX_REG_OFF 0x10
234	231
	232	+enum lpuart_type {
	233	+ VF610_LPUART,
	234	+ LS1021A_LPUART,
	235	+ LS1028A_LPUART,
	236	+ IMX7ULP_LPUART,
	237	+ IMX8QXP_LPUART,
	238	+};
	239	+
235	240	struct lpuart_port {
236	241	struct uart_port port;
237		- struct clk *clk;
	242	+ enum lpuart_type devtype;
	243	+ struct clk *ipg_clk;
	244	+ struct clk *baud_clk;
238	245	unsigned int txfifo_size;
239	246	unsigned int rxfifo_size;
240	247
..	..	@@ -259,33 +266,61 @@
259	266	};
260	267
261	268	struct lpuart_soc_data {
262		- char iotype;
263		- u8 reg_off;
	269	+ enum lpuart_type devtype;
	270	+ char iotype;
	271	+ u8 reg_off;
264	272	};
265	273
266	274	static const struct lpuart_soc_data vf_data = {
	275	+ .devtype = VF610_LPUART,
267	276	.iotype = UPIO_MEM,
268	277	};
269	278
270		-static const struct lpuart_soc_data ls_data = {
	279	+static const struct lpuart_soc_data ls1021a_data = {
	280	+ .devtype = LS1021A_LPUART,
271	281	.iotype = UPIO_MEM32BE,
272	282	};
273	283
274		-static struct lpuart_soc_data imx_data = {
	284	+static const struct lpuart_soc_data ls1028a_data = {
	285	+ .devtype = LS1028A_LPUART,
	286	+ .iotype = UPIO_MEM32,
	287	+};
	288	+
	289	+static struct lpuart_soc_data imx7ulp_data = {
	290	+ .devtype = IMX7ULP_LPUART,
	291	+ .iotype = UPIO_MEM32,
	292	+ .reg_off = IMX_REG_OFF,
	293	+};
	294	+
	295	+static struct lpuart_soc_data imx8qxp_data = {
	296	+ .devtype = IMX8QXP_LPUART,
275	297	.iotype = UPIO_MEM32,
276	298	.reg_off = IMX_REG_OFF,
277	299	};
278	300
279	301	static const struct of_device_id lpuart_dt_ids[] = {
280	302	{ .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
281		- { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, },
282		- { .compatible = "fsl,imx7ulp-lpuart", .data = &imx_data, },
	303	+ { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
	304	+ { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
	305	+ { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
	306	+ { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
283	307	{ /* sentinel */ }
284	308	};
285	309	MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
286	310
287	311	/* Forward declare this for the dma callbacks*/
288	312	static void lpuart_dma_tx_complete(void *arg);
	313	+
	314	+static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
	315	+{
	316	+ return (sport->devtype == LS1021A_LPUART \|\|
	317	+ sport->devtype == LS1028A_LPUART);
	318	+}
	319	+
	320	+static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
	321	+{
	322	+ return sport->devtype == IMX8QXP_LPUART;
	323	+}
289	324
290	325	static inline u32 lpuart32_read(struct uart_port *port, u32 off)
291	326	{
..	..	@@ -311,6 +346,39 @@
311	346	break;
312	347	}
313	348	}
	349	+
	350	+static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
	351	+{
	352	+ int ret = 0;
	353	+
	354	+ if (is_en) {
	355	+ ret = clk_prepare_enable(sport->ipg_clk);
	356	+ if (ret)
	357	+ return ret;
	358	+
	359	+ ret = clk_prepare_enable(sport->baud_clk);
	360	+ if (ret) {
	361	+ clk_disable_unprepare(sport->ipg_clk);
	362	+ return ret;
	363	+ }
	364	+ } else {
	365	+ clk_disable_unprepare(sport->baud_clk);
	366	+ clk_disable_unprepare(sport->ipg_clk);
	367	+ }
	368	+
	369	+ return 0;
	370	+}
	371	+
	372	+static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
	373	+{
	374	+ if (is_imx8qxp_lpuart(sport))
	375	+ return clk_get_rate(sport->baud_clk);
	376	+
	377	+ return clk_get_rate(sport->ipg_clk);
	378	+}
	379	+
	380	+#define lpuart_enable_clks(x) __lpuart_enable_clks(x, true)
	381	+#define lpuart_disable_clks(x) __lpuart_enable_clks(x, false)
314	382
315	383	static void lpuart_stop_tx(struct uart_port *port)
316	384	{
..	..	@@ -351,6 +419,7 @@
351	419	struct circ_buf *xmit = &sport->port.state->xmit;
352	420	struct scatterlist *sgl = sport->tx_sgl;
353	421	struct device *dev = sport->port.dev;
	422	+ struct dma_chan *chan = sport->dma_tx_chan;
354	423	int ret;
355	424
356	425	if (sport->dma_tx_in_progress)
..	..	@@ -369,17 +438,19 @@
369	438	sg_set_buf(sgl + 1, xmit->buf, xmit->head);
370	439	}
371	440
372		- ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
	441	+ ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
	442	+ DMA_TO_DEVICE);
373	443	if (!ret) {
374	444	dev_err(dev, "DMA mapping error for TX.\n");
375	445	return;
376	446	}
377	447
378		- sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
	448	+ sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
379	449	ret, DMA_MEM_TO_DEV,
380	450	DMA_PREP_INTERRUPT);
381	451	if (!sport->dma_tx_desc) {
382		- dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
	452	+ dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
	453	+ DMA_TO_DEVICE);
383	454	dev_err(dev, "Cannot prepare TX slave DMA!\n");
384	455	return;
385	456	}
..	..	@@ -388,7 +459,12 @@
388	459	sport->dma_tx_desc->callback_param = sport;
389	460	sport->dma_tx_in_progress = true;
390	461	sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
391		- dma_async_issue_pending(sport->dma_tx_chan);
	462	+ dma_async_issue_pending(chan);
	463	+}
	464	+
	465	+static bool lpuart_stopped_or_empty(struct uart_port *port)
	466	+{
	467	+ return uart_circ_empty(&port->state->xmit) \|\| uart_tx_stopped(port);
392	468	}
393	469
394	470	static void lpuart_dma_tx_complete(void *arg)
..	..	@@ -396,11 +472,13 @@
396	472	struct lpuart_port *sport = arg;
397	473	struct scatterlist *sgl = &sport->tx_sgl[0];
398	474	struct circ_buf *xmit = &sport->port.state->xmit;
	475	+ struct dma_chan *chan = sport->dma_tx_chan;
399	476	unsigned long flags;
400	477
401	478	spin_lock_irqsave(&sport->port.lock, flags);
402	479
403		- dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
	480	+ dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
	481	+ DMA_TO_DEVICE);
404	482
405	483	xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
406	484
..	..	@@ -418,10 +496,21 @@
418	496
419	497	spin_lock_irqsave(&sport->port.lock, flags);
420	498
421		- if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
	499	+ if (!lpuart_stopped_or_empty(&sport->port))
422	500	lpuart_dma_tx(sport);
423	501
424	502	spin_unlock_irqrestore(&sport->port.lock, flags);
	503	+}
	504	+
	505	+static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
	506	+{
	507	+ switch (sport->port.iotype) {
	508	+ case UPIO_MEM32:
	509	+ return sport->port.mapbase + UARTDATA;
	510	+ case UPIO_MEM32BE:
	511	+ return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
	512	+ }
	513	+ return sport->port.mapbase + UARTDR;
425	514	}
426	515
427	516	static int lpuart_dma_tx_request(struct uart_port *port)
..	..	@@ -431,7 +520,7 @@
431	520	struct dma_slave_config dma_tx_sconfig = {};
432	521	int ret;
433	522
434		- dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
	523	+ dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
435	524	dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
436	525	dma_tx_sconfig.dst_maxburst = 1;
437	526	dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
..	..	@@ -446,18 +535,50 @@
446	535	return 0;
447	536	}
448	537
	538	+static bool lpuart_is_32(struct lpuart_port *sport)
	539	+{
	540	+ return sport->port.iotype == UPIO_MEM32 \|\|
	541	+ sport->port.iotype == UPIO_MEM32BE;
	542	+}
	543	+
449	544	static void lpuart_flush_buffer(struct uart_port *port)
450	545	{
451	546	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
	547	+ struct dma_chan *chan = sport->dma_tx_chan;
	548	+ u32 val;
452	549
453	550	if (sport->lpuart_dma_tx_use) {
454	551	if (sport->dma_tx_in_progress) {
455		- dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
	552	+ dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
456	553	sport->dma_tx_nents, DMA_TO_DEVICE);
457	554	sport->dma_tx_in_progress = false;
458	555	}
459		- dmaengine_terminate_all(sport->dma_tx_chan);
	556	+ dmaengine_terminate_all(chan);
460	557	}
	558	+
	559	+ if (lpuart_is_32(sport)) {
	560	+ val = lpuart32_read(&sport->port, UARTFIFO);
	561	+ val \|= UARTFIFO_TXFLUSH \| UARTFIFO_RXFLUSH;
	562	+ lpuart32_write(&sport->port, val, UARTFIFO);
	563	+ } else {
	564	+ val = readb(sport->port.membase + UARTCFIFO);
	565	+ val \|= UARTCFIFO_TXFLUSH \| UARTCFIFO_RXFLUSH;
	566	+ writeb(val, sport->port.membase + UARTCFIFO);
	567	+ }
	568	+}
	569	+
	570	+static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
	571	+ u8 bit)
	572	+{
	573	+ while (!(readb(port->membase + offset) & bit))
	574	+ cpu_relax();
	575	+}
	576	+
	577	+static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
	578	+ u32 bit)
	579	+{
	580	+ while (!(lpuart32_read(port, offset) & bit))
	581	+ cpu_relax();
461	582	}
462	583
463	584	#if defined(CONFIG_CONSOLE_POLL)
..	..	@@ -503,9 +624,7 @@
503	624	static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
504	625	{
505	626	/* drain */
506		- while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
507		- barrier();
508		-
	627	+ lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
509	628	writeb(c, port->membase + UARTDR);
510	629	}
511	630
..	..	@@ -528,26 +647,24 @@
528	647	spin_lock_irqsave(&sport->port.lock, flags);
529	648
530	649	/* Disable Rx & Tx */
531		- lpuart32_write(&sport->port, UARTCTRL, 0);
	650	+ lpuart32_write(&sport->port, 0, UARTCTRL);
532	651
533	652	temp = lpuart32_read(&sport->port, UARTFIFO);
534	653
535	654	/* Enable Rx and Tx FIFO */
536		- lpuart32_write(&sport->port, UARTFIFO,
537		- temp \| UARTFIFO_RXFE \| UARTFIFO_TXFE);
	655	+ lpuart32_write(&sport->port, temp \| UARTFIFO_RXFE \| UARTFIFO_TXFE, UARTFIFO);
538	656
539	657	/* flush Tx and Rx FIFO */
540		- lpuart32_write(&sport->port, UARTFIFO,
541		- UARTFIFO_TXFLUSH \| UARTFIFO_RXFLUSH);
	658	+ lpuart32_write(&sport->port, UARTFIFO_TXFLUSH \| UARTFIFO_RXFLUSH, UARTFIFO);
542	659
543	660	/* explicitly clear RDRF */
544	661	if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
545	662	lpuart32_read(&sport->port, UARTDATA);
546		- lpuart32_write(&sport->port, UARTFIFO, UARTFIFO_RXUF);
	663	+ lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
547	664	}
548	665
549	666	/* Enable Rx and Tx */
550		- lpuart32_write(&sport->port, UARTCTRL, UARTCTRL_RE \| UARTCTRL_TE);
	667	+ lpuart32_write(&sport->port, UARTCTRL_RE \| UARTCTRL_TE, UARTCTRL);
551	668	spin_unlock_irqrestore(&sport->port.lock, flags);
552	669
553	670	return 0;
..	..	@@ -555,10 +672,8 @@
555	672
556	673	static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
557	674	{
558		- while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE))
559		- barrier();
560		-
561		- lpuart32_write(port, UARTDATA, c);
	675	+ lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
	676	+ lpuart32_write(port, c, UARTDATA);
562	677	}
563	678
564	679	static int lpuart32_poll_get_char(struct uart_port *port)
..	..	@@ -573,6 +688,18 @@
573	688	static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
574	689	{
575	690	struct circ_buf *xmit = &sport->port.state->xmit;
	691	+
	692	+ if (sport->port.x_char) {
	693	+ writeb(sport->port.x_char, sport->port.membase + UARTDR);
	694	+ sport->port.icount.tx++;
	695	+ sport->port.x_char = 0;
	696	+ return;
	697	+ }
	698	+
	699	+ if (lpuart_stopped_or_empty(&sport->port)) {
	700	+ lpuart_stop_tx(&sport->port);
	701	+ return;
	702	+ }
576	703
577	704	while (!uart_circ_empty(xmit) &&
578	705	(readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
..	..	@@ -592,6 +719,18 @@
592	719	{
593	720	struct circ_buf *xmit = &sport->port.state->xmit;
594	721	unsigned long txcnt;
	722	+
	723	+ if (sport->port.x_char) {
	724	+ lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
	725	+ sport->port.icount.tx++;
	726	+ sport->port.x_char = 0;
	727	+ return;
	728	+ }
	729	+
	730	+ if (lpuart_stopped_or_empty(&sport->port)) {
	731	+ lpuart32_stop_tx(&sport->port);
	732	+ return;
	733	+ }
595	734
596	735	txcnt = lpuart32_read(&sport->port, UARTWATER);
597	736	txcnt = txcnt >> UARTWATER_TXCNT_OFF;
..	..	@@ -616,14 +755,13 @@
616	755	{
617	756	struct lpuart_port *sport = container_of(port,
618	757	struct lpuart_port, port);
619		- struct circ_buf *xmit = &sport->port.state->xmit;
620	758	unsigned char temp;
621	759
622	760	temp = readb(port->membase + UARTCR2);
623	761	writeb(temp \| UARTCR2_TIE, port->membase + UARTCR2);
624	762
625	763	if (sport->lpuart_dma_tx_use) {
626		- if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
	764	+ if (!lpuart_stopped_or_empty(port))
627	765	lpuart_dma_tx(sport);
628	766	} else {
629	767	if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
..	..	@@ -636,11 +774,16 @@
636	774	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
637	775	unsigned long temp;
638	776
639		- temp = lpuart32_read(port, UARTCTRL);
640		- lpuart32_write(port, temp \| UARTCTRL_TIE, UARTCTRL);
	777	+ if (sport->lpuart_dma_tx_use) {
	778	+ if (!lpuart_stopped_or_empty(port))
	779	+ lpuart_dma_tx(sport);
	780	+ } else {
	781	+ temp = lpuart32_read(port, UARTCTRL);
	782	+ lpuart32_write(port, temp \| UARTCTRL_TIE, UARTCTRL);
641	783
642		- if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
643		- lpuart32_transmit_buffer(sport);
	784	+ if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
	785	+ lpuart32_transmit_buffer(sport);
	786	+ }
644	787	}
645	788
646	789	/* return TIOCSER_TEMT when transmitter is not busy */
..	..	@@ -662,56 +805,38 @@
662	805
663	806	static unsigned int lpuart32_tx_empty(struct uart_port *port)
664	807	{
665		- return (lpuart32_read(port, UARTSTAT) & UARTSTAT_TC) ?
666		- TIOCSER_TEMT : 0;
	808	+ struct lpuart_port *sport = container_of(port,
	809	+ struct lpuart_port, port);
	810	+ unsigned long stat = lpuart32_read(port, UARTSTAT);
	811	+ unsigned long sfifo = lpuart32_read(port, UARTFIFO);
	812	+ unsigned long ctrl = lpuart32_read(port, UARTCTRL);
	813	+
	814	+ if (sport->dma_tx_in_progress)
	815	+ return 0;
	816	+
	817	+ /*
	818	+ * LPUART Transmission Complete Flag may never be set while queuing a break
	819	+ * character, so avoid checking for transmission complete when UARTCTRL_SBK
	820	+ * is asserted.
	821	+ */
	822	+ if ((stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) \|\| ctrl & UARTCTRL_SBK)
	823	+ return TIOCSER_TEMT;
	824	+
	825	+ return 0;
667	826	}
668	827
669		-static bool lpuart_is_32(struct lpuart_port *sport)
	828	+static void lpuart_txint(struct lpuart_port *sport)
670	829	{
671		- return sport->port.iotype == UPIO_MEM32 \|\|
672		- sport->port.iotype == UPIO_MEM32BE;
673		-}
674		-
675		-static irqreturn_t lpuart_txint(int irq, void *dev_id)
676		-{
677		- struct lpuart_port *sport = dev_id;
678		- struct circ_buf *xmit = &sport->port.state->xmit;
679	830	unsigned long flags;
680	831
681	832	spin_lock_irqsave(&sport->port.lock, flags);
682		- if (sport->port.x_char) {
683		- if (lpuart_is_32(sport))
684		- lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
685		- else
686		- writeb(sport->port.x_char, sport->port.membase + UARTDR);
687		- goto out;
688		- }
689		-
690		- if (uart_circ_empty(xmit) \|\| uart_tx_stopped(&sport->port)) {
691		- if (lpuart_is_32(sport))
692		- lpuart32_stop_tx(&sport->port);
693		- else
694		- lpuart_stop_tx(&sport->port);
695		- goto out;
696		- }
697		-
698		- if (lpuart_is_32(sport))
699		- lpuart32_transmit_buffer(sport);
700		- else
701		- lpuart_transmit_buffer(sport);
702		-
703		- if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
704		- uart_write_wakeup(&sport->port);
705		-
706		-out:
	833	+ lpuart_transmit_buffer(sport);
707	834	spin_unlock_irqrestore(&sport->port.lock, flags);
708		- return IRQ_HANDLED;
709	835	}
710	836
711		-static irqreturn_t lpuart_rxint(int irq, void *dev_id)
	837	+static void lpuart_rxint(struct lpuart_port *sport)
712	838	{
713		- struct lpuart_port *sport = dev_id;
714		- unsigned int flg, ignored = 0;
	839	+ unsigned int flg, ignored = 0, overrun = 0;
715	840	struct tty_port *port = &sport->port.state->port;
716	841	unsigned long flags;
717	842	unsigned char rx, sr;
..	..	@@ -738,7 +863,7 @@
738	863	sport->port.icount.frame++;
739	864
740	865	if (sr & UARTSR1_OR)
741		- sport->port.icount.overrun++;
	866	+ overrun++;
742	867
743	868	if (sr & sport->port.ignore_status_mask) {
744	869	if (++ignored > 100)
..	..	@@ -756,24 +881,40 @@
756	881	if (sr & UARTSR1_OR)
757	882	flg = TTY_OVERRUN;
758	883
759		-#ifdef SUPPORT_SYSRQ
760	884	sport->port.sysrq = 0;
761		-#endif
762	885	}
763	886
764	887	tty_insert_flip_char(port, rx, flg);
765	888	}
766	889
767	890	out:
	891	+ if (overrun) {
	892	+ sport->port.icount.overrun += overrun;
	893	+
	894	+ /*
	895	+ * Overruns cause FIFO pointers to become missaligned.
	896	+ * Flushing the receive FIFO reinitializes the pointers.
	897	+ */
	898	+ writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
	899	+ writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
	900	+ }
	901	+
768	902	spin_unlock_irqrestore(&sport->port.lock, flags);
769	903
770	904	tty_flip_buffer_push(port);
771		- return IRQ_HANDLED;
772	905	}
773	906
774		-static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
	907	+static void lpuart32_txint(struct lpuart_port *sport)
775	908	{
776		- struct lpuart_port *sport = dev_id;
	909	+ unsigned long flags;
	910	+
	911	+ spin_lock_irqsave(&sport->port.lock, flags);
	912	+ lpuart32_transmit_buffer(sport);
	913	+ spin_unlock_irqrestore(&sport->port.lock, flags);
	914	+}
	915	+
	916	+static void lpuart32_rxint(struct lpuart_port *sport)
	917	+{
777	918	unsigned int flg, ignored = 0;
778	919	struct tty_port *port = &sport->port.state->port;
779	920	unsigned long flags;
..	..	@@ -820,9 +961,7 @@
820	961	if (sr & UARTSTAT_OR)
821	962	flg = TTY_OVERRUN;
822	963
823		-#ifdef SUPPORT_SYSRQ
824	964	sport->port.sysrq = 0;
825		-#endif
826	965	}
827	966
828	967	tty_insert_flip_char(port, rx, flg);
..	..	@@ -832,7 +971,6 @@
832	971	spin_unlock_irqrestore(&sport->port.lock, flags);
833	972
834	973	tty_flip_buffer_push(port);
835		- return IRQ_HANDLED;
836	974	}
837	975
838	976	static irqreturn_t lpuart_int(int irq, void *dev_id)
..	..	@@ -842,11 +980,20 @@
842	980
843	981	sts = readb(sport->port.membase + UARTSR1);
844	982
845		- if (sts & UARTSR1_RDRF)
846		- lpuart_rxint(irq, dev_id);
	983	+ /* SysRq, using dma, check for linebreak by framing err. */
	984	+ if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
	985	+ readb(sport->port.membase + UARTDR);
	986	+ uart_handle_break(&sport->port);
	987	+ /* linebreak produces some garbage, removing it */
	988	+ writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
	989	+ return IRQ_HANDLED;
	990	+ }
847	991
848		- if (sts & UARTSR1_TDRE)
849		- lpuart_txint(irq, dev_id);
	992	+ if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
	993	+ lpuart_rxint(sport);
	994	+
	995	+ if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
	996	+ lpuart_txint(sport);
850	997
851	998	return IRQ_HANDLED;
852	999	}
..	..	@@ -860,15 +1007,45 @@
860	1007	rxcount = lpuart32_read(&sport->port, UARTWATER);
861	1008	rxcount = rxcount >> UARTWATER_RXCNT_OFF;
862	1009
863		- if (sts & UARTSTAT_RDRF \|\| rxcount > 0)
864		- lpuart32_rxint(irq, dev_id);
	1010	+ if ((sts & UARTSTAT_RDRF \|\| rxcount > 0) && !sport->lpuart_dma_rx_use)
	1011	+ lpuart32_rxint(sport);
865	1012
866		- if ((sts & UARTSTAT_TDRE) &&
867		- !(lpuart32_read(&sport->port, UARTBAUD) & UARTBAUD_TDMAE))
868		- lpuart_txint(irq, dev_id);
	1013	+ if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
	1014	+ lpuart32_txint(sport);
869	1015
870	1016	lpuart32_write(&sport->port, sts, UARTSTAT);
871	1017	return IRQ_HANDLED;
	1018	+}
	1019	+
	1020	+
	1021	+static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
	1022	+ unsigned char *p, int count)
	1023	+{
	1024	+ while (count--) {
	1025	+ if (p && uart_handle_sysrq_char(port, p))
	1026	+ return;
	1027	+ p++;
	1028	+ }
	1029	+}
	1030	+
	1031	+static void lpuart_handle_sysrq(struct lpuart_port *sport)
	1032	+{
	1033	+ struct circ_buf *ring = &sport->rx_ring;
	1034	+ int count;
	1035	+
	1036	+ if (ring->head < ring->tail) {
	1037	+ count = sport->rx_sgl.length - ring->tail;
	1038	+ lpuart_handle_sysrq_chars(&sport->port,
	1039	+ ring->buf + ring->tail, count);
	1040	+ ring->tail = 0;
	1041	+ }
	1042	+
	1043	+ if (ring->head > ring->tail) {
	1044	+ count = ring->head - ring->tail;
	1045	+ lpuart_handle_sysrq_chars(&sport->port,
	1046	+ ring->buf + ring->tail, count);
	1047	+ ring->tail = ring->head;
	1048	+ }
872	1049	}
873	1050
874	1051	static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
..	..	@@ -876,31 +1053,68 @@
876	1053	struct tty_port *port = &sport->port.state->port;
877	1054	struct dma_tx_state state;
878	1055	enum dma_status dmastat;
	1056	+ struct dma_chan *chan = sport->dma_rx_chan;
879	1057	struct circ_buf *ring = &sport->rx_ring;
880	1058	unsigned long flags;
881	1059	int count = 0;
882		- unsigned char sr;
883	1060
884		- sr = readb(sport->port.membase + UARTSR1);
	1061	+ if (lpuart_is_32(sport)) {
	1062	+ unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
885	1063
886		- if (sr & (UARTSR1_PE \| UARTSR1_FE)) {
887		- /* Read DR to clear the error flags */
888		- readb(sport->port.membase + UARTDR);
	1064	+ if (sr & (UARTSTAT_PE \| UARTSTAT_FE)) {
	1065	+ /* Clear the error flags */
	1066	+ lpuart32_write(&sport->port, sr, UARTSTAT);
889	1067
890		- if (sr & UARTSR1_PE)
891		- sport->port.icount.parity++;
892		- else if (sr & UARTSR1_FE)
893		- sport->port.icount.frame++;
	1068	+ if (sr & UARTSTAT_PE)
	1069	+ sport->port.icount.parity++;
	1070	+ else if (sr & UARTSTAT_FE)
	1071	+ sport->port.icount.frame++;
	1072	+ }
	1073	+ } else {
	1074	+ unsigned char sr = readb(sport->port.membase + UARTSR1);
	1075	+
	1076	+ if (sr & (UARTSR1_PE \| UARTSR1_FE)) {
	1077	+ unsigned char cr2;
	1078	+
	1079	+ /* Disable receiver during this operation... */
	1080	+ cr2 = readb(sport->port.membase + UARTCR2);
	1081	+ cr2 &= ~UARTCR2_RE;
	1082	+ writeb(cr2, sport->port.membase + UARTCR2);
	1083	+
	1084	+ /* Read DR to clear the error flags */
	1085	+ readb(sport->port.membase + UARTDR);
	1086	+
	1087	+ if (sr & UARTSR1_PE)
	1088	+ sport->port.icount.parity++;
	1089	+ else if (sr & UARTSR1_FE)
	1090	+ sport->port.icount.frame++;
	1091	+ /*
	1092	+ * At this point parity/framing error is
	1093	+ * cleared However, since the DMA already read
	1094	+ * the data register and we had to read it
	1095	+ * again after reading the status register to
	1096	+ * properly clear the flags, the FIFO actually
	1097	+ * underflowed... This requires a clearing of
	1098	+ * the FIFO...
	1099	+ */
	1100	+ if (readb(sport->port.membase + UARTSFIFO) &
	1101	+ UARTSFIFO_RXUF) {
	1102	+ writeb(UARTSFIFO_RXUF,
	1103	+ sport->port.membase + UARTSFIFO);
	1104	+ writeb(UARTCFIFO_RXFLUSH,
	1105	+ sport->port.membase + UARTCFIFO);
	1106	+ }
	1107	+
	1108	+ cr2 \|= UARTCR2_RE;
	1109	+ writeb(cr2, sport->port.membase + UARTCR2);
	1110	+ }
894	1111	}
895	1112
896	1113	async_tx_ack(sport->dma_rx_desc);
897	1114
898	1115	spin_lock_irqsave(&sport->port.lock, flags);
899	1116
900		- dmastat = dmaengine_tx_status(sport->dma_rx_chan,
901		- sport->dma_rx_cookie,
902		- &state);
903		-
	1117	+ dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
904	1118	if (dmastat == DMA_ERROR) {
905	1119	dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
906	1120	spin_unlock_irqrestore(&sport->port.lock, flags);
..	..	@@ -908,7 +1122,8 @@
908	1122	}
909	1123
910	1124	/* CPU claims ownership of RX DMA buffer */
911		- dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
	1125	+ dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
	1126	+ DMA_FROM_DEVICE);
912	1127
913	1128	/*
914	1129	* ring->head points to the end of data already written by the DMA.
..	..	@@ -919,6 +1134,15 @@
919	1134	*/
920	1135	ring->head = sport->rx_sgl.length - state.residue;
921	1136	BUG_ON(ring->head > sport->rx_sgl.length);
	1137	+
	1138	+ /*
	1139	+ * Silent handling of keys pressed in the sysrq timeframe
	1140	+ */
	1141	+ if (sport->port.sysrq) {
	1142	+ lpuart_handle_sysrq(sport);
	1143	+ goto exit;
	1144	+ }
	1145	+
922	1146	/*
923	1147	* At this point ring->head may point to the first byte right after the
924	1148	* last byte of the dma buffer:
..	..	@@ -950,7 +1174,8 @@
950	1174	sport->port.icount.rx += count;
951	1175	}
952	1176
953		- dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
	1177	+exit:
	1178	+ dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
954	1179	DMA_FROM_DEVICE);
955	1180
956	1181	spin_unlock_irqrestore(&sport->port.lock, flags);
..	..	@@ -982,6 +1207,7 @@
982	1207	struct tty_port *port = &sport->port.state->port;
983	1208	struct tty_struct *tty = port->tty;
984	1209	struct ktermios *termios = &tty->termios;
	1210	+ struct dma_chan *chan = sport->dma_rx_chan;
985	1211
986	1212	baud = tty_get_baud_rate(tty);
987	1213
..	..	@@ -994,30 +1220,28 @@
994	1220	* 10ms at any baud rate.
995	1221	*/
996	1222	sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
997		- sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
	1223	+ sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len));
998	1224	if (sport->rx_dma_rng_buf_len < 16)
999	1225	sport->rx_dma_rng_buf_len = 16;
1000	1226
1001		- ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1002		- if (!ring->buf) {
1003		- dev_err(sport->port.dev, "Ring buf alloc failed\n");
	1227	+ ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
	1228	+ if (!ring->buf)
1004	1229	return -ENOMEM;
1005		- }
1006	1230
1007	1231	sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1008		- sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1009		- nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
	1232	+ nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
	1233	+ DMA_FROM_DEVICE);
1010	1234
1011	1235	if (!nent) {
1012	1236	dev_err(sport->port.dev, "DMA Rx mapping error\n");
1013	1237	return -EINVAL;
1014	1238	}
1015	1239
1016		- dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
	1240	+ dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1017	1241	dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1018	1242	dma_rx_sconfig.src_maxburst = 1;
1019	1243	dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1020		- ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
	1244	+ ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
1021	1245
1022	1246	if (ret < 0) {
1023	1247	dev_err(sport->port.dev,
..	..	@@ -1025,7 +1249,7 @@
1025	1249	return ret;
1026	1250	}
1027	1251
1028		- sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
	1252	+ sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1029	1253	sg_dma_address(&sport->rx_sgl),
1030	1254	sport->rx_sgl.length,
1031	1255	sport->rx_sgl.length / 2,
..	..	@@ -1039,10 +1263,16 @@
1039	1263	sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1040	1264	sport->dma_rx_desc->callback_param = sport;
1041	1265	sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1042		- dma_async_issue_pending(sport->dma_rx_chan);
	1266	+ dma_async_issue_pending(chan);
1043	1267
1044		- writeb(readb(sport->port.membase + UARTCR5) \| UARTCR5_RDMAS,
1045		- sport->port.membase + UARTCR5);
	1268	+ if (lpuart_is_32(sport)) {
	1269	+ unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
	1270	+
	1271	+ lpuart32_write(&sport->port, temp \| UARTBAUD_RDMAE, UARTBAUD);
	1272	+ } else {
	1273	+ writeb(readb(sport->port.membase + UARTCR5) \| UARTCR5_RDMAS,
	1274	+ sport->port.membase + UARTCR5);
	1275	+ }
1046	1276
1047	1277	return 0;
1048	1278	}
..	..	@@ -1051,11 +1281,11 @@
1051	1281	{
1052	1282	struct lpuart_port *sport = container_of(port,
1053	1283	struct lpuart_port, port);
	1284	+ struct dma_chan *chan = sport->dma_rx_chan;
1054	1285
1055		- if (sport->dma_rx_chan)
1056		- dmaengine_terminate_all(sport->dma_rx_chan);
1057		-
1058		- dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
	1286	+ dmaengine_terminate_all(chan);
	1287	+ del_timer_sync(&sport->lpuart_timer);
	1288	+ dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1059	1289	kfree(sport->rx_ring.buf);
1060	1290	sport->rx_ring.tail = 0;
1061	1291	sport->rx_ring.head = 0;
..	..	@@ -1083,7 +1313,7 @@
1083	1313	modem \|= UARTMODEM_TXRTSE;
1084	1314
1085	1315	/*
1086		- * RTS needs to be logic HIGH either during transer _or_ after
	1316	+ * RTS needs to be logic HIGH either during transfer _or_ after
1087	1317	* transfer, other variants are not supported by the hardware.
1088	1318	*/
1089	1319
..	..	@@ -1114,6 +1344,57 @@
1114	1344	return 0;
1115	1345	}
1116	1346
	1347	+static int lpuart32_config_rs485(struct uart_port *port,
	1348	+ struct serial_rs485 *rs485)
	1349	+{
	1350	+ struct lpuart_port *sport = container_of(port,
	1351	+ struct lpuart_port, port);
	1352	+
	1353	+ unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
	1354	+ & ~(UARTMODEM_TXRTSPOL \| UARTMODEM_TXRTSE);
	1355	+ lpuart32_write(&sport->port, modem, UARTMODIR);
	1356	+
	1357	+ /* clear unsupported configurations */
	1358	+ rs485->delay_rts_before_send = 0;
	1359	+ rs485->delay_rts_after_send = 0;
	1360	+ rs485->flags &= ~SER_RS485_RX_DURING_TX;
	1361	+
	1362	+ if (rs485->flags & SER_RS485_ENABLED) {
	1363	+ /* Enable auto RS-485 RTS mode */
	1364	+ modem \|= UARTMODEM_TXRTSE;
	1365	+
	1366	+ /*
	1367	+ * RTS needs to be logic HIGH either during transfer _or_ after
	1368	+ * transfer, other variants are not supported by the hardware.
	1369	+ */
	1370	+
	1371	+ if (!(rs485->flags & (SER_RS485_RTS_ON_SEND \|
	1372	+ SER_RS485_RTS_AFTER_SEND)))
	1373	+ rs485->flags \|= SER_RS485_RTS_ON_SEND;
	1374	+
	1375	+ if (rs485->flags & SER_RS485_RTS_ON_SEND &&
	1376	+ rs485->flags & SER_RS485_RTS_AFTER_SEND)
	1377	+ rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
	1378	+
	1379	+ /*
	1380	+ * The hardware defaults to RTS logic HIGH while transfer.
	1381	+ * Switch polarity in case RTS shall be logic HIGH
	1382	+ * after transfer.
	1383	+ * Note: UART is assumed to be active high.
	1384	+ */
	1385	+ if (rs485->flags & SER_RS485_RTS_ON_SEND)
	1386	+ modem \|= UARTMODEM_TXRTSPOL;
	1387	+ else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
	1388	+ modem &= ~UARTMODEM_TXRTSPOL;
	1389	+ }
	1390	+
	1391	+ /* Store the new configuration */
	1392	+ sport->port.rs485 = *rs485;
	1393	+
	1394	+ lpuart32_write(&sport->port, modem, UARTMODIR);
	1395	+ return 0;
	1396	+}
	1397	+
1117	1398	static unsigned int lpuart_get_mctrl(struct uart_port *port)
1118	1399	{
1119	1400	unsigned int temp = 0;
..	..	@@ -1131,17 +1412,7 @@
1131	1412
1132	1413	static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1133	1414	{
1134		- unsigned int temp = 0;
1135		- unsigned long reg;
1136		-
1137		- reg = lpuart32_read(port, UARTMODIR);
1138		- if (reg & UARTMODIR_TXCTSE)
1139		- temp \|= TIOCM_CTS;
1140		-
1141		- if (reg & UARTMODIR_RXRTSE)
1142		- temp \|= TIOCM_RTS;
1143		-
1144		- return temp;
	1415	+ return 0;
1145	1416	}
1146	1417
1147	1418	static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
..	..	@@ -1167,18 +1438,7 @@
1167	1438
1168	1439	static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1169	1440	{
1170		- unsigned long temp;
1171	1441
1172		- temp = lpuart32_read(port, UARTMODIR) &
1173		- ~(UARTMODIR_RXRTSE \| UARTMODIR_TXCTSE);
1174		-
1175		- if (mctrl & TIOCM_RTS)
1176		- temp \|= UARTMODIR_RXRTSE;
1177		-
1178		- if (mctrl & TIOCM_CTS)
1179		- temp \|= UARTMODIR_TXCTSE;
1180		-
1181		- lpuart32_write(port, temp, UARTMODIR);
1182	1442	}
1183	1443
1184	1444	static void lpuart_break_ctl(struct uart_port *port, int break_state)
..	..	@@ -1197,12 +1457,34 @@
1197	1457	{
1198	1458	unsigned long temp;
1199	1459
1200		- temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
	1460	+ temp = lpuart32_read(port, UARTCTRL);
1201	1461
1202		- if (break_state != 0)
1203		- temp \|= UARTCTRL_SBK;
1204		-
1205		- lpuart32_write(port, temp, UARTCTRL);
	1462	+ /*
	1463	+ * LPUART IP now has two known bugs, one is CTS has higher priority than the
	1464	+ * break signal, which causes the break signal sending through UARTCTRL_SBK
	1465	+ * may impacted by the CTS input if the HW flow control is enabled. It
	1466	+ * exists on all platforms we support in this driver.
	1467	+ * Another bug is i.MX8QM LPUART may have an additional break character
	1468	+ * being sent after SBK was cleared.
	1469	+ * To avoid above two bugs, we use Transmit Data Inversion function to send
	1470	+ * the break signal instead of UARTCTRL_SBK.
	1471	+ */
	1472	+ if (break_state != 0) {
	1473	+ /*
	1474	+ * Disable the transmitter to prevent any data from being sent out
	1475	+ * during break, then invert the TX line to send break.
	1476	+ */
	1477	+ temp &= ~UARTCTRL_TE;
	1478	+ lpuart32_write(port, temp, UARTCTRL);
	1479	+ temp \|= UARTCTRL_TXINV;
	1480	+ lpuart32_write(port, temp, UARTCTRL);
	1481	+ } else {
	1482	+ /* Disable the TXINV to turn off break and re-enable transmitter. */
	1483	+ temp &= ~UARTCTRL_TXINV;
	1484	+ lpuart32_write(port, temp, UARTCTRL);
	1485	+ temp \|= UARTCTRL_TE;
	1486	+ lpuart32_write(port, temp, UARTCTRL);
	1487	+ }
1206	1488	}
1207	1489
1208	1490	static void lpuart_setup_watermark(struct lpuart_port *sport)
..	..	@@ -1237,6 +1519,17 @@
1237	1519	writeb(cr2_saved, sport->port.membase + UARTCR2);
1238	1520	}
1239	1521
	1522	+static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
	1523	+{
	1524	+ unsigned char cr2;
	1525	+
	1526	+ lpuart_setup_watermark(sport);
	1527	+
	1528	+ cr2 = readb(sport->port.membase + UARTCR2);
	1529	+ cr2 \|= UARTCR2_RIE \| UARTCR2_RE \| UARTCR2_TE;
	1530	+ writeb(cr2, sport->port.membase + UARTCR2);
	1531	+}
	1532	+
1240	1533	static void lpuart32_setup_watermark(struct lpuart_port *sport)
1241	1534	{
1242	1535	unsigned long val, ctrl;
..	..	@@ -1262,11 +1555,108 @@
1262	1555	lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1263	1556	}
1264	1557
	1558	+static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
	1559	+{
	1560	+ u32 temp;
	1561	+
	1562	+ lpuart32_setup_watermark(sport);
	1563	+
	1564	+ temp = lpuart32_read(&sport->port, UARTCTRL);
	1565	+ temp \|= UARTCTRL_RE \| UARTCTRL_TE \| UARTCTRL_ILIE;
	1566	+ lpuart32_write(&sport->port, temp, UARTCTRL);
	1567	+}
	1568	+
1265	1569	static void rx_dma_timer_init(struct lpuart_port *sport)
1266	1570	{
1267		- timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1268		- sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1269		- add_timer(&sport->lpuart_timer);
	1571	+ timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
	1572	+ sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
	1573	+ add_timer(&sport->lpuart_timer);
	1574	+}
	1575	+
	1576	+static void lpuart_request_dma(struct lpuart_port *sport)
	1577	+{
	1578	+ sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
	1579	+ if (IS_ERR(sport->dma_tx_chan)) {
	1580	+ dev_dbg_once(sport->port.dev,
	1581	+ "DMA tx channel request failed, operating without tx DMA (%ld)\n",
	1582	+ PTR_ERR(sport->dma_tx_chan));
	1583	+ sport->dma_tx_chan = NULL;
	1584	+ }
	1585	+
	1586	+ sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
	1587	+ if (IS_ERR(sport->dma_rx_chan)) {
	1588	+ dev_dbg_once(sport->port.dev,
	1589	+ "DMA rx channel request failed, operating without rx DMA (%ld)\n",
	1590	+ PTR_ERR(sport->dma_rx_chan));
	1591	+ sport->dma_rx_chan = NULL;
	1592	+ }
	1593	+}
	1594	+
	1595	+static void lpuart_tx_dma_startup(struct lpuart_port *sport)
	1596	+{
	1597	+ u32 uartbaud;
	1598	+ int ret;
	1599	+
	1600	+ if (uart_console(&sport->port))
	1601	+ goto err;
	1602	+
	1603	+ if (!sport->dma_tx_chan)
	1604	+ goto err;
	1605	+
	1606	+ ret = lpuart_dma_tx_request(&sport->port);
	1607	+ if (ret)
	1608	+ goto err;
	1609	+
	1610	+ init_waitqueue_head(&sport->dma_wait);
	1611	+ sport->lpuart_dma_tx_use = true;
	1612	+ if (lpuart_is_32(sport)) {
	1613	+ uartbaud = lpuart32_read(&sport->port, UARTBAUD);
	1614	+ lpuart32_write(&sport->port,
	1615	+ uartbaud \| UARTBAUD_TDMAE, UARTBAUD);
	1616	+ } else {
	1617	+ writeb(readb(sport->port.membase + UARTCR5) \|
	1618	+ UARTCR5_TDMAS, sport->port.membase + UARTCR5);
	1619	+ }
	1620	+
	1621	+ return;
	1622	+
	1623	+err:
	1624	+ sport->lpuart_dma_tx_use = false;
	1625	+}
	1626	+
	1627	+static void lpuart_rx_dma_startup(struct lpuart_port *sport)
	1628	+{
	1629	+ int ret;
	1630	+ unsigned char cr3;
	1631	+
	1632	+ if (uart_console(&sport->port))
	1633	+ goto err;
	1634	+
	1635	+ if (!sport->dma_rx_chan)
	1636	+ goto err;
	1637	+
	1638	+ ret = lpuart_start_rx_dma(sport);
	1639	+ if (ret)
	1640	+ goto err;
	1641	+
	1642	+ /* set Rx DMA timeout */
	1643	+ sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
	1644	+ if (!sport->dma_rx_timeout)
	1645	+ sport->dma_rx_timeout = 1;
	1646	+
	1647	+ sport->lpuart_dma_rx_use = true;
	1648	+ rx_dma_timer_init(sport);
	1649	+
	1650	+ if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
	1651	+ cr3 = readb(sport->port.membase + UARTCR3);
	1652	+ cr3 \|= UARTCR3_FEIE;
	1653	+ writeb(cr3, sport->port.membase + UARTCR3);
	1654	+ }
	1655	+
	1656	+ return;
	1657	+
	1658	+err:
	1659	+ sport->lpuart_dma_rx_use = false;
1270	1660	}
1271	1661
1272	1662	static int lpuart_startup(struct uart_port *port)
..	..	@@ -1278,46 +1668,43 @@
1278	1668	/* determine FIFO size and enable FIFO mode */
1279	1669	temp = readb(sport->port.membase + UARTPFIFO);
1280	1670
1281		- sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1282		- UARTPFIFO_FIFOSIZE_MASK) + 1);
1283		-
	1671	+ sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
	1672	+ UARTPFIFO_FIFOSIZE_MASK);
1284	1673	sport->port.fifosize = sport->txfifo_size;
1285	1674
1286		- sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1287		- UARTPFIFO_FIFOSIZE_MASK) + 1);
	1675	+ sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
	1676	+ UARTPFIFO_FIFOSIZE_MASK);
	1677	+
	1678	+ lpuart_request_dma(sport);
1288	1679
1289	1680	spin_lock_irqsave(&sport->port.lock, flags);
1290	1681
1291		- lpuart_setup_watermark(sport);
	1682	+ lpuart_setup_watermark_enable(sport);
1292	1683
1293		- temp = readb(sport->port.membase + UARTCR2);
1294		- temp \|= (UARTCR2_RIE \| UARTCR2_TIE \| UARTCR2_RE \| UARTCR2_TE);
1295		- writeb(temp, sport->port.membase + UARTCR2);
1296		-
1297		- if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1298		- /* set Rx DMA timeout */
1299		- sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1300		- if (!sport->dma_rx_timeout)
1301		- sport->dma_rx_timeout = 1;
1302		-
1303		- sport->lpuart_dma_rx_use = true;
1304		- rx_dma_timer_init(sport);
1305		- } else {
1306		- sport->lpuart_dma_rx_use = false;
1307		- }
1308		-
1309		- if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1310		- init_waitqueue_head(&sport->dma_wait);
1311		- sport->lpuart_dma_tx_use = true;
1312		- temp = readb(port->membase + UARTCR5);
1313		- writeb(temp \| UARTCR5_TDMAS, port->membase + UARTCR5);
1314		- } else {
1315		- sport->lpuart_dma_tx_use = false;
1316		- }
	1684	+ lpuart_rx_dma_startup(sport);
	1685	+ lpuart_tx_dma_startup(sport);
1317	1686
1318	1687	spin_unlock_irqrestore(&sport->port.lock, flags);
1319	1688
1320	1689	return 0;
	1690	+}
	1691	+
	1692	+static void lpuart32_configure(struct lpuart_port *sport)
	1693	+{
	1694	+ unsigned long temp;
	1695	+
	1696	+ if (sport->lpuart_dma_rx_use) {
	1697	+ /* RXWATER must be 0 */
	1698	+ temp = lpuart32_read(&sport->port, UARTWATER);
	1699	+ temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
	1700	+ lpuart32_write(&sport->port, temp, UARTWATER);
	1701	+ }
	1702	+ temp = lpuart32_read(&sport->port, UARTCTRL);
	1703	+ if (!sport->lpuart_dma_rx_use)
	1704	+ temp \|= UARTCTRL_RIE;
	1705	+ if (!sport->lpuart_dma_tx_use)
	1706	+ temp \|= UARTCTRL_TIE;
	1707	+ lpuart32_write(&sport->port, temp, UARTCTRL);
1321	1708	}
1322	1709
1323	1710	static int lpuart32_startup(struct uart_port *port)
..	..	@@ -1329,23 +1716,59 @@
1329	1716	/* determine FIFO size */
1330	1717	temp = lpuart32_read(&sport->port, UARTFIFO);
1331	1718
1332		- sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1333		- UARTFIFO_FIFOSIZE_MASK) - 1);
	1719	+ sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
	1720	+ UARTFIFO_FIFOSIZE_MASK);
	1721	+ sport->port.fifosize = sport->txfifo_size;
1334	1722
1335		- sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1336		- UARTFIFO_FIFOSIZE_MASK) - 1);
	1723	+ sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
	1724	+ UARTFIFO_FIFOSIZE_MASK);
	1725	+
	1726	+ /*
	1727	+ * The LS1021A and LS1028A have a fixed FIFO depth of 16 words.
	1728	+ * Although they support the RX/TXSIZE fields, their encoding is
	1729	+ * different. Eg the reference manual states 0b101 is 16 words.
	1730	+ */
	1731	+ if (is_layerscape_lpuart(sport)) {
	1732	+ sport->rxfifo_size = 16;
	1733	+ sport->txfifo_size = 16;
	1734	+ sport->port.fifosize = sport->txfifo_size;
	1735	+ }
	1736	+
	1737	+ lpuart_request_dma(sport);
1337	1738
1338	1739	spin_lock_irqsave(&sport->port.lock, flags);
1339	1740
1340		- lpuart32_setup_watermark(sport);
	1741	+ lpuart32_setup_watermark_enable(sport);
1341	1742
1342		- temp = lpuart32_read(&sport->port, UARTCTRL);
1343		- temp \|= (UARTCTRL_RIE \| UARTCTRL_TIE \| UARTCTRL_RE \| UARTCTRL_TE);
1344		- temp \|= UARTCTRL_ILIE;
1345		- lpuart32_write(&sport->port, temp, UARTCTRL);
	1743	+ lpuart_rx_dma_startup(sport);
	1744	+ lpuart_tx_dma_startup(sport);
	1745	+
	1746	+ lpuart32_configure(sport);
1346	1747
1347	1748	spin_unlock_irqrestore(&sport->port.lock, flags);
1348	1749	return 0;
	1750	+}
	1751	+
	1752	+static void lpuart_dma_shutdown(struct lpuart_port *sport)
	1753	+{
	1754	+ if (sport->lpuart_dma_rx_use) {
	1755	+ lpuart_dma_rx_free(&sport->port);
	1756	+ sport->lpuart_dma_rx_use = false;
	1757	+ }
	1758	+
	1759	+ if (sport->lpuart_dma_tx_use) {
	1760	+ if (wait_event_interruptible(sport->dma_wait,
	1761	+ !sport->dma_tx_in_progress) != false) {
	1762	+ sport->dma_tx_in_progress = false;
	1763	+ dmaengine_terminate_all(sport->dma_tx_chan);
	1764	+ }
	1765	+ sport->lpuart_dma_tx_use = false;
	1766	+ }
	1767	+
	1768	+ if (sport->dma_tx_chan)
	1769	+ dma_release_channel(sport->dma_tx_chan);
	1770	+ if (sport->dma_rx_chan)
	1771	+ dma_release_channel(sport->dma_rx_chan);
1349	1772	}
1350	1773
1351	1774	static void lpuart_shutdown(struct uart_port *port)
..	..	@@ -1364,24 +1787,13 @@
1364	1787
1365	1788	spin_unlock_irqrestore(&port->lock, flags);
1366	1789
1367		- if (sport->lpuart_dma_rx_use) {
1368		- del_timer_sync(&sport->lpuart_timer);
1369		- lpuart_dma_rx_free(&sport->port);
1370		- }
1371		-
1372		- if (sport->lpuart_dma_tx_use) {
1373		- if (wait_event_interruptible(sport->dma_wait,
1374		- !sport->dma_tx_in_progress) != false) {
1375		- sport->dma_tx_in_progress = false;
1376		- dmaengine_terminate_all(sport->dma_tx_chan);
1377		- }
1378		-
1379		- lpuart_stop_tx(port);
1380		- }
	1790	+ lpuart_dma_shutdown(sport);
1381	1791	}
1382	1792
1383	1793	static void lpuart32_shutdown(struct uart_port *port)
1384	1794	{
	1795	+ struct lpuart_port *sport =
	1796	+ container_of(port, struct lpuart_port, port);
1385	1797	unsigned long temp;
1386	1798	unsigned long flags;
1387	1799
..	..	@@ -1394,6 +1806,8 @@
1394	1806	lpuart32_write(port, temp, UARTCTRL);
1395	1807
1396	1808	spin_unlock_irqrestore(&port->lock, flags);
	1809	+
	1810	+ lpuart_dma_shutdown(sport);
1397	1811	}
1398	1812
1399	1813	static void
..	..	@@ -1447,21 +1861,18 @@
1447	1861	if (sport->port.rs485.flags & SER_RS485_ENABLED)
1448	1862	termios->c_cflag &= ~CRTSCTS;
1449	1863
1450		- if (termios->c_cflag & CRTSCTS) {
1451		- modem \|= (UARTMODEM_RXRTSE \| UARTMODEM_TXCTSE);
1452		- } else {
1453		- termios->c_cflag &= ~CRTSCTS;
	1864	+ if (termios->c_cflag & CRTSCTS)
	1865	+ modem \|= UARTMODEM_RXRTSE \| UARTMODEM_TXCTSE;
	1866	+ else
1454	1867	modem &= ~(UARTMODEM_RXRTSE \| UARTMODEM_TXCTSE);
1455		- }
1456	1868
1457		- if (termios->c_cflag & CSTOPB)
1458		- termios->c_cflag &= ~CSTOPB;
	1869	+ termios->c_cflag &= ~CSTOPB;
1459	1870
1460	1871	/* parity must be enabled when CS7 to match 8-bits format */
1461	1872	if ((termios->c_cflag & CSIZE) == CS7)
1462	1873	termios->c_cflag \|= PARENB;
1463	1874
1464		- if ((termios->c_cflag & PARENB)) {
	1875	+ if (termios->c_cflag & PARENB) {
1465	1876	if (termios->c_cflag & CMSPAR) {
1466	1877	cr1 &= ~UARTCR1_PE;
1467	1878	if (termios->c_cflag & PARODD)
..	..	@@ -1491,16 +1902,14 @@
1491	1902	* Since timer function acqures sport->port.lock, need to stop before
1492	1903	* acquring same lock because otherwise del_timer_sync() can deadlock.
1493	1904	*/
1494		- if (old && sport->lpuart_dma_rx_use) {
1495		- del_timer_sync(&sport->lpuart_timer);
	1905	+ if (old && sport->lpuart_dma_rx_use)
1496	1906	lpuart_dma_rx_free(&sport->port);
1497		- }
1498	1907
1499	1908	spin_lock_irqsave(&sport->port.lock, flags);
1500	1909
1501	1910	sport->port.read_status_mask = 0;
1502	1911	if (termios->c_iflag & INPCK)
1503		- sport->port.read_status_mask \|= (UARTSR1_FE \| UARTSR1_PE);
	1912	+ sport->port.read_status_mask \|= UARTSR1_FE \| UARTSR1_PE;
1504	1913	if (termios->c_iflag & (IGNBRK \| BRKINT \| PARMRK))
1505	1914	sport->port.read_status_mask \|= UARTSR1_FE;
1506	1915
..	..	@@ -1522,8 +1931,7 @@
1522	1931	uart_update_timeout(port, termios->c_cflag, baud);
1523	1932
1524	1933	/* wait transmit engin complete */
1525		- while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1526		- barrier();
	1934	+ lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1527	1935
1528	1936	/* disable transmit and receive */
1529	1937	writeb(old_cr2 & ~(UARTCR2_TE \| UARTCR2_RE),
..	..	@@ -1555,11 +1963,12 @@
1555	1963	spin_unlock_irqrestore(&sport->port.lock, flags);
1556	1964	}
1557	1965
1558		-static void
1559		-lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate)
	1966	+static void __lpuart32_serial_setbrg(struct uart_port *port,
	1967	+ unsigned int baudrate, bool use_rx_dma,
	1968	+ bool use_tx_dma)
1560	1969	{
1561	1970	u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1562		- u32 clk = sport->port.uartclk;
	1971	+ u32 clk = port->uartclk;
1563	1972
1564	1973	/*
1565	1974	* The idea is to use the best OSR (over-sampling rate) possible.
..	..	@@ -1593,6 +2002,9 @@
1593	2002	tmp_sbr++;
1594	2003	}
1595	2004
	2005	+ if (tmp_sbr > UARTBAUD_SBR_MASK)
	2006	+ continue;
	2007	+
1596	2008	if (tmp_diff <= baud_diff) {
1597	2009	baud_diff = tmp_diff;
1598	2010	osr = tmp_osr;
..	..	@@ -1605,24 +2017,36 @@
1605	2017
1606	2018	/* handle buadrate outside acceptable rate */
1607	2019	if (baud_diff > ((baudrate / 100) * 3))
1608		- dev_warn(sport->port.dev,
	2020	+ dev_warn(port->dev,
1609	2021	"unacceptable baud rate difference of more than 3%%\n");
1610	2022
1611		- tmp = lpuart32_read(&sport->port, UARTBAUD);
	2023	+ tmp = lpuart32_read(port, UARTBAUD);
1612	2024
1613	2025	if ((osr > 3) && (osr < 8))
1614	2026	tmp \|= UARTBAUD_BOTHEDGE;
1615	2027
1616	2028	tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
1617		- tmp \|= (((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT);
	2029	+ tmp \|= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
1618	2030
1619	2031	tmp &= ~UARTBAUD_SBR_MASK;
1620	2032	tmp \|= sbr & UARTBAUD_SBR_MASK;
1621	2033
1622		- tmp &= ~(UARTBAUD_TDMAE \| UARTBAUD_RDMAE);
	2034	+ if (!use_rx_dma)
	2035	+ tmp &= ~UARTBAUD_RDMAE;
	2036	+ if (!use_tx_dma)
	2037	+ tmp &= ~UARTBAUD_TDMAE;
1623	2038
1624		- lpuart32_write(&sport->port, tmp, UARTBAUD);
	2039	+ lpuart32_write(port, tmp, UARTBAUD);
1625	2040	}
	2041	+
	2042	+static void lpuart32_serial_setbrg(struct lpuart_port *sport,
	2043	+ unsigned int baudrate)
	2044	+{
	2045	+ __lpuart32_serial_setbrg(&sport->port, baudrate,
	2046	+ sport->lpuart_dma_rx_use,
	2047	+ sport->lpuart_dma_tx_use);
	2048	+}
	2049	+
1626	2050
1627	2051	static void
1628	2052	lpuart32_set_termios(struct uart_port port, struct ktermios termios,
..	..	@@ -1663,11 +2087,18 @@
1663	2087	ctrl \|= UARTCTRL_M;
1664	2088	}
1665	2089
	2090	+ /*
	2091	+ * When auto RS-485 RTS mode is enabled,
	2092	+ * hardware flow control need to be disabled.
	2093	+ */
	2094	+ if (sport->port.rs485.flags & SER_RS485_ENABLED)
	2095	+ termios->c_cflag &= ~CRTSCTS;
	2096	+
1666	2097	if (termios->c_cflag & CRTSCTS) {
1667		- modem \|= (UARTMODEM_RXRTSE \| UARTMODEM_TXCTSE);
	2098	+ modem \|= (UARTMODIR_RXRTSE \| UARTMODIR_TXCTSE);
1668	2099	} else {
1669	2100	termios->c_cflag &= ~CRTSCTS;
1670		- modem &= ~(UARTMODEM_RXRTSE \| UARTMODEM_TXCTSE);
	2101	+ modem &= ~(UARTMODIR_RXRTSE \| UARTMODIR_TXCTSE);
1671	2102	}
1672	2103
1673	2104	if (termios->c_cflag & CSTOPB)
..	..	@@ -1682,7 +2113,7 @@
1682	2113	ctrl &= ~UARTCTRL_PE;
1683	2114	ctrl \|= UARTCTRL_M;
1684	2115	} else {
1685		- ctrl \|= UARTCR1_PE;
	2116	+ ctrl \|= UARTCTRL_PE;
1686	2117	if ((termios->c_cflag & CSIZE) == CS8)
1687	2118	ctrl \|= UARTCTRL_M;
1688	2119	if (termios->c_cflag & PARODD)
..	..	@@ -1697,11 +2128,21 @@
1697	2128	/* ask the core to calculate the divisor */
1698	2129	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
1699	2130
	2131	+ /*
	2132	+ * Need to update the Ring buffer length according to the selected
	2133	+ * baud rate and restart Rx DMA path.
	2134	+ *
	2135	+ * Since timer function acqures sport->port.lock, need to stop before
	2136	+ * acquring same lock because otherwise del_timer_sync() can deadlock.
	2137	+ */
	2138	+ if (old && sport->lpuart_dma_rx_use)
	2139	+ lpuart_dma_rx_free(&sport->port);
	2140	+
1700	2141	spin_lock_irqsave(&sport->port.lock, flags);
1701	2142
1702	2143	sport->port.read_status_mask = 0;
1703	2144	if (termios->c_iflag & INPCK)
1704		- sport->port.read_status_mask \|= (UARTSTAT_FE \| UARTSTAT_PE);
	2145	+ sport->port.read_status_mask \|= UARTSTAT_FE \| UARTSTAT_PE;
1705	2146	if (termios->c_iflag & (IGNBRK \| BRKINT \| PARMRK))
1706	2147	sport->port.read_status_mask \|= UARTSTAT_FE;
1707	2148
..	..	@@ -1722,9 +2163,15 @@
1722	2163	/* update the per-port timeout */
1723	2164	uart_update_timeout(port, termios->c_cflag, baud);
1724	2165
1725		- /* wait transmit engin complete */
1726		- while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
1727		- barrier();
	2166	+ /*
	2167	+ * LPUART Transmission Complete Flag may never be set while queuing a break
	2168	+ * character, so skip waiting for transmission complete when UARTCTRL_SBK is
	2169	+ * asserted.
	2170	+ */
	2171	+ if (!(old_ctrl & UARTCTRL_SBK)) {
	2172	+ lpuart32_write(&sport->port, 0, UARTMODIR);
	2173	+ lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
	2174	+ }
1728	2175
1729	2176	/* disable transmit and receive */
1730	2177	lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE \| UARTCTRL_RE),
..	..	@@ -1734,6 +2181,13 @@
1734	2181	lpuart32_write(&sport->port, modem, UARTMODIR);
1735	2182	lpuart32_write(&sport->port, ctrl, UARTCTRL);
1736	2183	/* restore control register */
	2184	+
	2185	+ if (old && sport->lpuart_dma_rx_use) {
	2186	+ if (!lpuart_start_rx_dma(sport))
	2187	+ rx_dma_timer_init(sport);
	2188	+ else
	2189	+ sport->lpuart_dma_rx_use = false;
	2190	+ }
1737	2191
1738	2192	spin_unlock_irqrestore(&sport->port.lock, flags);
1739	2193	}
..	..	@@ -1832,17 +2286,13 @@
1832	2286	#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1833	2287	static void lpuart_console_putchar(struct uart_port *port, int ch)
1834	2288	{
1835		- while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1836		- barrier();
1837		-
	2289	+ lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
1838	2290	writeb(ch, port->membase + UARTDR);
1839	2291	}
1840	2292
1841	2293	static void lpuart32_console_putchar(struct uart_port *port, int ch)
1842	2294	{
1843		- while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE))
1844		- barrier();
1845		-
	2295	+ lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
1846	2296	lpuart32_write(port, ch, UARTDATA);
1847	2297	}
1848	2298
..	..	@@ -1861,15 +2311,14 @@
1861	2311
1862	2312	/* first save CR2 and then disable interrupts */
1863	2313	cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1864		- cr2 \|= (UARTCR2_TE \| UARTCR2_RE);
	2314	+ cr2 \|= UARTCR2_TE \| UARTCR2_RE;
1865	2315	cr2 &= ~(UARTCR2_TIE \| UARTCR2_TCIE \| UARTCR2_RIE);
1866	2316	writeb(cr2, sport->port.membase + UARTCR2);
1867	2317
1868	2318	uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1869	2319
1870	2320	/* wait for transmitter finish complete and restore CR2 */
1871		- while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1872		- barrier();
	2321	+ lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1873	2322
1874	2323	writeb(old_cr2, sport->port.membase + UARTCR2);
1875	2324
..	..	@@ -1892,15 +2341,14 @@
1892	2341
1893	2342	/* first save CR2 and then disable interrupts */
1894	2343	cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
1895		- cr \|= (UARTCTRL_TE \| UARTCTRL_RE);
	2344	+ cr \|= UARTCTRL_TE \| UARTCTRL_RE;
1896	2345	cr &= ~(UARTCTRL_TIE \| UARTCTRL_TCIE \| UARTCTRL_RIE);
1897	2346	lpuart32_write(&sport->port, cr, UARTCTRL);
1898	2347
1899	2348	uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1900	2349
1901	2350	/* wait for transmitter finish complete and restore CR2 */
1902		- while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
1903		- barrier();
	2351	+ lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
1904	2352
1905	2353	lpuart32_write(&sport->port, old_cr, UARTCTRL);
1906	2354
..	..	@@ -1950,14 +2398,14 @@
1950	2398	brfa = readb(sport->port.membase + UARTCR4);
1951	2399	brfa &= UARTCR4_BRFA_MASK;
1952	2400
1953		- uartclk = clk_get_rate(sport->clk);
	2401	+ uartclk = lpuart_get_baud_clk_rate(sport);
1954	2402	/*
1955	2403	* baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1956	2404	*/
1957	2405	baud_raw = uartclk / (16 * (sbr + brfa / 32));
1958	2406
1959	2407	if (*baud != baud_raw)
1960		- printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
	2408	+ dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
1961	2409	"from %d to %d\n", baud_raw, *baud);
1962	2410	}
1963	2411
..	..	@@ -1996,14 +2444,14 @@
1996	2444	return;
1997	2445
1998	2446	sbr = bd;
1999		- uartclk = clk_get_rate(sport->clk);
	2447	+ uartclk = lpuart_get_baud_clk_rate(sport);
2000	2448	/*
2001	2449	* baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2002	2450	*/
2003	2451	baud_raw = uartclk / (16 * sbr);
2004	2452
2005	2453	if (*baud != baud_raw)
2006		- printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
	2454	+ dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2007	2455	"from %d to %d\n", baud_raw, *baud);
2008	2456	}
2009	2457
..	..	@@ -2094,8 +2542,34 @@
2094	2542	if (!device->port.membase)
2095	2543	return -ENODEV;
2096	2544
2097		- device->port.iotype = UPIO_MEM32BE;
	2545	+ if (device->port.iotype != UPIO_MEM32)
	2546	+ device->port.iotype = UPIO_MEM32BE;
	2547	+
2098	2548	device->con->write = lpuart32_early_write;
	2549	+ return 0;
	2550	+}
	2551	+
	2552	+static int __init ls1028a_early_console_setup(struct earlycon_device *device,
	2553	+ const char *opt)
	2554	+{
	2555	+ u32 cr;
	2556	+
	2557	+ if (!device->port.membase)
	2558	+ return -ENODEV;
	2559	+
	2560	+ device->port.iotype = UPIO_MEM32;
	2561	+ device->con->write = lpuart32_early_write;
	2562	+
	2563	+ /* set the baudrate */
	2564	+ if (device->port.uartclk && device->baud)
	2565	+ __lpuart32_serial_setbrg(&device->port, device->baud,
	2566	+ false, false);
	2567	+
	2568	+ /* enable transmitter */
	2569	+ cr = lpuart32_read(&device->port, UARTCTRL);
	2570	+ cr \|= UARTCTRL_TE;
	2571	+ lpuart32_write(&device->port, cr, UARTCTRL);
	2572	+
2099	2573	return 0;
2100	2574	}
2101	2575
..	..	@@ -2113,7 +2587,10 @@
2113	2587	}
2114	2588	OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2115	2589	OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
	2590	+OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2116	2591	OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
	2592	+OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup);
	2593	+OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2117	2594	EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2118	2595	EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2119	2596
..	..	@@ -2140,13 +2617,56 @@
2140	2617	struct device_node *np = pdev->dev.of_node;
2141	2618	struct lpuart_port *sport;
2142	2619	struct resource *res;
	2620	+ irq_handler_t handler;
2143	2621	int ret;
2144	2622
2145	2623	sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2146	2624	if (!sport)
2147	2625	return -ENOMEM;
2148	2626
2149		- pdev->dev.coherent_dma_mask = 0;
	2627	+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	2628	+ sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
	2629	+ if (IS_ERR(sport->port.membase))
	2630	+ return PTR_ERR(sport->port.membase);
	2631	+
	2632	+ sport->port.membase += sdata->reg_off;
	2633	+ sport->port.mapbase = res->start + sdata->reg_off;
	2634	+ sport->port.dev = &pdev->dev;
	2635	+ sport->port.type = PORT_LPUART;
	2636	+ sport->devtype = sdata->devtype;
	2637	+ ret = platform_get_irq(pdev, 0);
	2638	+ if (ret < 0)
	2639	+ return ret;
	2640	+ sport->port.irq = ret;
	2641	+ sport->port.iotype = sdata->iotype;
	2642	+ if (lpuart_is_32(sport))
	2643	+ sport->port.ops = &lpuart32_pops;
	2644	+ else
	2645	+ sport->port.ops = &lpuart_pops;
	2646	+ sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
	2647	+ sport->port.flags = UPF_BOOT_AUTOCONF;
	2648	+
	2649	+ if (lpuart_is_32(sport))
	2650	+ sport->port.rs485_config = lpuart32_config_rs485;
	2651	+ else
	2652	+ sport->port.rs485_config = lpuart_config_rs485;
	2653	+
	2654	+ sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	2655	+ if (IS_ERR(sport->ipg_clk)) {
	2656	+ ret = PTR_ERR(sport->ipg_clk);
	2657	+ dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
	2658	+ return ret;
	2659	+ }
	2660	+
	2661	+ sport->baud_clk = NULL;
	2662	+ if (is_imx8qxp_lpuart(sport)) {
	2663	+ sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
	2664	+ if (IS_ERR(sport->baud_clk)) {
	2665	+ ret = PTR_ERR(sport->baud_clk);
	2666	+ dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
	2667	+ return ret;
	2668	+ }
	2669	+ }
2150	2670
2151	2671	ret = of_alias_get_id(np, "serial");
2152	2672	if (ret < 0) {
..	..	@@ -2158,44 +2678,11 @@
2158	2678	return -EINVAL;
2159	2679	}
2160	2680	sport->port.line = ret;
2161		- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2162		- sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2163		- if (IS_ERR(sport->port.membase))
2164		- return PTR_ERR(sport->port.membase);
2165	2681
2166		- sport->port.membase += sdata->reg_off;
2167		- sport->port.mapbase = res->start + sdata->reg_off;
2168		- sport->port.dev = &pdev->dev;
2169		- sport->port.type = PORT_LPUART;
2170		- ret = platform_get_irq(pdev, 0);
2171		- if (ret < 0) {
2172		- dev_err(&pdev->dev, "cannot obtain irq\n");
	2682	+ ret = lpuart_enable_clks(sport);
	2683	+ if (ret)
2173	2684	return ret;
2174		- }
2175		- sport->port.irq = ret;
2176		- sport->port.iotype = sdata->iotype;
2177		- if (lpuart_is_32(sport))
2178		- sport->port.ops = &lpuart32_pops;
2179		- else
2180		- sport->port.ops = &lpuart_pops;
2181		- sport->port.flags = UPF_BOOT_AUTOCONF;
2182		-
2183		- sport->port.rs485_config = lpuart_config_rs485;
2184		-
2185		- sport->clk = devm_clk_get(&pdev->dev, "ipg");
2186		- if (IS_ERR(sport->clk)) {
2187		- ret = PTR_ERR(sport->clk);
2188		- dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
2189		- return ret;
2190		- }
2191		-
2192		- ret = clk_prepare_enable(sport->clk);
2193		- if (ret) {
2194		- dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
2195		- return ret;
2196		- }
2197		-
2198		- sport->port.uartclk = clk_get_rate(sport->clk);
	2685	+ sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2199	2686
2200	2687	lpuart_ports[sport->port.line] = sport;
2201	2688
..	..	@@ -2203,22 +2690,15 @@
2203	2690
2204	2691	if (lpuart_is_32(sport)) {
2205	2692	lpuart_reg.cons = LPUART32_CONSOLE;
2206		- ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0,
2207		- DRIVER_NAME, sport);
	2693	+ handler = lpuart32_int;
2208	2694	} else {
2209	2695	lpuart_reg.cons = LPUART_CONSOLE;
2210		- ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0,
2211		- DRIVER_NAME, sport);
	2696	+ handler = lpuart_int;
2212	2697	}
2213	2698
	2699	+ ret = uart_get_rs485_mode(&sport->port);
2214	2700	if (ret)
2215		- goto failed_irq_request;
2216		-
2217		- ret = uart_add_one_port(&lpuart_reg, &sport->port);
2218		- if (ret)
2219		- goto failed_attach_port;
2220		-
2221		- uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
	2701	+ goto failed_get_rs485;
2222	2702
2223	2703	if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2224	2704	dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
..	..	@@ -2227,23 +2707,22 @@
2227	2707	sport->port.rs485.delay_rts_after_send)
2228	2708	dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2229	2709
2230		- lpuart_config_rs485(&sport->port, &sport->port.rs485);
	2710	+ ret = uart_add_one_port(&lpuart_reg, &sport->port);
	2711	+ if (ret)
	2712	+ goto failed_attach_port;
2231	2713
2232		- sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
2233		- if (!sport->dma_tx_chan)
2234		- dev_info(sport->port.dev, "DMA tx channel request failed, "
2235		- "operating without tx DMA\n");
2236		-
2237		- sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
2238		- if (!sport->dma_rx_chan)
2239		- dev_info(sport->port.dev, "DMA rx channel request failed, "
2240		- "operating without rx DMA\n");
	2714	+ ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
	2715	+ DRIVER_NAME, sport);
	2716	+ if (ret)
	2717	+ goto failed_irq_request;
2241	2718
2242	2719	return 0;
2243	2720
2244		-failed_attach_port:
2245	2721	failed_irq_request:
2246		- clk_disable_unprepare(sport->clk);
	2722	+ uart_remove_one_port(&lpuart_reg, &sport->port);
	2723	+failed_get_rs485:
	2724	+failed_attach_port:
	2725	+ lpuart_disable_clks(sport);
2247	2726	return ret;
2248	2727	}
2249	2728
..	..	@@ -2253,7 +2732,7 @@
2253	2732
2254	2733	uart_remove_one_port(&lpuart_reg, &sport->port);
2255	2734
2256		- clk_disable_unprepare(sport->clk);
	2735	+ lpuart_disable_clks(sport);
2257	2736
2258	2737	if (sport->dma_tx_chan)
2259	2738	dma_release_channel(sport->dma_tx_chan);
..	..	@@ -2264,8 +2743,7 @@
2264	2743	return 0;
2265	2744	}
2266	2745
2267		-#ifdef CONFIG_PM_SLEEP
2268		-static int lpuart_suspend(struct device *dev)
	2746	+static int __maybe_unused lpuart_suspend(struct device *dev)
2269	2747	{
2270	2748	struct lpuart_port *sport = dev_get_drvdata(dev);
2271	2749	unsigned long temp;
..	..	@@ -2293,17 +2771,22 @@
2293	2771	* EDMA driver during suspend will forcefully release any
2294	2772	* non-idle DMA channels. If port wakeup is enabled or if port
2295	2773	* is console port or 'no_console_suspend' is set the Rx DMA
2296		- * cannot resume as as expected, hence gracefully release the
	2774	+ * cannot resume as expected, hence gracefully release the
2297	2775	* Rx DMA path before suspend and start Rx DMA path on resume.
2298	2776	*/
2299	2777	if (irq_wake) {
2300		- del_timer_sync(&sport->lpuart_timer);
2301	2778	lpuart_dma_rx_free(&sport->port);
2302	2779	}
2303	2780
2304	2781	/* Disable Rx DMA to use UART port as wakeup source */
2305		- writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS,
2306		- sport->port.membase + UARTCR5);
	2782	+ if (lpuart_is_32(sport)) {
	2783	+ temp = lpuart32_read(&sport->port, UARTBAUD);
	2784	+ lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
	2785	+ UARTBAUD);
	2786	+ } else {
	2787	+ writeb(readb(sport->port.membase + UARTCR5) &
	2788	+ ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
	2789	+ }
2307	2790	}
2308	2791
2309	2792	if (sport->lpuart_dma_tx_use) {
..	..	@@ -2312,32 +2795,23 @@
2312	2795	}
2313	2796
2314	2797	if (sport->port.suspended && !irq_wake)
2315		- clk_disable_unprepare(sport->clk);
	2798	+ lpuart_disable_clks(sport);
2316	2799
2317	2800	return 0;
2318	2801	}
2319	2802
2320		-static int lpuart_resume(struct device *dev)
	2803	+static int __maybe_unused lpuart_resume(struct device *dev)
2321	2804	{
2322	2805	struct lpuart_port *sport = dev_get_drvdata(dev);
2323	2806	bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2324		- unsigned long temp;
2325	2807
2326	2808	if (sport->port.suspended && !irq_wake)
2327		- clk_prepare_enable(sport->clk);
	2809	+ lpuart_enable_clks(sport);
2328	2810
2329		- if (lpuart_is_32(sport)) {
2330		- lpuart32_setup_watermark(sport);
2331		- temp = lpuart32_read(&sport->port, UARTCTRL);
2332		- temp \|= (UARTCTRL_RIE \| UARTCTRL_TIE \| UARTCTRL_RE \|
2333		- UARTCTRL_TE \| UARTCTRL_ILIE);
2334		- lpuart32_write(&sport->port, temp, UARTCTRL);
2335		- } else {
2336		- lpuart_setup_watermark(sport);
2337		- temp = readb(sport->port.membase + UARTCR2);
2338		- temp \|= (UARTCR2_RIE \| UARTCR2_TIE \| UARTCR2_RE \| UARTCR2_TE);
2339		- writeb(temp, sport->port.membase + UARTCR2);
2340		- }
	2811	+ if (lpuart_is_32(sport))
	2812	+ lpuart32_setup_watermark_enable(sport);
	2813	+ else
	2814	+ lpuart_setup_watermark_enable(sport);
2341	2815
2342	2816	if (sport->lpuart_dma_rx_use) {
2343	2817	if (irq_wake) {
..	..	@@ -2348,20 +2822,15 @@
2348	2822	}
2349	2823	}
2350	2824
2351		- if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
2352		- init_waitqueue_head(&sport->dma_wait);
2353		- sport->lpuart_dma_tx_use = true;
2354		- writeb(readb(sport->port.membase + UARTCR5) \|
2355		- UARTCR5_TDMAS, sport->port.membase + UARTCR5);
2356		- } else {
2357		- sport->lpuart_dma_tx_use = false;
2358		- }
	2825	+ lpuart_tx_dma_startup(sport);
	2826	+
	2827	+ if (lpuart_is_32(sport))
	2828	+ lpuart32_configure(sport);
2359	2829
2360	2830	uart_resume_port(&lpuart_reg, &sport->port);
2361	2831
2362	2832	return 0;
2363	2833	}
2364		-#endif
2365	2834
2366	2835	static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2367	2836