forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/drivers/tty/serial/fsl_lpuart.c
....@@ -809,11 +809,17 @@
809809 			struct lpuart_port, port);
810810 	unsigned long stat = lpuart32_read(port, UARTSTAT);
811811 	unsigned long sfifo = lpuart32_read(port, UARTFIFO);
812
+	unsigned long ctrl = lpuart32_read(port, UARTCTRL);
812813 
813814 	if (sport->dma_tx_in_progress)
814815 		return 0;
815816 
816
-	if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT)
817
+	/*
818
+	 * LPUART Transmission Complete Flag may never be set while queuing a break
819
+	 * character, so avoid checking for transmission complete when UARTCTRL_SBK
820
+	 * is asserted.
821
+	 */
822
+	if ((stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) || ctrl & UARTCTRL_SBK)
817823 		return TIOCSER_TEMT;
818824 
819825 	return 0;
....@@ -1056,8 +1062,8 @@
10561062 		unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
10571063 
10581064 		if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1059
-			/* Read DR to clear the error flags */
1060
-			lpuart32_read(&sport->port, UARTDATA);
1065
+			/* Clear the error flags */
1066
+			lpuart32_write(&sport->port, sr, UARTSTAT);
10611067 
10621068 			if (sr & UARTSTAT_PE)
10631069 				sport->port.icount.parity++;
....@@ -1214,7 +1220,7 @@
12141220 	 * 10ms at any baud rate.
12151221 	 */
12161222 	sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud /  bits / 1000) * 2;
1217
-	sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
1223
+	sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len));
12181224 	if (sport->rx_dma_rng_buf_len < 16)
12191225 		sport->rx_dma_rng_buf_len = 16;
12201226 
....@@ -1278,6 +1284,7 @@
12781284 	struct dma_chan *chan = sport->dma_rx_chan;
12791285 
12801286 	dmaengine_terminate_all(chan);
1287
+	del_timer_sync(&sport->lpuart_timer);
12811288 	dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
12821289 	kfree(sport->rx_ring.buf);
12831290 	sport->rx_ring.tail = 0;
....@@ -1450,12 +1457,34 @@
14501457 {
14511458 	unsigned long temp;
14521459 
1453
-	temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1460
+	temp = lpuart32_read(port, UARTCTRL);
14541461 
1455
-	if (break_state != 0)
1456
-		temp |= UARTCTRL_SBK;
1457
-
1458
-	lpuart32_write(port, temp, UARTCTRL);
1462
+	/*
1463
+	 * LPUART IP now has two known bugs, one is CTS has higher priority than the
1464
+	 * break signal, which causes the break signal sending through UARTCTRL_SBK
1465
+	 * may impacted by the CTS input if the HW flow control is enabled. It
1466
+	 * exists on all platforms we support in this driver.
1467
+	 * Another bug is i.MX8QM LPUART may have an additional break character
1468
+	 * being sent after SBK was cleared.
1469
+	 * To avoid above two bugs, we use Transmit Data Inversion function to send
1470
+	 * the break signal instead of UARTCTRL_SBK.
1471
+	 */
1472
+	if (break_state != 0) {
1473
+		/*
1474
+		 * Disable the transmitter to prevent any data from being sent out
1475
+		 * during break, then invert the TX line to send break.
1476
+		 */
1477
+		temp &= ~UARTCTRL_TE;
1478
+		lpuart32_write(port, temp, UARTCTRL);
1479
+		temp |= UARTCTRL_TXINV;
1480
+		lpuart32_write(port, temp, UARTCTRL);
1481
+	} else {
1482
+		/* Disable the TXINV to turn off break and re-enable transmitter. */
1483
+		temp &= ~UARTCTRL_TXINV;
1484
+		lpuart32_write(port, temp, UARTCTRL);
1485
+		temp |= UARTCTRL_TE;
1486
+		lpuart32_write(port, temp, UARTCTRL);
1487
+	}
14591488 }
14601489 
14611490 static void lpuart_setup_watermark(struct lpuart_port *sport)
....@@ -1723,7 +1752,6 @@
17231752 static void lpuart_dma_shutdown(struct lpuart_port *sport)
17241753 {
17251754 	if (sport->lpuart_dma_rx_use) {
1726
-		del_timer_sync(&sport->lpuart_timer);
17271755 		lpuart_dma_rx_free(&sport->port);
17281756 		sport->lpuart_dma_rx_use = false;
17291757 	}
....@@ -1874,10 +1902,8 @@
18741902 	 * Since timer function acqures sport->port.lock, need to stop before
18751903 	 * acquring same lock because otherwise del_timer_sync() can deadlock.
18761904 	 */
1877
-	if (old && sport->lpuart_dma_rx_use) {
1878
-		del_timer_sync(&sport->lpuart_timer);
1905
+	if (old && sport->lpuart_dma_rx_use)
18791906 		lpuart_dma_rx_free(&sport->port);
1880
-	}
18811907 
18821908 	spin_lock_irqsave(&sport->port.lock, flags);
18831909 
....@@ -2109,10 +2135,8 @@
21092135 	 * Since timer function acqures sport->port.lock, need to stop before
21102136 	 * acquring same lock because otherwise del_timer_sync() can deadlock.
21112137 	 */
2112
-	if (old && sport->lpuart_dma_rx_use) {
2113
-		del_timer_sync(&sport->lpuart_timer);
2138
+	if (old && sport->lpuart_dma_rx_use)
21142139 		lpuart_dma_rx_free(&sport->port);
2115
-	}
21162140 
21172141 	spin_lock_irqsave(&sport->port.lock, flags);
21182142 
....@@ -2139,9 +2163,15 @@
21392163 	/* update the per-port timeout */
21402164 	uart_update_timeout(port, termios->c_cflag, baud);
21412165 
2142
-	/* wait transmit engin complete */
2143
-	lpuart32_write(&sport->port, 0, UARTMODIR);
2144
-	lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2166
+	/*
2167
+	 * LPUART Transmission Complete Flag may never be set while queuing a break
2168
+	 * character, so skip waiting for transmission complete when UARTCTRL_SBK is
2169
+	 * asserted.
2170
+	 */
2171
+	if (!(old_ctrl & UARTCTRL_SBK)) {
2172
+		lpuart32_write(&sport->port, 0, UARTMODIR);
2173
+		lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2174
+	}
21452175 
21462176 	/* disable transmit and receive */
21472177 	lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
....@@ -2559,6 +2589,7 @@
25592589 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
25602590 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
25612591 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2592
+OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup);
25622593 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
25632594 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
25642595 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
....@@ -2586,6 +2617,7 @@
25862617 	struct device_node *np = pdev->dev.of_node;
25872618 	struct lpuart_port *sport;
25882619 	struct resource *res;
2620
+	irq_handler_t handler;
25892621 	int ret;
25902622 
25912623 	sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
....@@ -2658,16 +2690,11 @@
26582690 
26592691 	if (lpuart_is_32(sport)) {
26602692 		lpuart_reg.cons = LPUART32_CONSOLE;
2661
-		ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0,
2662
-					DRIVER_NAME, sport);
2693
+		handler = lpuart32_int;
26632694 	} else {
26642695 		lpuart_reg.cons = LPUART_CONSOLE;
2665
-		ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0,
2666
-					DRIVER_NAME, sport);
2696
+		handler = lpuart_int;
26672697 	}
2668
-
2669
-	if (ret)
2670
-		goto failed_irq_request;
26712698 
26722699 	ret = uart_get_rs485_mode(&sport->port);
26732700 	if (ret)
....@@ -2684,11 +2711,17 @@
26842711 	if (ret)
26852712 		goto failed_attach_port;
26862713 
2714
+	ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
2715
+				DRIVER_NAME, sport);
2716
+	if (ret)
2717
+		goto failed_irq_request;
2718
+
26872719 	return 0;
26882720 
2721
+failed_irq_request:
2722
+	uart_remove_one_port(&lpuart_reg, &sport->port);
26892723 failed_get_rs485:
26902724 failed_attach_port:
2691
-failed_irq_request:
26922725 	lpuart_disable_clks(sport);
26932726 	return ret;
26942727 }
....@@ -2738,11 +2771,10 @@
27382771 		 * EDMA driver during suspend will forcefully release any
27392772 		 * non-idle DMA channels. If port wakeup is enabled or if port
27402773 		 * is console port or 'no_console_suspend' is set the Rx DMA
2741
-		 * cannot resume as as expected, hence gracefully release the
2774
+		 * cannot resume as expected, hence gracefully release the
27422775 		 * Rx DMA path before suspend and start Rx DMA path on resume.
27432776 		 */
27442777 		if (irq_wake) {
2745
-			del_timer_sync(&sport->lpuart_timer);
27462778 			lpuart_dma_rx_free(&sport->port);
27472779 		}
27482780