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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/drivers/spi/spi-mt65xx.c
....@@ -1,15 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2015 MediaTek Inc.
34  * Author: Leilk Liu <leilk.liu@mediatek.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License version 2 as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful,
10
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
- * GNU General Public License for more details.
135  */
146 
157 #include <linux/clk.h>
....@@ -25,6 +17,7 @@
2517 #include <linux/platform_data/spi-mt65xx.h>
2618 #include <linux/pm_runtime.h>
2719 #include <linux/spi/spi.h>
20
+#include <linux/dma-mapping.h>
2821 
2922 #define SPI_CFG0_REG                      0x0000
3023 #define SPI_CFG1_REG                      0x0004
....@@ -36,6 +29,8 @@
3629 #define SPI_STATUS0_REG                   0x001c
3730 #define SPI_PAD_SEL_REG                   0x0024
3831 #define SPI_CFG2_REG                      0x0028
32
+#define SPI_TX_SRC_REG_64                 0x002c
33
+#define SPI_RX_DST_REG_64                 0x0030
3934 
4035 #define SPI_CFG0_SCK_HIGH_OFFSET          0
4136 #define SPI_CFG0_SCK_LOW_OFFSET           8
....@@ -82,6 +77,10 @@
8277 
8378 #define MTK_SPI_MAX_FIFO_SIZE 32U
8479 #define MTK_SPI_PACKET_SIZE 1024
80
+#define MTK_SPI_32BITS_MASK  (0xffffffff)
81
+
82
+#define DMA_ADDR_EXT_BITS (36)
83
+#define DMA_ADDR_DEF_BITS (32)
8584 
8685 struct mtk_spi_compatible {
8786 	bool need_pad_sel;
....@@ -89,6 +88,8 @@
8988 	bool must_tx;
9089 	/* some IC design adjust cfg register to enhance time accuracy */
9190 	bool enhance_timing;
91
+	/* some IC support DMA addr extension */
92
+	bool dma_ext;
9293 };
9394 
9495 struct mtk_spi {
....@@ -111,6 +112,13 @@
111112 	.must_tx = true,
112113 };
113114 
115
+static const struct mtk_spi_compatible mt6765_compat = {
116
+	.need_pad_sel = true,
117
+	.must_tx = true,
118
+	.enhance_timing = true,
119
+	.dma_ext = true,
120
+};
121
+
114122 static const struct mtk_spi_compatible mt7622_compat = {
115123 	.must_tx = true,
116124 	.enhance_timing = true,
....@@ -121,14 +129,17 @@
121129 	.must_tx = true,
122130 };
123131 
132
+static const struct mtk_spi_compatible mt8183_compat = {
133
+	.need_pad_sel = true,
134
+	.must_tx = true,
135
+	.enhance_timing = true,
136
+};
137
+
124138 /*
125139  * A piece of default chip info unless the platform
126140  * supplies it.
127141  */
128142 static const struct mtk_chip_config mtk_default_chip_info = {
129
-	.rx_mlsb = 1,
130
-	.tx_mlsb = 1,
131
-	.cs_pol = 0,
132143 	.sample_sel = 0,
133144 };
134145 
....@@ -142,7 +153,13 @@
142153 	{ .compatible = "mediatek,mt6589-spi",
143154 		.data = (void *)&mtk_common_compat,
144155 	},
156
+	{ .compatible = "mediatek,mt6765-spi",
157
+		.data = (void *)&mt6765_compat,
158
+	},
145159 	{ .compatible = "mediatek,mt7622-spi",
160
+		.data = (void *)&mt7622_compat,
161
+	},
162
+	{ .compatible = "mediatek,mt7629-spi",
146163 		.data = (void *)&mt7622_compat,
147164 	},
148165 	{ .compatible = "mediatek,mt8135-spi",
....@@ -150,6 +167,12 @@
150167 	},
151168 	{ .compatible = "mediatek,mt8173-spi",
152169 		.data = (void *)&mt8173_compat,
170
+	},
171
+	{ .compatible = "mediatek,mt8183-spi",
172
+		.data = (void *)&mt8183_compat,
173
+	},
174
+	{ .compatible = "mediatek,mt8192-spi",
175
+		.data = (void *)&mt6765_compat,
153176 	},
154177 	{}
155178 };
....@@ -192,14 +215,13 @@
192215 		reg_val &= ~SPI_CMD_CPOL;
193216 
194217 	/* set the mlsbx and mlsbtx */
195
-	if (chip_config->tx_mlsb)
196
-		reg_val |= SPI_CMD_TXMSBF;
197
-	else
218
+	if (spi->mode & SPI_LSB_FIRST) {
198219 		reg_val &= ~SPI_CMD_TXMSBF;
199
-	if (chip_config->rx_mlsb)
200
-		reg_val |= SPI_CMD_RXMSBF;
201
-	else
202220 		reg_val &= ~SPI_CMD_RXMSBF;
221
+	} else {
222
+		reg_val |= SPI_CMD_TXMSBF;
223
+		reg_val |= SPI_CMD_RXMSBF;
224
+	}
203225 
204226 	/* set the tx/rx endian */
205227 #ifdef __LITTLE_ENDIAN
....@@ -211,10 +233,12 @@
211233 #endif
212234 
213235 	if (mdata->dev_comp->enhance_timing) {
214
-		if (chip_config->cs_pol)
236
+		/* set CS polarity */
237
+		if (spi->mode & SPI_CS_HIGH)
215238 			reg_val |= SPI_CMD_CS_POL;
216239 		else
217240 			reg_val &= ~SPI_CMD_CS_POL;
241
+
218242 		if (chip_config->sample_sel)
219243 			reg_val |= SPI_CMD_SAMPLE_SEL;
220244 		else
....@@ -244,6 +268,9 @@
244268 {
245269 	u32 reg_val;
246270 	struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
271
+
272
+	if (spi->mode & SPI_CS_HIGH)
273
+		enable = !enable;
247274 
248275 	reg_val = readl(mdata->base + SPI_CMD_REG);
249276 	if (!enable) {
....@@ -371,10 +398,25 @@
371398 {
372399 	struct mtk_spi *mdata = spi_master_get_devdata(master);
373400 
374
-	if (mdata->tx_sgl)
375
-		writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG);
376
-	if (mdata->rx_sgl)
377
-		writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG);
401
+	if (mdata->tx_sgl) {
402
+		writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
403
+		       mdata->base + SPI_TX_SRC_REG);
404
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
405
+		if (mdata->dev_comp->dma_ext)
406
+			writel((u32)(xfer->tx_dma >> 32),
407
+			       mdata->base + SPI_TX_SRC_REG_64);
408
+#endif
409
+	}
410
+
411
+	if (mdata->rx_sgl) {
412
+		writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
413
+		       mdata->base + SPI_RX_DST_REG);
414
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
415
+		if (mdata->dev_comp->dma_ext)
416
+			writel((u32)(xfer->rx_dma >> 32),
417
+			       mdata->base + SPI_RX_DST_REG_64);
418
+#endif
419
+	}
378420 }
379421 
380422 static int mtk_spi_fifo_transfer(struct spi_master *master,
....@@ -586,8 +628,7 @@
586628 	struct spi_master *master;
587629 	struct mtk_spi *mdata;
588630 	const struct of_device_id *of_id;
589
-	struct resource *res;
590
-	int i, irq, ret;
631
+	int i, irq, ret, addr_bits;
591632 
592633 	master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
593634 	if (!master) {
....@@ -597,7 +638,7 @@
597638 
598639 	master->auto_runtime_pm = true;
599640 	master->dev.of_node = pdev->dev.of_node;
600
-	master->mode_bits = SPI_CPOL | SPI_CPHA;
641
+	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
601642 
602643 	master->set_cs = mtk_spi_set_cs;
603644 	master->prepare_message = mtk_spi_prepare_message;
....@@ -614,6 +655,10 @@
614655 
615656 	mdata = spi_master_get_devdata(master);
616657 	mdata->dev_comp = of_id->data;
658
+
659
+	if (mdata->dev_comp->enhance_timing)
660
+		master->mode_bits |= SPI_CS_HIGH;
661
+
617662 	if (mdata->dev_comp->must_tx)
618663 		master->flags = SPI_MASTER_MUST_TX;
619664 
....@@ -649,15 +694,7 @@
649694 	}
650695 
651696 	platform_set_drvdata(pdev, master);
652
-
653
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
654
-	if (!res) {
655
-		ret = -ENODEV;
656
-		dev_err(&pdev->dev, "failed to determine base address\n");
657
-		goto err_put_master;
658
-	}
659
-
660
-	mdata->base = devm_ioremap_resource(&pdev->dev, res);
697
+	mdata->base = devm_platform_ioremap_resource(pdev, 0);
661698 	if (IS_ERR(mdata->base)) {
662699 		ret = PTR_ERR(mdata->base);
663700 		goto err_put_master;
....@@ -665,7 +702,6 @@
665702 
666703 	irq = platform_get_irq(pdev, 0);
667704 	if (irq < 0) {
668
-		dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
669705 		ret = irq;
670706 		goto err_put_master;
671707 	}
....@@ -754,6 +790,15 @@
754790 		}
755791 	}
756792 
793
+	if (mdata->dev_comp->dma_ext)
794
+		addr_bits = DMA_ADDR_EXT_BITS;
795
+	else
796
+		addr_bits = DMA_ADDR_DEF_BITS;
797
+	ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits));
798
+	if (ret)
799
+		dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
800
+			   addr_bits, ret);
801
+
757802 	return 0;
758803 
759804 err_disable_runtime_pm: