| .. | .. |
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| 244 | 244 | if (output) |
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| 245 | 245 | return gpiod_direction_output(spi_gpio->mosi, 1); |
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| 246 | 246 | |
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| 247 | | - ret = gpiod_direction_input(spi_gpio->mosi); |
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| 248 | | - if (ret) |
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| 249 | | - return ret; |
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| 247 | + /* |
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| 248 | + * Only change MOSI to an input if using 3WIRE mode. |
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| 249 | + * Otherwise, MOSI could be left floating if there is |
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| 250 | + * no pull resistor connected to the I/O pin, or could |
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| 251 | + * be left logic high if there is a pull-up. Transmitting |
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| 252 | + * logic high when only clocking MISO data in can put some |
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| 253 | + * SPI devices in to a bad state. |
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| 254 | + */ |
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| 255 | + if (spi->mode & SPI_3WIRE) { |
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| 256 | + ret = gpiod_direction_input(spi_gpio->mosi); |
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| 257 | + if (ret) |
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| 258 | + return ret; |
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| 259 | + } |
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| 250 | 260 | /* |
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| 251 | 261 | * Send a turnaround high impedance cycle when switching |
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| 252 | 262 | * from output to input. Theoretically there should be |
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