~hc/RK356X_SDK_RELEASE.git

..	..	@@ -3,10 +3,13 @@
3	3	// Freescale i.MX7ULP LPSPI driver
4	4	//
5	5	// Copyright 2016 Freescale Semiconductor, Inc.
	6	+// Copyright 2018 NXP Semiconductors
6	7
7	8	#include <linux/clk.h>
8	9	#include <linux/completion.h>
9	10	#include <linux/delay.h>
	11	+#include <linux/dmaengine.h>
	12	+#include <linux/dma-mapping.h>
10	13	#include <linux/err.h>
11	14	#include <linux/interrupt.h>
12	15	#include <linux/io.h>
..	..	@@ -15,13 +18,21 @@
15	18	#include <linux/module.h>
16	19	#include <linux/of.h>
17	20	#include <linux/of_device.h>
	21	+#include <linux/pinctrl/consumer.h>
18	22	#include <linux/platform_device.h>
	23	+#include <linux/platform_data/dma-imx.h>
	24	+#include <linux/pm_runtime.h>
19	25	#include <linux/slab.h>
20	26	#include <linux/spi/spi.h>
21	27	#include <linux/spi/spi_bitbang.h>
22	28	#include <linux/types.h>
23	29
24	30	#define DRIVER_NAME "fsl_lpspi"
	31	+
	32	+#define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
	33	+
	34	+/* The maximum bytes that edma can transfer once.*/
	35	+#define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
25	36
26	37	/* i.MX7ULP LPSPI registers */
27	38	#define IMX7ULP_VERID 0x0
..	..	@@ -47,16 +58,23 @@
47	58	#define CR_RTF BIT(8)
48	59	#define CR_RST BIT(1)
49	60	#define CR_MEN BIT(0)
	61	+#define SR_MBF BIT(24)
50	62	#define SR_TCF BIT(10)
	63	+#define SR_FCF BIT(9)
51	64	#define SR_RDF BIT(1)
52	65	#define SR_TDF BIT(0)
53	66	#define IER_TCIE BIT(10)
	67	+#define IER_FCIE BIT(9)
54	68	#define IER_RDIE BIT(1)
55	69	#define IER_TDIE BIT(0)
	70	+#define DER_RDDE BIT(1)
	71	+#define DER_TDDE BIT(0)
56	72	#define CFGR1_PCSCFG BIT(27)
	73	+#define CFGR1_PINCFG (BIT(24)\|BIT(25))
57	74	#define CFGR1_PCSPOL BIT(8)
58	75	#define CFGR1_NOSTALL BIT(3)
59	76	#define CFGR1_MASTER BIT(0)
	77	+#define FSR_TXCOUNT (0xFF)
60	78	#define RSR_RXEMPTY BIT(1)
61	79	#define TCR_CPOL BIT(31)
62	80	#define TCR_CPHA BIT(30)
..	..	@@ -64,8 +82,6 @@
64	82	#define TCR_CONTC BIT(20)
65	83	#define TCR_RXMSK BIT(19)
66	84	#define TCR_TXMSK BIT(18)
67		-
68		-static int clkdivs[] = {1, 2, 4, 8, 16, 32, 64, 128};
69	85
70	86	struct lpspi_config {
71	87	u8 bpw;
..	..	@@ -78,7 +94,12 @@
78	94	struct fsl_lpspi_data {
79	95	struct device *dev;
80	96	void __iomem *base;
81		- struct clk *clk;
	97	+ unsigned long base_phys;
	98	+ struct clk *clk_ipg;
	99	+ struct clk *clk_per;
	100	+ bool is_slave;
	101	+ bool is_only_cs1;
	102	+ bool is_first_byte;
82	103
83	104	void *rx_buf;
84	105	const void *tx_buf;
..	..	@@ -86,11 +107,19 @@
86	107	void (rx)(struct fsl_lpspi_data );
87	108
88	109	u32 remain;
	110	+ u8 watermark;
89	111	u8 txfifosize;
90	112	u8 rxfifosize;
91	113
92	114	struct lpspi_config config;
93	115	struct completion xfer_done;
	116	+
	117	+ bool slave_aborted;
	118	+
	119	+ /* DMA */
	120	+ bool usedma;
	121	+ struct completion dma_rx_completion;
	122	+ struct completion dma_tx_completion;
94	123	};
95	124
96	125	static const struct of_device_id fsl_lpspi_dt_ids[] = {
..	..	@@ -137,37 +166,56 @@
137	166	writel(enable, fsl_lpspi->base + IMX7ULP_IER);
138	167	}
139	168
140		-static int lpspi_prepare_xfer_hardware(struct spi_master *master)
	169	+static int fsl_lpspi_bytes_per_word(const int bpw)
141	170	{
142		- struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master);
143		-
144		- return clk_prepare_enable(fsl_lpspi->clk);
	171	+ return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
145	172	}
146	173
147		-static int lpspi_unprepare_xfer_hardware(struct spi_master *master)
	174	+static bool fsl_lpspi_can_dma(struct spi_controller *controller,
	175	+ struct spi_device *spi,
	176	+ struct spi_transfer *transfer)
148	177	{
149		- struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master);
	178	+ unsigned int bytes_per_word;
150	179
151		- clk_disable_unprepare(fsl_lpspi->clk);
	180	+ if (!controller->dma_rx)
	181	+ return false;
	182	+
	183	+ bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
	184	+
	185	+ switch (bytes_per_word) {
	186	+ case 1:
	187	+ case 2:
	188	+ case 4:
	189	+ break;
	190	+ default:
	191	+ return false;
	192	+ }
	193	+
	194	+ return true;
	195	+}
	196	+
	197	+static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
	198	+{
	199	+ struct fsl_lpspi_data *fsl_lpspi =
	200	+ spi_controller_get_devdata(controller);
	201	+ int ret;
	202	+
	203	+ ret = pm_runtime_resume_and_get(fsl_lpspi->dev);
	204	+ if (ret < 0) {
	205	+ dev_err(fsl_lpspi->dev, "failed to enable clock\n");
	206	+ return ret;
	207	+ }
152	208
153	209	return 0;
154	210	}
155	211
156		-static int fsl_lpspi_txfifo_empty(struct fsl_lpspi_data *fsl_lpspi)
	212	+static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
157	213	{
158		- u32 txcnt;
159		- unsigned long orig_jiffies = jiffies;
	214	+ struct fsl_lpspi_data *fsl_lpspi =
	215	+ spi_controller_get_devdata(controller);
160	216
161		- do {
162		- txcnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
163		-
164		- if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
165		- dev_dbg(fsl_lpspi->dev, "txfifo empty timeout\n");
166		- return -ETIMEDOUT;
167		- }
168		- cond_resched();
169		-
170		- } while (txcnt);
	217	+ pm_runtime_mark_last_busy(fsl_lpspi->dev);
	218	+ pm_runtime_put_autosuspend(fsl_lpspi->dev);
171	219
172	220	return 0;
173	221	}
..	..	@@ -175,6 +223,7 @@
175	223	static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
176	224	{
177	225	u8 txfifo_cnt;
	226	+ u32 temp;
178	227
179	228	txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
180	229
..	..	@@ -185,9 +234,15 @@
185	234	txfifo_cnt++;
186	235	}
187	236
188		- if (!fsl_lpspi->remain && (txfifo_cnt < fsl_lpspi->txfifosize))
189		- writel(0, fsl_lpspi->base + IMX7ULP_TDR);
190		- else
	237	+ if (txfifo_cnt < fsl_lpspi->txfifosize) {
	238	+ if (!fsl_lpspi->is_slave) {
	239	+ temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
	240	+ temp &= ~TCR_CONTC;
	241	+ writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
	242	+ }
	243	+
	244	+ fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
	245	+ } else
191	246	fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
192	247	}
193	248
..	..	@@ -197,27 +252,28 @@
197	252	fsl_lpspi->rx(fsl_lpspi);
198	253	}
199	254
200		-static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi,
201		- bool is_first_xfer)
	255	+static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
202	256	{
203	257	u32 temp = 0;
204	258
205	259	temp \|= fsl_lpspi->config.bpw - 1;
206		- temp \|= fsl_lpspi->config.prescale << 27;
207	260	temp \|= (fsl_lpspi->config.mode & 0x3) << 30;
208	261	temp \|= (fsl_lpspi->config.chip_select & 0x3) << 24;
209		-
210		- /*
211		- * Set TCR_CONT will keep SS asserted after current transfer.
212		- * For the first transfer, clear TCR_CONTC to assert SS.
213		- * For subsequent transfer, set TCR_CONTC to keep SS asserted.
214		- */
215		- temp \|= TCR_CONT;
216		- if (is_first_xfer)
217		- temp &= ~TCR_CONTC;
218		- else
219		- temp \|= TCR_CONTC;
220		-
	262	+ if (!fsl_lpspi->is_slave) {
	263	+ temp \|= fsl_lpspi->config.prescale << 27;
	264	+ /*
	265	+ * Set TCR_CONT will keep SS asserted after current transfer.
	266	+ * For the first transfer, clear TCR_CONTC to assert SS.
	267	+ * For subsequent transfer, set TCR_CONTC to keep SS asserted.
	268	+ */
	269	+ if (!fsl_lpspi->usedma) {
	270	+ temp \|= TCR_CONT;
	271	+ if (fsl_lpspi->is_first_byte)
	272	+ temp &= ~TCR_CONTC;
	273	+ else
	274	+ temp \|= TCR_CONTC;
	275	+ }
	276	+ }
221	277	writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
222	278
223	279	dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
..	..	@@ -227,7 +283,11 @@
227	283	{
228	284	u32 temp;
229	285
230		- temp = fsl_lpspi->txfifosize >> 1 \| (fsl_lpspi->rxfifosize >> 1) << 16;
	286	+ if (!fsl_lpspi->usedma)
	287	+ temp = fsl_lpspi->watermark >> 1 \|
	288	+ (fsl_lpspi->watermark >> 1) << 16;
	289	+ else
	290	+ temp = fsl_lpspi->watermark >> 1;
231	291
232	292	writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
233	293
..	..	@@ -240,23 +300,77 @@
240	300	unsigned int perclk_rate, scldiv;
241	301	u8 prescale;
242	302
243		- perclk_rate = clk_get_rate(fsl_lpspi->clk);
	303	+ perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
	304	+
	305	+ if (config.speed_hz > perclk_rate / 2) {
	306	+ dev_err(fsl_lpspi->dev,
	307	+ "per-clk should be at least two times of transfer speed");
	308	+ return -EINVAL;
	309	+ }
	310	+
244	311	for (prescale = 0; prescale < 8; prescale++) {
245		- scldiv = perclk_rate /
246		- (clkdivs[prescale] * config.speed_hz) - 2;
	312	+ scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2;
247	313	if (scldiv < 256) {
248	314	fsl_lpspi->config.prescale = prescale;
249	315	break;
250	316	}
251	317	}
252	318
253		- if (prescale == 8 && scldiv >= 256)
	319	+ if (scldiv >= 256)
254	320	return -EINVAL;
255	321
256		- writel(scldiv, fsl_lpspi->base + IMX7ULP_CCR);
	322	+ writel(scldiv \| (scldiv << 8) \| ((scldiv >> 1) << 16),
	323	+ fsl_lpspi->base + IMX7ULP_CCR);
257	324
258		- dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale =%d, scldiv=%d\n",
	325	+ dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n",
259	326	perclk_rate, config.speed_hz, prescale, scldiv);
	327	+
	328	+ return 0;
	329	+}
	330	+
	331	+static int fsl_lpspi_dma_configure(struct spi_controller *controller)
	332	+{
	333	+ int ret;
	334	+ enum dma_slave_buswidth buswidth;
	335	+ struct dma_slave_config rx = {}, tx = {};
	336	+ struct fsl_lpspi_data *fsl_lpspi =
	337	+ spi_controller_get_devdata(controller);
	338	+
	339	+ switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
	340	+ case 4:
	341	+ buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
	342	+ break;
	343	+ case 2:
	344	+ buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
	345	+ break;
	346	+ case 1:
	347	+ buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
	348	+ break;
	349	+ default:
	350	+ return -EINVAL;
	351	+ }
	352	+
	353	+ tx.direction = DMA_MEM_TO_DEV;
	354	+ tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
	355	+ tx.dst_addr_width = buswidth;
	356	+ tx.dst_maxburst = 1;
	357	+ ret = dmaengine_slave_config(controller->dma_tx, &tx);
	358	+ if (ret) {
	359	+ dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
	360	+ ret);
	361	+ return ret;
	362	+ }
	363	+
	364	+ rx.direction = DMA_DEV_TO_MEM;
	365	+ rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
	366	+ rx.src_addr_width = buswidth;
	367	+ rx.src_maxburst = 1;
	368	+ ret = dmaengine_slave_config(controller->dma_rx, &rx);
	369	+ if (ret) {
	370	+ dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
	371	+ ret);
	372	+ return ret;
	373	+ }
260	374
261	375	return 0;
262	376	}
..	..	@@ -266,17 +380,18 @@
266	380	u32 temp;
267	381	int ret;
268	382
269		- temp = CR_RST;
270		- writel(temp, fsl_lpspi->base + IMX7ULP_CR);
271		- writel(0, fsl_lpspi->base + IMX7ULP_CR);
272		-
273		- ret = fsl_lpspi_set_bitrate(fsl_lpspi);
274		- if (ret)
275		- return ret;
	383	+ if (!fsl_lpspi->is_slave) {
	384	+ ret = fsl_lpspi_set_bitrate(fsl_lpspi);
	385	+ if (ret)
	386	+ return ret;
	387	+ }
276	388
277	389	fsl_lpspi_set_watermark(fsl_lpspi);
278	390
279		- temp = CFGR1_PCSCFG \| CFGR1_MASTER;
	391	+ if (!fsl_lpspi->is_slave)
	392	+ temp = CFGR1_MASTER;
	393	+ else
	394	+ temp = CFGR1_PINCFG;
280	395	if (fsl_lpspi->config.mode & SPI_CS_HIGH)
281	396	temp \|= CFGR1_PCSPOL;
282	397	writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
..	..	@@ -285,18 +400,31 @@
285	400	temp \|= CR_RRF \| CR_RTF \| CR_MEN;
286	401	writel(temp, fsl_lpspi->base + IMX7ULP_CR);
287	402
	403	+ temp = 0;
	404	+ if (fsl_lpspi->usedma)
	405	+ temp = DER_TDDE \| DER_RDDE;
	406	+ writel(temp, fsl_lpspi->base + IMX7ULP_DER);
	407	+
288	408	return 0;
289	409	}
290	410
291		-static void fsl_lpspi_setup_transfer(struct spi_device *spi,
	411	+static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
	412	+ struct spi_device *spi,
292	413	struct spi_transfer *t)
293	414	{
294		- struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(spi->master);
	415	+ struct fsl_lpspi_data *fsl_lpspi =
	416	+ spi_controller_get_devdata(spi->controller);
	417	+
	418	+ if (t == NULL)
	419	+ return -EINVAL;
295	420
296	421	fsl_lpspi->config.mode = spi->mode;
297		- fsl_lpspi->config.bpw = t ? t->bits_per_word : spi->bits_per_word;
298		- fsl_lpspi->config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
299		- fsl_lpspi->config.chip_select = spi->chip_select;
	422	+ fsl_lpspi->config.bpw = t->bits_per_word;
	423	+ fsl_lpspi->config.speed_hz = t->speed_hz;
	424	+ if (fsl_lpspi->is_only_cs1)
	425	+ fsl_lpspi->config.chip_select = 1;
	426	+ else
	427	+ fsl_lpspi->config.chip_select = spi->chip_select;
300	428
301	429	if (!fsl_lpspi->config.speed_hz)
302	430	fsl_lpspi->config.speed_hz = spi->max_speed_hz;
..	..	@@ -315,14 +443,251 @@
315	443	fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
316	444	}
317	445
318		- fsl_lpspi_config(fsl_lpspi);
	446	+ if (t->len <= fsl_lpspi->txfifosize)
	447	+ fsl_lpspi->watermark = t->len;
	448	+ else
	449	+ fsl_lpspi->watermark = fsl_lpspi->txfifosize;
	450	+
	451	+ if (fsl_lpspi_can_dma(controller, spi, t))
	452	+ fsl_lpspi->usedma = true;
	453	+ else
	454	+ fsl_lpspi->usedma = false;
	455	+
	456	+ return fsl_lpspi_config(fsl_lpspi);
319	457	}
320	458
321		-static int fsl_lpspi_transfer_one(struct spi_master *master,
322		- struct spi_device *spi,
	459	+static int fsl_lpspi_slave_abort(struct spi_controller *controller)
	460	+{
	461	+ struct fsl_lpspi_data *fsl_lpspi =
	462	+ spi_controller_get_devdata(controller);
	463	+
	464	+ fsl_lpspi->slave_aborted = true;
	465	+ if (!fsl_lpspi->usedma)
	466	+ complete(&fsl_lpspi->xfer_done);
	467	+ else {
	468	+ complete(&fsl_lpspi->dma_tx_completion);
	469	+ complete(&fsl_lpspi->dma_rx_completion);
	470	+ }
	471	+
	472	+ return 0;
	473	+}
	474	+
	475	+static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
	476	+{
	477	+ struct fsl_lpspi_data *fsl_lpspi =
	478	+ spi_controller_get_devdata(controller);
	479	+
	480	+ if (fsl_lpspi->is_slave) {
	481	+ if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) \|\|
	482	+ fsl_lpspi->slave_aborted) {
	483	+ dev_dbg(fsl_lpspi->dev, "interrupted\n");
	484	+ return -EINTR;
	485	+ }
	486	+ } else {
	487	+ if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
	488	+ dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
	489	+ return -ETIMEDOUT;
	490	+ }
	491	+ }
	492	+
	493	+ return 0;
	494	+}
	495	+
	496	+static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
	497	+{
	498	+ u32 temp;
	499	+
	500	+ if (!fsl_lpspi->usedma) {
	501	+ /* Disable all interrupt */
	502	+ fsl_lpspi_intctrl(fsl_lpspi, 0);
	503	+ }
	504	+
	505	+ /* W1C for all flags in SR */
	506	+ temp = 0x3F << 8;
	507	+ writel(temp, fsl_lpspi->base + IMX7ULP_SR);
	508	+
	509	+ /* Clear FIFO and disable module */
	510	+ temp = CR_RRF \| CR_RTF;
	511	+ writel(temp, fsl_lpspi->base + IMX7ULP_CR);
	512	+
	513	+ return 0;
	514	+}
	515	+
	516	+static void fsl_lpspi_dma_rx_callback(void *cookie)
	517	+{
	518	+ struct fsl_lpspi_data fsl_lpspi = (struct fsl_lpspi_data )cookie;
	519	+
	520	+ complete(&fsl_lpspi->dma_rx_completion);
	521	+}
	522	+
	523	+static void fsl_lpspi_dma_tx_callback(void *cookie)
	524	+{
	525	+ struct fsl_lpspi_data fsl_lpspi = (struct fsl_lpspi_data )cookie;
	526	+
	527	+ complete(&fsl_lpspi->dma_tx_completion);
	528	+}
	529	+
	530	+static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
	531	+ int size)
	532	+{
	533	+ unsigned long timeout = 0;
	534	+
	535	+ /* Time with actual data transfer and CS change delay related to HW */
	536	+ timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
	537	+
	538	+ /* Add extra second for scheduler related activities */
	539	+ timeout += 1;
	540	+
	541	+ /* Double calculated timeout */
	542	+ return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
	543	+}
	544	+
	545	+static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
	546	+ struct fsl_lpspi_data *fsl_lpspi,
	547	+ struct spi_transfer *transfer)
	548	+{
	549	+ struct dma_async_tx_descriptor desc_tx, desc_rx;
	550	+ unsigned long transfer_timeout;
	551	+ unsigned long timeout;
	552	+ struct sg_table tx = &transfer->tx_sg, rx = &transfer->rx_sg;
	553	+ int ret;
	554	+
	555	+ ret = fsl_lpspi_dma_configure(controller);
	556	+ if (ret)
	557	+ return ret;
	558	+
	559	+ desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
	560	+ rx->sgl, rx->nents, DMA_DEV_TO_MEM,
	561	+ DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	562	+ if (!desc_rx)
	563	+ return -EINVAL;
	564	+
	565	+ desc_rx->callback = fsl_lpspi_dma_rx_callback;
	566	+ desc_rx->callback_param = (void *)fsl_lpspi;
	567	+ dmaengine_submit(desc_rx);
	568	+ reinit_completion(&fsl_lpspi->dma_rx_completion);
	569	+ dma_async_issue_pending(controller->dma_rx);
	570	+
	571	+ desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
	572	+ tx->sgl, tx->nents, DMA_MEM_TO_DEV,
	573	+ DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	574	+ if (!desc_tx) {
	575	+ dmaengine_terminate_all(controller->dma_tx);
	576	+ return -EINVAL;
	577	+ }
	578	+
	579	+ desc_tx->callback = fsl_lpspi_dma_tx_callback;
	580	+ desc_tx->callback_param = (void *)fsl_lpspi;
	581	+ dmaengine_submit(desc_tx);
	582	+ reinit_completion(&fsl_lpspi->dma_tx_completion);
	583	+ dma_async_issue_pending(controller->dma_tx);
	584	+
	585	+ fsl_lpspi->slave_aborted = false;
	586	+
	587	+ if (!fsl_lpspi->is_slave) {
	588	+ transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
	589	+ transfer->len);
	590	+
	591	+ /* Wait eDMA to finish the data transfer.*/
	592	+ timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
	593	+ transfer_timeout);
	594	+ if (!timeout) {
	595	+ dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
	596	+ dmaengine_terminate_all(controller->dma_tx);
	597	+ dmaengine_terminate_all(controller->dma_rx);
	598	+ fsl_lpspi_reset(fsl_lpspi);
	599	+ return -ETIMEDOUT;
	600	+ }
	601	+
	602	+ timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
	603	+ transfer_timeout);
	604	+ if (!timeout) {
	605	+ dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
	606	+ dmaengine_terminate_all(controller->dma_tx);
	607	+ dmaengine_terminate_all(controller->dma_rx);
	608	+ fsl_lpspi_reset(fsl_lpspi);
	609	+ return -ETIMEDOUT;
	610	+ }
	611	+ } else {
	612	+ if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) \|\|
	613	+ fsl_lpspi->slave_aborted) {
	614	+ dev_dbg(fsl_lpspi->dev,
	615	+ "I/O Error in DMA TX interrupted\n");
	616	+ dmaengine_terminate_all(controller->dma_tx);
	617	+ dmaengine_terminate_all(controller->dma_rx);
	618	+ fsl_lpspi_reset(fsl_lpspi);
	619	+ return -EINTR;
	620	+ }
	621	+
	622	+ if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) \|\|
	623	+ fsl_lpspi->slave_aborted) {
	624	+ dev_dbg(fsl_lpspi->dev,
	625	+ "I/O Error in DMA RX interrupted\n");
	626	+ dmaengine_terminate_all(controller->dma_tx);
	627	+ dmaengine_terminate_all(controller->dma_rx);
	628	+ fsl_lpspi_reset(fsl_lpspi);
	629	+ return -EINTR;
	630	+ }
	631	+ }
	632	+
	633	+ fsl_lpspi_reset(fsl_lpspi);
	634	+
	635	+ return 0;
	636	+}
	637	+
	638	+static void fsl_lpspi_dma_exit(struct spi_controller *controller)
	639	+{
	640	+ if (controller->dma_rx) {
	641	+ dma_release_channel(controller->dma_rx);
	642	+ controller->dma_rx = NULL;
	643	+ }
	644	+
	645	+ if (controller->dma_tx) {
	646	+ dma_release_channel(controller->dma_tx);
	647	+ controller->dma_tx = NULL;
	648	+ }
	649	+}
	650	+
	651	+static int fsl_lpspi_dma_init(struct device *dev,
	652	+ struct fsl_lpspi_data *fsl_lpspi,
	653	+ struct spi_controller *controller)
	654	+{
	655	+ int ret;
	656	+
	657	+ /* Prepare for TX DMA: */
	658	+ controller->dma_tx = dma_request_chan(dev, "tx");
	659	+ if (IS_ERR(controller->dma_tx)) {
	660	+ ret = PTR_ERR(controller->dma_tx);
	661	+ dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
	662	+ controller->dma_tx = NULL;
	663	+ goto err;
	664	+ }
	665	+
	666	+ /* Prepare for RX DMA: */
	667	+ controller->dma_rx = dma_request_chan(dev, "rx");
	668	+ if (IS_ERR(controller->dma_rx)) {
	669	+ ret = PTR_ERR(controller->dma_rx);
	670	+ dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
	671	+ controller->dma_rx = NULL;
	672	+ goto err;
	673	+ }
	674	+
	675	+ init_completion(&fsl_lpspi->dma_rx_completion);
	676	+ init_completion(&fsl_lpspi->dma_tx_completion);
	677	+ controller->can_dma = fsl_lpspi_can_dma;
	678	+ controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
	679	+
	680	+ return 0;
	681	+err:
	682	+ fsl_lpspi_dma_exit(controller);
	683	+ return ret;
	684	+}
	685	+
	686	+static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
323	687	struct spi_transfer *t)
324	688	{
325		- struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master);
	689	+ struct fsl_lpspi_data *fsl_lpspi =
	690	+ spi_controller_get_devdata(controller);
326	691	int ret;
327	692
328	693	fsl_lpspi->tx_buf = t->tx_buf;
..	..	@@ -330,110 +695,163 @@
330	695	fsl_lpspi->remain = t->len;
331	696
332	697	reinit_completion(&fsl_lpspi->xfer_done);
	698	+ fsl_lpspi->slave_aborted = false;
	699	+
333	700	fsl_lpspi_write_tx_fifo(fsl_lpspi);
334	701
335		- ret = wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ);
336		- if (!ret) {
337		- dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
338		- return -ETIMEDOUT;
339		- }
340		-
341		- ret = fsl_lpspi_txfifo_empty(fsl_lpspi);
	702	+ ret = fsl_lpspi_wait_for_completion(controller);
342	703	if (ret)
343	704	return ret;
344	705
345		- fsl_lpspi_read_rx_fifo(fsl_lpspi);
	706	+ fsl_lpspi_reset(fsl_lpspi);
346	707
347	708	return 0;
348	709	}
349	710
350		-static int fsl_lpspi_transfer_one_msg(struct spi_master *master,
351		- struct spi_message *msg)
	711	+static int fsl_lpspi_transfer_one(struct spi_controller *controller,
	712	+ struct spi_device *spi,
	713	+ struct spi_transfer *t)
352	714	{
353		- struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master);
354		- struct spi_device *spi = msg->spi;
355		- struct spi_transfer *xfer;
356		- bool is_first_xfer = true;
357		- u32 temp;
358		- int ret = 0;
	715	+ struct fsl_lpspi_data *fsl_lpspi =
	716	+ spi_controller_get_devdata(controller);
	717	+ int ret;
359	718
360		- msg->status = 0;
361		- msg->actual_length = 0;
	719	+ fsl_lpspi->is_first_byte = true;
	720	+ ret = fsl_lpspi_setup_transfer(controller, spi, t);
	721	+ if (ret < 0)
	722	+ return ret;
362	723
363		- list_for_each_entry(xfer, &msg->transfers, transfer_list) {
364		- fsl_lpspi_setup_transfer(spi, xfer);
365		- fsl_lpspi_set_cmd(fsl_lpspi, is_first_xfer);
	724	+ fsl_lpspi_set_cmd(fsl_lpspi);
	725	+ fsl_lpspi->is_first_byte = false;
366	726
367		- is_first_xfer = false;
	727	+ if (fsl_lpspi->usedma)
	728	+ ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
	729	+ else
	730	+ ret = fsl_lpspi_pio_transfer(controller, t);
	731	+ if (ret < 0)
	732	+ return ret;
368	733
369		- ret = fsl_lpspi_transfer_one(master, spi, xfer);
370		- if (ret < 0)
371		- goto complete;
372		-
373		- msg->actual_length += xfer->len;
374		- }
375		-
376		-complete:
377		- /* de-assert SS, then finalize current message */
378		- temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
379		- temp &= ~TCR_CONTC;
380		- writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
381		-
382		- msg->status = ret;
383		- spi_finalize_current_message(master);
384		-
385		- return ret;
	734	+ return 0;
386	735	}
387	736
388	737	static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
389	738	{
	739	+ u32 temp_SR, temp_IER;
390	740	struct fsl_lpspi_data *fsl_lpspi = dev_id;
391		- u32 temp;
392	741
	742	+ temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
393	743	fsl_lpspi_intctrl(fsl_lpspi, 0);
394		- temp = readl(fsl_lpspi->base + IMX7ULP_SR);
	744	+ temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
395	745
396	746	fsl_lpspi_read_rx_fifo(fsl_lpspi);
397	747
398		- if (temp & SR_TDF) {
	748	+ if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
399	749	fsl_lpspi_write_tx_fifo(fsl_lpspi);
	750	+ return IRQ_HANDLED;
	751	+ }
400	752
401		- if (!fsl_lpspi->remain)
402		- complete(&fsl_lpspi->xfer_done);
	753	+ if (temp_SR & SR_MBF \|\|
	754	+ readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
	755	+ writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
	756	+ fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
	757	+ return IRQ_HANDLED;
	758	+ }
403	759
	760	+ if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
	761	+ writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
	762	+ complete(&fsl_lpspi->xfer_done);
404	763	return IRQ_HANDLED;
405	764	}
406	765
407	766	return IRQ_NONE;
408	767	}
409	768
	769	+#ifdef CONFIG_PM
	770	+static int fsl_lpspi_runtime_resume(struct device *dev)
	771	+{
	772	+ struct spi_controller *controller = dev_get_drvdata(dev);
	773	+ struct fsl_lpspi_data *fsl_lpspi;
	774	+ int ret;
	775	+
	776	+ fsl_lpspi = spi_controller_get_devdata(controller);
	777	+
	778	+ ret = clk_prepare_enable(fsl_lpspi->clk_per);
	779	+ if (ret)
	780	+ return ret;
	781	+
	782	+ ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
	783	+ if (ret) {
	784	+ clk_disable_unprepare(fsl_lpspi->clk_per);
	785	+ return ret;
	786	+ }
	787	+
	788	+ return 0;
	789	+}
	790	+
	791	+static int fsl_lpspi_runtime_suspend(struct device *dev)
	792	+{
	793	+ struct spi_controller *controller = dev_get_drvdata(dev);
	794	+ struct fsl_lpspi_data *fsl_lpspi;
	795	+
	796	+ fsl_lpspi = spi_controller_get_devdata(controller);
	797	+
	798	+ clk_disable_unprepare(fsl_lpspi->clk_per);
	799	+ clk_disable_unprepare(fsl_lpspi->clk_ipg);
	800	+
	801	+ return 0;
	802	+}
	803	+#endif
	804	+
	805	+static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
	806	+{
	807	+ struct device *dev = fsl_lpspi->dev;
	808	+
	809	+ pm_runtime_enable(dev);
	810	+ pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
	811	+ pm_runtime_use_autosuspend(dev);
	812	+
	813	+ return 0;
	814	+}
	815	+
410	816	static int fsl_lpspi_probe(struct platform_device *pdev)
411	817	{
412	818	struct fsl_lpspi_data *fsl_lpspi;
413		- struct spi_master *master;
	819	+ struct spi_controller *controller;
414	820	struct resource *res;
415	821	int ret, irq;
416	822	u32 temp;
	823	+ bool is_slave;
417	824
418		- master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_lpspi_data));
419		- if (!master)
	825	+ is_slave = of_property_read_bool((&pdev->dev)->of_node, "spi-slave");
	826	+ if (is_slave)
	827	+ controller = spi_alloc_slave(&pdev->dev,
	828	+ sizeof(struct fsl_lpspi_data));
	829	+ else
	830	+ controller = spi_alloc_master(&pdev->dev,
	831	+ sizeof(struct fsl_lpspi_data));
	832	+
	833	+ if (!controller)
420	834	return -ENOMEM;
421	835
422		- platform_set_drvdata(pdev, master);
	836	+ platform_set_drvdata(pdev, controller);
423	837
424		- master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
425		- master->bus_num = pdev->id;
426		-
427		- fsl_lpspi = spi_master_get_devdata(master);
	838	+ fsl_lpspi = spi_controller_get_devdata(controller);
428	839	fsl_lpspi->dev = &pdev->dev;
	840	+ fsl_lpspi->is_slave = is_slave;
	841	+ fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
	842	+ "fsl,spi-only-use-cs1-sel");
429	843
430		- master->transfer_one_message = fsl_lpspi_transfer_one_msg;
431		- master->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
432		- master->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
433		- master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH;
434		- master->flags = SPI_MASTER_MUST_RX \| SPI_MASTER_MUST_TX;
435		- master->dev.of_node = pdev->dev.of_node;
436		- master->bus_num = pdev->id;
	844	+ controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
	845	+ controller->transfer_one = fsl_lpspi_transfer_one;
	846	+ controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
	847	+ controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
	848	+ controller->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH;
	849	+ controller->flags = SPI_MASTER_MUST_RX \| SPI_MASTER_MUST_TX;
	850	+ controller->dev.of_node = pdev->dev.of_node;
	851	+ controller->bus_num = pdev->id;
	852	+ controller->slave_abort = fsl_lpspi_slave_abort;
	853	+ if (!fsl_lpspi->is_slave)
	854	+ controller->use_gpio_descriptors = true;
437	855
438	856	init_completion(&fsl_lpspi->xfer_done);
439	857
..	..	@@ -441,74 +859,134 @@
441	859	fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
442	860	if (IS_ERR(fsl_lpspi->base)) {
443	861	ret = PTR_ERR(fsl_lpspi->base);
444		- goto out_master_put;
	862	+ goto out_controller_put;
445	863	}
	864	+ fsl_lpspi->base_phys = res->start;
446	865
447	866	irq = platform_get_irq(pdev, 0);
448	867	if (irq < 0) {
449	868	ret = irq;
450		- goto out_master_put;
	869	+ goto out_controller_put;
451	870	}
452	871
453	872	ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
454	873	dev_name(&pdev->dev), fsl_lpspi);
455	874	if (ret) {
456	875	dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
457		- goto out_master_put;
	876	+ goto out_controller_put;
458	877	}
459	878
460		- fsl_lpspi->clk = devm_clk_get(&pdev->dev, "ipg");
461		- if (IS_ERR(fsl_lpspi->clk)) {
462		- ret = PTR_ERR(fsl_lpspi->clk);
463		- goto out_master_put;
	879	+ fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
	880	+ if (IS_ERR(fsl_lpspi->clk_per)) {
	881	+ ret = PTR_ERR(fsl_lpspi->clk_per);
	882	+ goto out_controller_put;
464	883	}
465	884
466		- ret = clk_prepare_enable(fsl_lpspi->clk);
467		- if (ret) {
468		- dev_err(&pdev->dev, "can't enable lpspi clock, ret=%d\n", ret);
469		- goto out_master_put;
	885	+ fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	886	+ if (IS_ERR(fsl_lpspi->clk_ipg)) {
	887	+ ret = PTR_ERR(fsl_lpspi->clk_ipg);
	888	+ goto out_controller_put;
	889	+ }
	890	+
	891	+ /* enable the clock */
	892	+ ret = fsl_lpspi_init_rpm(fsl_lpspi);
	893	+ if (ret)
	894	+ goto out_controller_put;
	895	+
	896	+ ret = pm_runtime_get_sync(fsl_lpspi->dev);
	897	+ if (ret < 0) {
	898	+ dev_err(fsl_lpspi->dev, "failed to enable clock\n");
	899	+ goto out_pm_get;
470	900	}
471	901
472	902	temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
473	903	fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
474	904	fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
475	905
476		- clk_disable_unprepare(fsl_lpspi->clk);
	906	+ ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
	907	+ if (ret == -EPROBE_DEFER)
	908	+ goto out_pm_get;
	909	+ if (ret < 0)
	910	+ dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret);
	911	+ else
	912	+ /*
	913	+ * disable LPSPI module IRQ when enable DMA mode successfully,
	914	+ * to prevent the unexpected LPSPI module IRQ events.
	915	+ */
	916	+ disable_irq(irq);
477	917
478		- ret = devm_spi_register_master(&pdev->dev, master);
	918	+ ret = devm_spi_register_controller(&pdev->dev, controller);
479	919	if (ret < 0) {
480		- dev_err(&pdev->dev, "spi_register_master error.\n");
481		- goto out_master_put;
	920	+ dev_err(&pdev->dev, "spi_register_controller error.\n");
	921	+ goto out_pm_get;
482	922	}
	923	+
	924	+ pm_runtime_mark_last_busy(fsl_lpspi->dev);
	925	+ pm_runtime_put_autosuspend(fsl_lpspi->dev);
483	926
484	927	return 0;
485	928
486		-out_master_put:
487		- spi_master_put(master);
	929	+out_pm_get:
	930	+ pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
	931	+ pm_runtime_put_sync(fsl_lpspi->dev);
	932	+ pm_runtime_disable(fsl_lpspi->dev);
	933	+out_controller_put:
	934	+ spi_controller_put(controller);
488	935
489	936	return ret;
490	937	}
491	938
492	939	static int fsl_lpspi_remove(struct platform_device *pdev)
493	940	{
494		- struct spi_master *master = platform_get_drvdata(pdev);
495		- struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master);
	941	+ struct spi_controller *controller = platform_get_drvdata(pdev);
	942	+ struct fsl_lpspi_data *fsl_lpspi =
	943	+ spi_controller_get_devdata(controller);
496	944
497		- clk_disable_unprepare(fsl_lpspi->clk);
	945	+ pm_runtime_disable(fsl_lpspi->dev);
	946	+ return 0;
	947	+}
	948	+
	949	+static int __maybe_unused fsl_lpspi_suspend(struct device *dev)
	950	+{
	951	+ int ret;
	952	+
	953	+ pinctrl_pm_select_sleep_state(dev);
	954	+ ret = pm_runtime_force_suspend(dev);
	955	+ return ret;
	956	+}
	957	+
	958	+static int __maybe_unused fsl_lpspi_resume(struct device *dev)
	959	+{
	960	+ int ret;
	961	+
	962	+ ret = pm_runtime_force_resume(dev);
	963	+ if (ret) {
	964	+ dev_err(dev, "Error in resume: %d\n", ret);
	965	+ return ret;
	966	+ }
	967	+
	968	+ pinctrl_pm_select_default_state(dev);
498	969
499	970	return 0;
500	971	}
	972	+
	973	+static const struct dev_pm_ops fsl_lpspi_pm_ops = {
	974	+ SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
	975	+ fsl_lpspi_runtime_resume, NULL)
	976	+ SET_SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
	977	+};
501	978
502	979	static struct platform_driver fsl_lpspi_driver = {
503	980	.driver = {
504	981	.name = DRIVER_NAME,
505	982	.of_match_table = fsl_lpspi_dt_ids,
	983	+ .pm = &fsl_lpspi_pm_ops,
506	984	},
507	985	.probe = fsl_lpspi_probe,
508	986	.remove = fsl_lpspi_remove,
509	987	};
510	988	module_platform_driver(fsl_lpspi_driver);
511	989
512		-MODULE_DESCRIPTION("LPSPI Master Controller driver");
	990	+MODULE_DESCRIPTION("LPSPI Controller driver");
513	991	MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
514	992	MODULE_LICENSE("GPL");