write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/spi/spi-fsl-dspi.c
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@@ -975,7 +975,9 @@
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 static int dspi_setup(struct spi_device *spi)
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 {
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 	struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
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+	u32 period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->max_speed_hz);
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 	unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
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+	u32 quarter_period_ns = DIV_ROUND_UP(period_ns, 4);
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 	u32 cs_sck_delay = 0, sck_cs_delay = 0;
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 	struct fsl_dspi_platform_data *pdata;
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 	unsigned char pasc = 0, asc = 0;
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@@ -1003,6 +1005,19 @@
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 		sck_cs_delay = pdata->sck_cs_delay;
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 	}
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+	/* Since tCSC and tASC apply to continuous transfers too, avoid SCK
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+	 * glitches of half a cycle by never allowing tCSC + tASC to go below
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+	 * half a SCK period.
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+	 */
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+	if (cs_sck_delay < quarter_period_ns)
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+		cs_sck_delay = quarter_period_ns;
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+	if (sck_cs_delay < quarter_period_ns)
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+		sck_cs_delay = quarter_period_ns;
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+
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+	dev_dbg(&spi->dev,
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+		"DSPI controller timing params: CS-to-SCK delay %u ns, SCK-to-CS delay %u ns\n",
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+		cs_sck_delay, sck_cs_delay);
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+
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 	clkrate = clk_get_rate(dspi->clk);
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 	hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
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