write in 30M

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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/rtc/rtc-xgene.c
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@@ -1,34 +1,21 @@
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+// SPDX-License-Identifier: GPL-2.0+
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 /*
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  * APM X-Gene SoC Real Time Clock Driver
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  *
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  * Copyright (c) 2014, Applied Micro Circuits Corporation
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  * Author: Rameshwar Prasad Sahu <rsahu@apm.com>
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  *         Loc Ho <lho@apm.com>
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- *
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- * This program is free software; you can redistribute  it and/or modify it
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- * under  the terms of  the GNU General  Public License as published by the
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- * Free Software Foundation;  either version 2 of the  License, or (at your
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- * option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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- *
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  */
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+#include <linux/clk.h>
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+#include <linux/delay.h>
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 #include <linux/init.h>
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+#include <linux/io.h>
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 #include <linux/module.h>
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 #include <linux/of.h>
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 #include <linux/platform_device.h>
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-#include <linux/io.h>
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-#include <linux/slab.h>
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-#include <linux/clk.h>
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-#include <linux/delay.h>
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 #include <linux/rtc.h>
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+#include <linux/slab.h>
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 /* RTC CSR Registers */
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 #define RTC_CCVR		0x00
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@@ -47,8 +34,6 @@
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34
 
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 struct xgene_rtc_dev {
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 	struct rtc_device *rtc;
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-	struct device *dev;
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-	unsigned long alarm_time;
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 	void __iomem *csr_base;
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 	struct clk *clk;
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 	unsigned int irq_wake;
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@@ -59,11 +44,11 @@
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 {
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 	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
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-	rtc_time_to_tm(readl(pdata->csr_base + RTC_CCVR), tm);
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+	rtc_time64_to_tm(readl(pdata->csr_base + RTC_CCVR), tm);
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 	return 0;
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 }
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-static int xgene_rtc_set_mmss(struct device *dev, unsigned long secs)
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+static int xgene_rtc_set_time(struct device *dev, struct rtc_time *tm)
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 {
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 	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
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@@ -71,7 +56,7 @@
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 	 * NOTE: After the following write, the RTC_CCVR is only reflected
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 	 *       after the update cycle of 1 seconds.
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 	 */
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-	writel((u32) secs, pdata->csr_base + RTC_CLR);
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+	writel((u32)rtc_tm_to_time64(tm), pdata->csr_base + RTC_CLR);
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 	readl(pdata->csr_base + RTC_CLR); /* Force a barrier */
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 	return 0;
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@@ -81,7 +66,8 @@
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 {
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 	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
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-	rtc_time_to_tm(pdata->alarm_time, &alrm->time);
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+	/* If possible, CMR should be read here */
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+	rtc_time64_to_tm(0, &alrm->time);
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 	alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE;
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 	return 0;
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@@ -115,11 +101,8 @@
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 static int xgene_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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 {
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 	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
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-	unsigned long alarm_time;
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-	rtc_tm_to_time(&alrm->time, &alarm_time);
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-	pdata->alarm_time = alarm_time;
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-	writel((u32) pdata->alarm_time, pdata->csr_base + RTC_CMR);
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+	writel((u32)rtc_tm_to_time64(&alrm->time), pdata->csr_base + RTC_CMR);
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 	xgene_rtc_alarm_irq_enable(dev, alrm->enabled);
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@@ -128,7 +111,7 @@
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 static const struct rtc_class_ops xgene_rtc_ops = {
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 	.read_time	= xgene_rtc_read_time,
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-	.set_mmss	= xgene_rtc_set_mmss,
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+	.set_time	= xgene_rtc_set_time,
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 	.read_alarm	= xgene_rtc_read_alarm,
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 	.set_alarm	= xgene_rtc_set_alarm,
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 	.alarm_irq_enable = xgene_rtc_alarm_irq_enable,
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@@ -136,7 +119,7 @@
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 static irqreturn_t xgene_rtc_interrupt(int irq, void *id)
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 {
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-	struct xgene_rtc_dev *pdata = (struct xgene_rtc_dev *) id;
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+	struct xgene_rtc_dev *pdata = id;
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 	/* Check if interrupt asserted */
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 	if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT))
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@@ -153,7 +136,6 @@
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 static int xgene_rtc_probe(struct platform_device *pdev)
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 {
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 	struct xgene_rtc_dev *pdata;
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-	struct resource *res;
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 	int ret;
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 	int irq;
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@@ -161,10 +143,8 @@
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 	if (!pdata)
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 		return -ENOMEM;
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 	platform_set_drvdata(pdev, pdata);
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-	pdata->dev = &pdev->dev;
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-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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-	pdata->csr_base = devm_ioremap_resource(&pdev->dev, res);
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+	pdata->csr_base = devm_platform_ioremap_resource(pdev, 0);
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 	if (IS_ERR(pdata->csr_base))
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 		return PTR_ERR(pdata->csr_base);
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@@ -173,10 +153,8 @@
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 		return PTR_ERR(pdata->rtc);
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 	irq = platform_get_irq(pdev, 0);
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-	if (irq < 0) {
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-		dev_err(&pdev->dev, "No IRQ resource\n");
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+	if (irq < 0)
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 		return irq;
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-	}
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 	ret = devm_request_irq(&pdev->dev, irq, xgene_rtc_interrupt, 0,
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 			       dev_name(&pdev->dev), pdata);
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 	if (ret) {
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@@ -205,6 +183,7 @@
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 	/* HW does not support update faster than 1 seconds */
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 	pdata->rtc->uie_unsupported = 1;
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 	pdata->rtc->ops = &xgene_rtc_ops;
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+	pdata->rtc->range_max = U32_MAX;
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 	ret = rtc_register_device(pdata->rtc);
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 	if (ret) {