forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/drivers/rtc/rtc-sun6i.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * An RTC driver for Allwinner A31/A23
34  *
....@@ -8,16 +9,6 @@
89  * An RTC driver for Allwinner A10/A20
910  *
1011  * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
11
- *
12
- * This program is free software; you can redistribute it and/or modify
13
- * it under the terms of the GNU General Public License as published by
14
- * the Free Software Foundation; either version 2 of the License, or
15
- * (at your option) any later version.
16
- *
17
- * This program is distributed in the hope that it will be useful, but WITHOUT
18
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
20
- * more details.
2112  */
2213 
2314 #include <linux/clk.h>
....@@ -41,9 +32,11 @@
4132 /* Control register */
4233 #define SUN6I_LOSC_CTRL				0x0000
4334 #define SUN6I_LOSC_CTRL_KEY			(0x16aa << 16)
35
+#define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS		BIT(15)
4436 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC		BIT(9)
4537 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC		BIT(8)
4638 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC		BIT(7)
39
+#define SUN6I_LOSC_CTRL_EXT_LOSC_EN		BIT(4)
4740 #define SUN6I_LOSC_CTRL_EXT_OSC			BIT(0)
4841 #define SUN6I_LOSC_CTRL_ACC_MASK		GENMASK(9, 7)
4942 
....@@ -115,15 +108,36 @@
115108  * driver, even though it is somewhat limited.
116109  */
117110 #define SUN6I_YEAR_MIN				1970
118
-#define SUN6I_YEAR_MAX				2033
119111 #define SUN6I_YEAR_OFF				(SUN6I_YEAR_MIN - 1900)
112
+
113
+/*
114
+ * There are other differences between models, including:
115
+ *
116
+ *   - number of GPIO pins that can be configured to hold a certain level
117
+ *   - crypto-key related registers (H5, H6)
118
+ *   - boot process related (super standby, secondary processor entry address)
119
+ *     registers (R40, H6)
120
+ *   - SYS power domain controls (R40)
121
+ *   - DCXO controls (H6)
122
+ *   - RC oscillator calibration (H6)
123
+ *
124
+ * These functions are not covered by this driver.
125
+ */
126
+struct sun6i_rtc_clk_data {
127
+	unsigned long rc_osc_rate;
128
+	unsigned int fixed_prescaler : 16;
129
+	unsigned int has_prescaler : 1;
130
+	unsigned int has_out_clk : 1;
131
+	unsigned int has_losc_en : 1;
132
+	unsigned int has_auto_swt : 1;
133
+};
120134 
121135 struct sun6i_rtc_dev {
122136 	struct rtc_device *rtc;
123
-	struct device *dev;
137
+	const struct sun6i_rtc_clk_data *data;
124138 	void __iomem *base;
125139 	int irq;
126
-	unsigned long alarm;
140
+	time64_t alarm;
127141 
128142 	struct clk_hw hw;
129143 	struct clk_hw *int_osc;
....@@ -139,14 +153,19 @@
139153 					       unsigned long parent_rate)
140154 {
141155 	struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
142
-	u32 val;
156
+	u32 val = 0;
143157 
144158 	val = readl(rtc->base + SUN6I_LOSC_CTRL);
145159 	if (val & SUN6I_LOSC_CTRL_EXT_OSC)
146160 		return parent_rate;
147161 
148
-	val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
149
-	val &= GENMASK(4, 0);
162
+	if (rtc->data->fixed_prescaler)
163
+		parent_rate /= rtc->data->fixed_prescaler;
164
+
165
+	if (rtc->data->has_prescaler) {
166
+		val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
167
+		val &= GENMASK(4, 0);
168
+	}
150169 
151170 	return parent_rate / (val + 1);
152171 }
....@@ -172,6 +191,10 @@
172191 	val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
173192 	val |= SUN6I_LOSC_CTRL_KEY;
174193 	val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
194
+	if (rtc->data->has_losc_en) {
195
+		val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN;
196
+		val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0;
197
+	}
175198 	writel(val, rtc->base + SUN6I_LOSC_CTRL);
176199 	spin_unlock_irqrestore(&rtc->lock, flags);
177200 
....@@ -185,22 +208,26 @@
185208 	.set_parent	= sun6i_rtc_osc_set_parent,
186209 };
187210 
188
-static void __init sun6i_rtc_clk_init(struct device_node *node)
211
+static void __init sun6i_rtc_clk_init(struct device_node *node,
212
+				      const struct sun6i_rtc_clk_data *data)
189213 {
190214 	struct clk_hw_onecell_data *clk_data;
191215 	struct sun6i_rtc_dev *rtc;
192216 	struct clk_init_data init = {
193217 		.ops		= &sun6i_rtc_osc_ops,
218
+		.name		= "losc",
194219 	};
220
+	const char *iosc_name = "rtc-int-osc";
195221 	const char *clkout_name = "osc32k-out";
196222 	const char *parents[2];
223
+	u32 reg;
197224 
198225 	rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
199226 	if (!rtc)
200227 		return;
201228 
202
-	clk_data = kzalloc(sizeof(*clk_data) + (sizeof(*clk_data->hws) * 2),
203
-			   GFP_KERNEL);
229
+	rtc->data = data;
230
+	clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL);
204231 	if (!clk_data) {
205232 		kfree(rtc);
206233 		return;
....@@ -214,21 +241,31 @@
214241 		goto err;
215242 	}
216243 
217
-	/* Switch to the external, more precise, oscillator */
218
-	writel(SUN6I_LOSC_CTRL_KEY | SUN6I_LOSC_CTRL_EXT_OSC,
219
-	       rtc->base + SUN6I_LOSC_CTRL);
244
+	reg = SUN6I_LOSC_CTRL_KEY;
245
+	if (rtc->data->has_auto_swt) {
246
+		/* Bypass auto-switch to int osc, on ext losc failure */
247
+		reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS;
248
+		writel(reg, rtc->base + SUN6I_LOSC_CTRL);
249
+	}
250
+
251
+	/* Switch to the external, more precise, oscillator, if present */
252
+	if (of_get_property(node, "clocks", NULL)) {
253
+		reg |= SUN6I_LOSC_CTRL_EXT_OSC;
254
+		if (rtc->data->has_losc_en)
255
+			reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;
256
+	}
257
+	writel(reg, rtc->base + SUN6I_LOSC_CTRL);
220258 
221259 	/* Yes, I know, this is ugly. */
222260 	sun6i_rtc = rtc;
223261 
224
-	/* Deal with old DTs */
225
-	if (!of_get_property(node, "clocks", NULL))
226
-		goto err;
262
+	of_property_read_string_index(node, "clock-output-names", 2,
263
+				      &iosc_name);
227264 
228265 	rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
229
-								"rtc-int-osc",
266
+								iosc_name,
230267 								NULL, 0,
231
-								667000,
268
+								rtc->data->rc_osc_rate,
232269 								300000000);
233270 	if (IS_ERR(rtc->int_osc)) {
234271 		pr_crit("Couldn't register the internal oscillator\n");
....@@ -236,11 +273,13 @@
236273 	}
237274 
238275 	parents[0] = clk_hw_get_name(rtc->int_osc);
276
+	/* If there is no external oscillator, this will be NULL and ... */
239277 	parents[1] = of_clk_get_parent_name(node, 0);
240278 
241279 	rtc->hw.init = &init;
242280 
243281 	init.parent_names = parents;
282
+	/* ... number of clock parents will be 1. */
244283 	init.num_parents = of_clk_get_parent_count(node) + 1;
245284 	of_property_read_string_index(node, "clock-output-names", 0,
246285 				      &init.name);
....@@ -253,7 +292,7 @@
253292 
254293 	of_property_read_string_index(node, "clock-output-names", 1,
255294 				      &clkout_name);
256
-	rtc->ext_losc = clk_register_gate(NULL, clkout_name, rtc->hw.init->name,
295
+	rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name,
257296 					  0, rtc->base + SUN6I_LOSC_OUT_GATING,
258297 					  SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
259298 					  &rtc->lock);
....@@ -262,9 +301,10 @@
262301 		goto err_register;
263302 	}
264303 
265
-	clk_data->num = 2;
304
+	clk_data->num = 3;
266305 	clk_data->hws[0] = &rtc->hw;
267306 	clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
307
+	clk_data->hws[2] = rtc->int_osc;
268308 	of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
269309 	return;
270310 
....@@ -273,8 +313,92 @@
273313 err:
274314 	kfree(clk_data);
275315 }
276
-CLK_OF_DECLARE_DRIVER(sun6i_rtc_clk, "allwinner,sun6i-a31-rtc",
277
-		      sun6i_rtc_clk_init);
316
+
317
+static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = {
318
+	.rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
319
+	.has_prescaler = 1,
320
+};
321
+
322
+static void __init sun6i_a31_rtc_clk_init(struct device_node *node)
323
+{
324
+	sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data);
325
+}
326
+CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc",
327
+		      sun6i_a31_rtc_clk_init);
328
+
329
+static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = {
330
+	.rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
331
+	.has_prescaler = 1,
332
+	.has_out_clk = 1,
333
+};
334
+
335
+static void __init sun8i_a23_rtc_clk_init(struct device_node *node)
336
+{
337
+	sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data);
338
+}
339
+CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc",
340
+		      sun8i_a23_rtc_clk_init);
341
+
342
+static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = {
343
+	.rc_osc_rate = 16000000,
344
+	.fixed_prescaler = 32,
345
+	.has_prescaler = 1,
346
+	.has_out_clk = 1,
347
+};
348
+
349
+static void __init sun8i_h3_rtc_clk_init(struct device_node *node)
350
+{
351
+	sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data);
352
+}
353
+CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc",
354
+		      sun8i_h3_rtc_clk_init);
355
+/* As far as we are concerned, clocks for H5 are the same as H3 */
356
+CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc",
357
+		      sun8i_h3_rtc_clk_init);
358
+
359
+static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = {
360
+	.rc_osc_rate = 16000000,
361
+	.fixed_prescaler = 32,
362
+	.has_prescaler = 1,
363
+	.has_out_clk = 1,
364
+	.has_losc_en = 1,
365
+	.has_auto_swt = 1,
366
+};
367
+
368
+static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
369
+{
370
+	sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data);
371
+}
372
+CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
373
+		      sun50i_h6_rtc_clk_init);
374
+
375
+/*
376
+ * The R40 user manual is self-conflicting on whether the prescaler is
377
+ * fixed or configurable. The clock diagram shows it as fixed, but there
378
+ * is also a configurable divider in the RTC block.
379
+ */
380
+static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = {
381
+	.rc_osc_rate = 16000000,
382
+	.fixed_prescaler = 512,
383
+};
384
+static void __init sun8i_r40_rtc_clk_init(struct device_node *node)
385
+{
386
+	sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data);
387
+}
388
+CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc",
389
+		      sun8i_r40_rtc_clk_init);
390
+
391
+static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = {
392
+	.rc_osc_rate = 32000,
393
+	.has_out_clk = 1,
394
+};
395
+
396
+static void __init sun8i_v3_rtc_clk_init(struct device_node *node)
397
+{
398
+	sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data);
399
+}
400
+CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc",
401
+		      sun8i_v3_rtc_clk_init);
278402 
279403 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
280404 {
....@@ -368,7 +492,7 @@
368492 
369493 	wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
370494 	wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
371
-	rtc_time_to_tm(chip->alarm, &wkalrm->time);
495
+	rtc_time64_to_tm(chip->alarm, &wkalrm->time);
372496 
373497 	return 0;
374498 }
....@@ -378,10 +502,8 @@
378502 	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
379503 	struct rtc_time *alrm_tm = &wkalrm->time;
380504 	struct rtc_time tm_now;
381
-	unsigned long time_now = 0;
382
-	unsigned long time_set = 0;
383
-	unsigned long time_gap = 0;
384
-	int ret = 0;
505
+	time64_t time_now, time_set;
506
+	int ret;
385507 
386508 	ret = sun6i_rtc_gettime(dev, &tm_now);
387509 	if (ret < 0) {
....@@ -389,16 +511,14 @@
389511 		return -EINVAL;
390512 	}
391513 
392
-	rtc_tm_to_time(alrm_tm, &time_set);
393
-	rtc_tm_to_time(&tm_now, &time_now);
514
+	time_set = rtc_tm_to_time64(alrm_tm);
515
+	time_now = rtc_tm_to_time64(&tm_now);
394516 	if (time_set <= time_now) {
395517 		dev_err(dev, "Date to set in the past\n");
396518 		return -EINVAL;
397519 	}
398520 
399
-	time_gap = time_set - time_now;
400
-
401
-	if (time_gap > U32_MAX) {
521
+	if ((time_set - time_now) > U32_MAX) {
402522 		dev_err(dev, "Date too far in the future\n");
403523 		return -EINVAL;
404524 	}
....@@ -407,7 +527,7 @@
407527 	writel(0, chip->base + SUN6I_ALRM_COUNTER);
408528 	usleep_range(100, 300);
409529 
410
-	writel(time_gap, chip->base + SUN6I_ALRM_COUNTER);
530
+	writel(time_set - time_now, chip->base + SUN6I_ALRM_COUNTER);
411531 	chip->alarm = time_set;
412532 
413533 	sun6i_rtc_setaie(wkalrm->enabled, chip);
....@@ -438,14 +558,6 @@
438558 	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
439559 	u32 date = 0;
440560 	u32 time = 0;
441
-	int year;
442
-
443
-	year = rtc_tm->tm_year + 1900;
444
-	if (year < SUN6I_YEAR_MIN || year > SUN6I_YEAR_MAX) {
445
-		dev_err(dev, "rtc only supports year in range %d - %d\n",
446
-			SUN6I_YEAR_MIN, SUN6I_YEAR_MAX);
447
-		return -EINVAL;
448
-	}
449561 
450562 	rtc_tm->tm_year -= SUN6I_YEAR_OFF;
451563 	rtc_tm->tm_mon += 1;
....@@ -454,7 +566,7 @@
454566 		SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon)  |
455567 		SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
456568 
457
-	if (is_leap_year(year))
569
+	if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN))
458570 		date |= SUN6I_LEAP_SET_VALUE(1);
459571 
460572 	time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec)  |
....@@ -517,6 +629,33 @@
517629 	.alarm_irq_enable	= sun6i_rtc_alarm_irq_enable
518630 };
519631 
632
+#ifdef CONFIG_PM_SLEEP
633
+/* Enable IRQ wake on suspend, to wake up from RTC. */
634
+static int sun6i_rtc_suspend(struct device *dev)
635
+{
636
+	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
637
+
638
+	if (device_may_wakeup(dev))
639
+		enable_irq_wake(chip->irq);
640
+
641
+	return 0;
642
+}
643
+
644
+/* Disable IRQ wake on resume. */
645
+static int sun6i_rtc_resume(struct device *dev)
646
+{
647
+	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
648
+
649
+	if (device_may_wakeup(dev))
650
+		disable_irq_wake(chip->irq);
651
+
652
+	return 0;
653
+}
654
+#endif
655
+
656
+static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
657
+	sun6i_rtc_suspend, sun6i_rtc_resume);
658
+
520659 static int sun6i_rtc_probe(struct platform_device *pdev)
521660 {
522661 	struct sun6i_rtc_dev *chip = sun6i_rtc;
....@@ -526,13 +665,10 @@
526665 		return -ENODEV;
527666 
528667 	platform_set_drvdata(pdev, chip);
529
-	chip->dev = &pdev->dev;
530668 
531669 	chip->irq = platform_get_irq(pdev, 0);
532
-	if (chip->irq < 0) {
533
-		dev_err(&pdev->dev, "No IRQ resource\n");
670
+	if (chip->irq < 0)
534671 		return chip->irq;
535
-	}
536672 
537673 	ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
538674 			       0, dev_name(&pdev->dev), chip);
....@@ -569,20 +705,38 @@
569705 
570706 	clk_prepare_enable(chip->losc);
571707 
572
-	chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-sun6i",
573
-					     &sun6i_rtc_ops, THIS_MODULE);
574
-	if (IS_ERR(chip->rtc)) {
575
-		dev_err(&pdev->dev, "unable to register device\n");
708
+	device_init_wakeup(&pdev->dev, 1);
709
+
710
+	chip->rtc = devm_rtc_allocate_device(&pdev->dev);
711
+	if (IS_ERR(chip->rtc))
576712 		return PTR_ERR(chip->rtc);
577
-	}
713
+
714
+	chip->rtc->ops = &sun6i_rtc_ops;
715
+	chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */
716
+
717
+	ret = rtc_register_device(chip->rtc);
718
+	if (ret)
719
+		return ret;
578720 
579721 	dev_info(&pdev->dev, "RTC enabled\n");
580722 
581723 	return 0;
582724 }
583725 
726
+/*
727
+ * As far as RTC functionality goes, all models are the same. The
728
+ * datasheets claim that different models have different number of
729
+ * registers available for non-volatile storage, but experiments show
730
+ * that all SoCs have 16 registers available for this purpose.
731
+ */
584732 static const struct of_device_id sun6i_rtc_dt_ids[] = {
585733 	{ .compatible = "allwinner,sun6i-a31-rtc" },
734
+	{ .compatible = "allwinner,sun8i-a23-rtc" },
735
+	{ .compatible = "allwinner,sun8i-h3-rtc" },
736
+	{ .compatible = "allwinner,sun8i-r40-rtc" },
737
+	{ .compatible = "allwinner,sun8i-v3-rtc" },
738
+	{ .compatible = "allwinner,sun50i-h5-rtc" },
739
+	{ .compatible = "allwinner,sun50i-h6-rtc" },
586740 	{ /* sentinel */ },
587741 };
588742 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
....@@ -592,6 +746,7 @@
592746 	.driver		= {
593747 		.name		= "sun6i-rtc",
594748 		.of_match_table = sun6i_rtc_dt_ids,
749
+		.pm = &sun6i_rtc_pm_ops,
595750 	},
596751 };
597752 builtin_platform_driver(sun6i_rtc_driver);