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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/pwm/pwm-mtk-disp.c
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..
@@ -1,16 +1,8 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * MediaTek display pulse-width-modulation controller driver.
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  * Copyright (c) 2015 MediaTek Inc.
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  * Author: YH Huang <yh.huang@mediatek.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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7
 
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 #include <linux/clk.h>
..
..
@@ -82,6 +74,19 @@
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 	u64 div, rate;
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 	int err;
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+	err = clk_prepare_enable(mdp->clk_main);
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+	if (err < 0) {
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+		dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
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+		return err;
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+	}
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+
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+	err = clk_prepare_enable(mdp->clk_mm);
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+	if (err < 0) {
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+		dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
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+		clk_disable_unprepare(mdp->clk_main);
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+		return err;
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+	}
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+
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 	/*
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 	 * Find period, high_width and clk_div to suit duty_ns and period_ns.
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 	 * Calculate proper div value to keep period value in the bound.
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@@ -95,8 +100,11 @@
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 	rate = clk_get_rate(mdp->clk_main);
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 	clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >>
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 			  PWM_PERIOD_BIT_WIDTH;
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-	if (clk_div > PWM_CLKDIV_MAX)
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+	if (clk_div > PWM_CLKDIV_MAX) {
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+		clk_disable_unprepare(mdp->clk_mm);
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+		clk_disable_unprepare(mdp->clk_main);
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 		return -EINVAL;
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+	}
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 	div = NSEC_PER_SEC * (clk_div + 1);
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 	period = div64_u64(rate * period_ns, div);
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@@ -106,14 +114,17 @@
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 	high_width = div64_u64(rate * duty_ns, div);
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 	value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
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-	err = clk_enable(mdp->clk_main);
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-	if (err < 0)
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-		return err;
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-
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-	err = clk_enable(mdp->clk_mm);
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-	if (err < 0) {
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-		clk_disable(mdp->clk_main);
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-		return err;
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+	if (mdp->data->bls_debug && !mdp->data->has_commit) {
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+		/*
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+		 * For MT2701, disable double buffer before writing register
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+		 * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
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+		 */
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+		mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
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+					 mdp->data->bls_debug_mask,
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+					 mdp->data->bls_debug_mask);
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+		mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
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+					 mdp->data->con0_sel,
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+					 mdp->data->con0_sel);
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 	}
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 	mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
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@@ -132,8 +143,8 @@
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 					 0x0);
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 	}
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-	clk_disable(mdp->clk_mm);
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-	clk_disable(mdp->clk_main);
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+	clk_disable_unprepare(mdp->clk_mm);
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+	clk_disable_unprepare(mdp->clk_main);
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 	return 0;
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 }
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@@ -143,13 +154,16 @@
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 	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
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 	int err;
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-	err = clk_enable(mdp->clk_main);
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-	if (err < 0)
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-		return err;
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-
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-	err = clk_enable(mdp->clk_mm);
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+	err = clk_prepare_enable(mdp->clk_main);
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 	if (err < 0) {
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-		clk_disable(mdp->clk_main);
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+		dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
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+		return err;
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+	}
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+
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+	err = clk_prepare_enable(mdp->clk_mm);
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+	if (err < 0) {
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+		dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
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+		clk_disable_unprepare(mdp->clk_main);
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 		return err;
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 	}
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@@ -166,8 +180,8 @@
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 	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
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 				 0x0);
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-	clk_disable(mdp->clk_mm);
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-	clk_disable(mdp->clk_main);
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+	clk_disable_unprepare(mdp->clk_mm);
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+	clk_disable_unprepare(mdp->clk_main);
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 }
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 static const struct pwm_ops mtk_disp_pwm_ops = {
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@@ -202,14 +216,6 @@
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 	if (IS_ERR(mdp->clk_mm))
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 		return PTR_ERR(mdp->clk_mm);
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218
 
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-	ret = clk_prepare(mdp->clk_main);
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-	if (ret < 0)
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-		return ret;
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-
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-	ret = clk_prepare(mdp->clk_mm);
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-	if (ret < 0)
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-		goto disable_clk_main;
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-
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 	mdp->chip.dev = &pdev->dev;
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 	mdp->chip.ops = &mtk_disp_pwm_ops;
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 	mdp->chip.base = -1;
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@@ -217,44 +223,22 @@
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 	ret = pwmchip_add(&mdp->chip);
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 	if (ret < 0) {
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-		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
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-		goto disable_clk_mm;
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+		dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret));
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+		return ret;
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 	}
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 	platform_set_drvdata(pdev, mdp);
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231
 
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-	/*
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-	 * For MT2701, disable double buffer before writing register
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-	 * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
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-	 */
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-	if (!mdp->data->has_commit) {
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-		mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
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-					 mdp->data->bls_debug_mask,
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-					 mdp->data->bls_debug_mask);
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-		mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
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-					 mdp->data->con0_sel,
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-					 mdp->data->con0_sel);
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-	}
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-
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 	return 0;
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-
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-disable_clk_mm:
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-	clk_unprepare(mdp->clk_mm);
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-disable_clk_main:
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-	clk_unprepare(mdp->clk_main);
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-	return ret;
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 }
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 static int mtk_disp_pwm_remove(struct platform_device *pdev)
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 {
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 	struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
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-	int ret;
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-	ret = pwmchip_remove(&mdp->chip);
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-	clk_unprepare(mdp->clk_mm);
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-	clk_unprepare(mdp->clk_main);
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+	pwmchip_remove(&mdp->chip);
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-	return ret;
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+	return 0;
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 }
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 static const struct mtk_pwm_data mt2701_pwm_data = {
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@@ -277,10 +261,21 @@
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 	.commit_mask = 0x1,
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 };
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+static const struct mtk_pwm_data mt8183_pwm_data = {
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+	.enable_mask = BIT(0),
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+	.con0 = 0x18,
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+	.con0_sel = 0x0,
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+	.con1 = 0x1c,
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+	.has_commit = false,
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+	.bls_debug = 0x80,
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+	.bls_debug_mask = 0x3,
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+};
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+
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 static const struct of_device_id mtk_disp_pwm_of_match[] = {
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 	{ .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
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 	{ .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
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 	{ .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
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+	{ .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
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 	{ }
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 };
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 MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);