write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/pwm/pwm-lpc32xx.c
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@@ -1,10 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; version 2.
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- *
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  */
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 #include <linux/clk.h>
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@@ -55,10 +51,10 @@
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 	if (duty_cycles > 255)
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 		duty_cycles = 255;
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-	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
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+	val = readl(lpc32xx->base);
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 	val &= ~0xFFFF;
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 	val |= (period_cycles << 8) | duty_cycles;
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-	writel(val, lpc32xx->base + (pwm->hwpwm << 2));
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+	writel(val, lpc32xx->base);
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 	return 0;
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 }
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@@ -73,9 +69,9 @@
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 	if (ret)
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 		return ret;
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-	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
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+	val = readl(lpc32xx->base);
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 	val |= PWM_ENABLE;
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-	writel(val, lpc32xx->base + (pwm->hwpwm << 2));
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+	writel(val, lpc32xx->base);
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 	return 0;
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 }
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@@ -85,9 +81,9 @@
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 	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
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 	u32 val;
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-	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
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+	val = readl(lpc32xx->base);
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 	val &= ~PWM_ENABLE;
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-	writel(val, lpc32xx->base + (pwm->hwpwm << 2));
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+	writel(val, lpc32xx->base);
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 	clk_disable_unprepare(lpc32xx->clk);
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 }
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@@ -125,9 +121,9 @@
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 	lpc32xx->chip.base = -1;
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 	/* If PWM is disabled, configure the output to the default value */
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-	val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
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+	val = readl(lpc32xx->base);
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 	val &= ~PWM_PIN_LEVEL;
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-	writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
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+	writel(val, lpc32xx->base);
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 	ret = pwmchip_add(&lpc32xx->chip);
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 	if (ret < 0) {