~hc/RK356X_SDK_RELEASE.git

..	..	@@ -25,6 +25,23 @@
25	25	#include "pinconf.h"
26	26	#include "pinmux.h"
27	27
	28	+#define ocelot_clrsetbits(addr, clear, set) \
	29	+ writel((readl(addr) & ~(clear)) \| (set), (addr))
	30	+
	31	+/* PINCONFIG bits (sparx5 only) */
	32	+enum {
	33	+ PINCONF_BIAS,
	34	+ PINCONF_SCHMITT,
	35	+ PINCONF_DRIVE_STRENGTH,
	36	+};
	37	+
	38	+#define BIAS_PD_BIT BIT(4)
	39	+#define BIAS_PU_BIT BIT(3)
	40	+#define BIAS_BITS (BIAS_PD_BIT\|BIAS_PU_BIT)
	41	+#define SCHMITT_BIT BIT(2)
	42	+#define DRIVE_BITS GENMASK(1, 0)
	43	+
	44	+/* GPIO standard registers */
28	45	#define OCELOT_GPIO_OUT_SET 0x0
29	46	#define OCELOT_GPIO_OUT_CLR 0x4
30	47	#define OCELOT_GPIO_OUT 0x8
..	..	@@ -37,70 +54,87 @@
37	54	#define OCELOT_GPIO_ALT1 0x24
38	55	#define OCELOT_GPIO_SD_MAP 0x28
39	56
40		-#define OCELOT_PINS 22
41	57	#define OCELOT_FUNC_PER_PIN 4
42	58
43	59	enum {
44	60	FUNC_NONE,
45	61	FUNC_GPIO,
	62	+ FUNC_IRQ0,
46	63	FUNC_IRQ0_IN,
47	64	FUNC_IRQ0_OUT,
	65	+ FUNC_IRQ1,
48	66	FUNC_IRQ1_IN,
49	67	FUNC_IRQ1_OUT,
50		- FUNC_MIIM1,
	68	+ FUNC_EXT_IRQ,
	69	+ FUNC_MIIM,
	70	+ FUNC_PHY_LED,
51	71	FUNC_PCI_WAKE,
	72	+ FUNC_MD,
52	73	FUNC_PTP0,
53	74	FUNC_PTP1,
54	75	FUNC_PTP2,
55	76	FUNC_PTP3,
56	77	FUNC_PWM,
57		- FUNC_RECO_CLK0,
58		- FUNC_RECO_CLK1,
59		- FUNC_SFP0,
60		- FUNC_SFP1,
61		- FUNC_SFP2,
62		- FUNC_SFP3,
63		- FUNC_SFP4,
64		- FUNC_SFP5,
	78	+ FUNC_RECO_CLK,
	79	+ FUNC_SFP,
65	80	FUNC_SG0,
	81	+ FUNC_SG1,
	82	+ FUNC_SG2,
66	83	FUNC_SI,
	84	+ FUNC_SI2,
67	85	FUNC_TACHO,
68	86	FUNC_TWI,
	87	+ FUNC_TWI2,
	88	+ FUNC_TWI3,
69	89	FUNC_TWI_SCL_M,
70	90	FUNC_UART,
71	91	FUNC_UART2,
	92	+ FUNC_UART3,
	93	+ FUNC_PLL_STAT,
	94	+ FUNC_EMMC,
	95	+ FUNC_REF_CLK,
	96	+ FUNC_RCVRD_CLK,
72	97	FUNC_MAX
73	98	};
74	99
75	100	static const char *const ocelot_function_names[] = {
76	101	[FUNC_NONE] = "none",
77	102	[FUNC_GPIO] = "gpio",
	103	+ [FUNC_IRQ0] = "irq0",
78	104	[FUNC_IRQ0_IN] = "irq0_in",
79	105	[FUNC_IRQ0_OUT] = "irq0_out",
	106	+ [FUNC_IRQ1] = "irq1",
80	107	[FUNC_IRQ1_IN] = "irq1_in",
81	108	[FUNC_IRQ1_OUT] = "irq1_out",
82		- [FUNC_MIIM1] = "miim1",
	109	+ [FUNC_EXT_IRQ] = "ext_irq",
	110	+ [FUNC_MIIM] = "miim",
	111	+ [FUNC_PHY_LED] = "phy_led",
83	112	[FUNC_PCI_WAKE] = "pci_wake",
	113	+ [FUNC_MD] = "md",
84	114	[FUNC_PTP0] = "ptp0",
85	115	[FUNC_PTP1] = "ptp1",
86	116	[FUNC_PTP2] = "ptp2",
87	117	[FUNC_PTP3] = "ptp3",
88	118	[FUNC_PWM] = "pwm",
89		- [FUNC_RECO_CLK0] = "reco_clk0",
90		- [FUNC_RECO_CLK1] = "reco_clk1",
91		- [FUNC_SFP0] = "sfp0",
92		- [FUNC_SFP1] = "sfp1",
93		- [FUNC_SFP2] = "sfp2",
94		- [FUNC_SFP3] = "sfp3",
95		- [FUNC_SFP4] = "sfp4",
96		- [FUNC_SFP5] = "sfp5",
	119	+ [FUNC_RECO_CLK] = "reco_clk",
	120	+ [FUNC_SFP] = "sfp",
97	121	[FUNC_SG0] = "sg0",
	122	+ [FUNC_SG1] = "sg1",
	123	+ [FUNC_SG2] = "sg2",
98	124	[FUNC_SI] = "si",
	125	+ [FUNC_SI2] = "si2",
99	126	[FUNC_TACHO] = "tacho",
100	127	[FUNC_TWI] = "twi",
	128	+ [FUNC_TWI2] = "twi2",
	129	+ [FUNC_TWI3] = "twi3",
101	130	[FUNC_TWI_SCL_M] = "twi_scl_m",
102	131	[FUNC_UART] = "uart",
103	132	[FUNC_UART2] = "uart2",
	133	+ [FUNC_UART3] = "uart3",
	134	+ [FUNC_PLL_STAT] = "pll_stat",
	135	+ [FUNC_EMMC] = "emmc",
	136	+ [FUNC_REF_CLK] = "ref_clk",
	137	+ [FUNC_RCVRD_CLK] = "rcvrd_clk",
104	138	};
105	139
106	140	struct ocelot_pmx_func {
..	..	@@ -118,7 +152,10 @@
118	152	struct pinctrl_dev *pctl;
119	153	struct gpio_chip gpio_chip;
120	154	struct regmap *map;
	155	+ void __iomem *pincfg;
	156	+ struct pinctrl_desc *desc;
121	157	struct ocelot_pmx_func func[FUNC_MAX];
	158	+ u8 stride;
122	159	};
123	160
124	161	#define OCELOT_P(p, f0, f1, f2) \
..	..	@@ -139,18 +176,18 @@
139	176	OCELOT_P(7, UART, TWI_SCL_M, NONE);
140	177	OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
141	178	OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
142		-OCELOT_P(10, PTP2, TWI_SCL_M, SFP0);
143		-OCELOT_P(11, PTP3, TWI_SCL_M, SFP1);
144		-OCELOT_P(12, UART2, TWI_SCL_M, SFP2);
145		-OCELOT_P(13, UART2, TWI_SCL_M, SFP3);
146		-OCELOT_P(14, MIIM1, TWI_SCL_M, SFP4);
147		-OCELOT_P(15, MIIM1, TWI_SCL_M, SFP5);
	179	+OCELOT_P(10, PTP2, TWI_SCL_M, SFP);
	180	+OCELOT_P(11, PTP3, TWI_SCL_M, SFP);
	181	+OCELOT_P(12, UART2, TWI_SCL_M, SFP);
	182	+OCELOT_P(13, UART2, TWI_SCL_M, SFP);
	183	+OCELOT_P(14, MIIM, TWI_SCL_M, SFP);
	184	+OCELOT_P(15, MIIM, TWI_SCL_M, SFP);
148	185	OCELOT_P(16, TWI, NONE, SI);
149	186	OCELOT_P(17, TWI, TWI_SCL_M, SI);
150	187	OCELOT_P(18, PTP0, TWI_SCL_M, NONE);
151	188	OCELOT_P(19, PTP1, TWI_SCL_M, NONE);
152		-OCELOT_P(20, RECO_CLK0, TACHO, NONE);
153		-OCELOT_P(21, RECO_CLK1, PWM, NONE);
	189	+OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M);
	190	+OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M);
154	191
155	192	#define OCELOT_PIN(n) { \
156	193	.number = n, \
..	..	@@ -183,6 +220,298 @@
183	220	OCELOT_PIN(21),
184	221	};
185	222
	223	+#define JAGUAR2_P(p, f0, f1) \
	224	+static struct ocelot_pin_caps jaguar2_pin_##p = { \
	225	+ .pin = p, \
	226	+ .functions = { \
	227	+ FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
	228	+ }, \
	229	+}
	230	+
	231	+JAGUAR2_P(0, SG0, NONE);
	232	+JAGUAR2_P(1, SG0, NONE);
	233	+JAGUAR2_P(2, SG0, NONE);
	234	+JAGUAR2_P(3, SG0, NONE);
	235	+JAGUAR2_P(4, SG1, NONE);
	236	+JAGUAR2_P(5, SG1, NONE);
	237	+JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT);
	238	+JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT);
	239	+JAGUAR2_P(8, PTP0, NONE);
	240	+JAGUAR2_P(9, PTP1, NONE);
	241	+JAGUAR2_P(10, UART, NONE);
	242	+JAGUAR2_P(11, UART, NONE);
	243	+JAGUAR2_P(12, SG1, NONE);
	244	+JAGUAR2_P(13, SG1, NONE);
	245	+JAGUAR2_P(14, TWI, TWI_SCL_M);
	246	+JAGUAR2_P(15, TWI, NONE);
	247	+JAGUAR2_P(16, SI, TWI_SCL_M);
	248	+JAGUAR2_P(17, SI, TWI_SCL_M);
	249	+JAGUAR2_P(18, SI, TWI_SCL_M);
	250	+JAGUAR2_P(19, PCI_WAKE, NONE);
	251	+JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M);
	252	+JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M);
	253	+JAGUAR2_P(22, TACHO, NONE);
	254	+JAGUAR2_P(23, PWM, NONE);
	255	+JAGUAR2_P(24, UART2, NONE);
	256	+JAGUAR2_P(25, UART2, SI);
	257	+JAGUAR2_P(26, PTP2, SI);
	258	+JAGUAR2_P(27, PTP3, SI);
	259	+JAGUAR2_P(28, TWI2, SI);
	260	+JAGUAR2_P(29, TWI2, SI);
	261	+JAGUAR2_P(30, SG2, SI);
	262	+JAGUAR2_P(31, SG2, SI);
	263	+JAGUAR2_P(32, SG2, SI);
	264	+JAGUAR2_P(33, SG2, SI);
	265	+JAGUAR2_P(34, NONE, TWI_SCL_M);
	266	+JAGUAR2_P(35, NONE, TWI_SCL_M);
	267	+JAGUAR2_P(36, NONE, TWI_SCL_M);
	268	+JAGUAR2_P(37, NONE, TWI_SCL_M);
	269	+JAGUAR2_P(38, NONE, TWI_SCL_M);
	270	+JAGUAR2_P(39, NONE, TWI_SCL_M);
	271	+JAGUAR2_P(40, NONE, TWI_SCL_M);
	272	+JAGUAR2_P(41, NONE, TWI_SCL_M);
	273	+JAGUAR2_P(42, NONE, TWI_SCL_M);
	274	+JAGUAR2_P(43, NONE, TWI_SCL_M);
	275	+JAGUAR2_P(44, NONE, SFP);
	276	+JAGUAR2_P(45, NONE, SFP);
	277	+JAGUAR2_P(46, NONE, SFP);
	278	+JAGUAR2_P(47, NONE, SFP);
	279	+JAGUAR2_P(48, SFP, NONE);
	280	+JAGUAR2_P(49, SFP, SI);
	281	+JAGUAR2_P(50, SFP, SI);
	282	+JAGUAR2_P(51, SFP, SI);
	283	+JAGUAR2_P(52, SFP, NONE);
	284	+JAGUAR2_P(53, SFP, NONE);
	285	+JAGUAR2_P(54, SFP, NONE);
	286	+JAGUAR2_P(55, SFP, NONE);
	287	+JAGUAR2_P(56, MIIM, SFP);
	288	+JAGUAR2_P(57, MIIM, SFP);
	289	+JAGUAR2_P(58, MIIM, SFP);
	290	+JAGUAR2_P(59, MIIM, SFP);
	291	+JAGUAR2_P(60, NONE, NONE);
	292	+JAGUAR2_P(61, NONE, NONE);
	293	+JAGUAR2_P(62, NONE, NONE);
	294	+JAGUAR2_P(63, NONE, NONE);
	295	+
	296	+#define JAGUAR2_PIN(n) { \
	297	+ .number = n, \
	298	+ .name = "GPIO_"#n, \
	299	+ .drv_data = &jaguar2_pin_##n \
	300	+}
	301	+
	302	+static const struct pinctrl_pin_desc jaguar2_pins[] = {
	303	+ JAGUAR2_PIN(0),
	304	+ JAGUAR2_PIN(1),
	305	+ JAGUAR2_PIN(2),
	306	+ JAGUAR2_PIN(3),
	307	+ JAGUAR2_PIN(4),
	308	+ JAGUAR2_PIN(5),
	309	+ JAGUAR2_PIN(6),
	310	+ JAGUAR2_PIN(7),
	311	+ JAGUAR2_PIN(8),
	312	+ JAGUAR2_PIN(9),
	313	+ JAGUAR2_PIN(10),
	314	+ JAGUAR2_PIN(11),
	315	+ JAGUAR2_PIN(12),
	316	+ JAGUAR2_PIN(13),
	317	+ JAGUAR2_PIN(14),
	318	+ JAGUAR2_PIN(15),
	319	+ JAGUAR2_PIN(16),
	320	+ JAGUAR2_PIN(17),
	321	+ JAGUAR2_PIN(18),
	322	+ JAGUAR2_PIN(19),
	323	+ JAGUAR2_PIN(20),
	324	+ JAGUAR2_PIN(21),
	325	+ JAGUAR2_PIN(22),
	326	+ JAGUAR2_PIN(23),
	327	+ JAGUAR2_PIN(24),
	328	+ JAGUAR2_PIN(25),
	329	+ JAGUAR2_PIN(26),
	330	+ JAGUAR2_PIN(27),
	331	+ JAGUAR2_PIN(28),
	332	+ JAGUAR2_PIN(29),
	333	+ JAGUAR2_PIN(30),
	334	+ JAGUAR2_PIN(31),
	335	+ JAGUAR2_PIN(32),
	336	+ JAGUAR2_PIN(33),
	337	+ JAGUAR2_PIN(34),
	338	+ JAGUAR2_PIN(35),
	339	+ JAGUAR2_PIN(36),
	340	+ JAGUAR2_PIN(37),
	341	+ JAGUAR2_PIN(38),
	342	+ JAGUAR2_PIN(39),
	343	+ JAGUAR2_PIN(40),
	344	+ JAGUAR2_PIN(41),
	345	+ JAGUAR2_PIN(42),
	346	+ JAGUAR2_PIN(43),
	347	+ JAGUAR2_PIN(44),
	348	+ JAGUAR2_PIN(45),
	349	+ JAGUAR2_PIN(46),
	350	+ JAGUAR2_PIN(47),
	351	+ JAGUAR2_PIN(48),
	352	+ JAGUAR2_PIN(49),
	353	+ JAGUAR2_PIN(50),
	354	+ JAGUAR2_PIN(51),
	355	+ JAGUAR2_PIN(52),
	356	+ JAGUAR2_PIN(53),
	357	+ JAGUAR2_PIN(54),
	358	+ JAGUAR2_PIN(55),
	359	+ JAGUAR2_PIN(56),
	360	+ JAGUAR2_PIN(57),
	361	+ JAGUAR2_PIN(58),
	362	+ JAGUAR2_PIN(59),
	363	+ JAGUAR2_PIN(60),
	364	+ JAGUAR2_PIN(61),
	365	+ JAGUAR2_PIN(62),
	366	+ JAGUAR2_PIN(63),
	367	+};
	368	+
	369	+#define SPARX5_P(p, f0, f1, f2) \
	370	+static struct ocelot_pin_caps sparx5_pin_##p = { \
	371	+ .pin = p, \
	372	+ .functions = { \
	373	+ FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
	374	+ }, \
	375	+}
	376	+
	377	+SPARX5_P(0, SG0, PLL_STAT, NONE);
	378	+SPARX5_P(1, SG0, NONE, NONE);
	379	+SPARX5_P(2, SG0, NONE, NONE);
	380	+SPARX5_P(3, SG0, NONE, NONE);
	381	+SPARX5_P(4, SG1, NONE, NONE);
	382	+SPARX5_P(5, SG1, NONE, NONE);
	383	+SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP);
	384	+SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP);
	385	+SPARX5_P(8, PTP0, NONE, SFP);
	386	+SPARX5_P(9, PTP1, SFP, TWI_SCL_M);
	387	+SPARX5_P(10, UART, NONE, NONE);
	388	+SPARX5_P(11, UART, NONE, NONE);
	389	+SPARX5_P(12, SG1, NONE, NONE);
	390	+SPARX5_P(13, SG1, NONE, NONE);
	391	+SPARX5_P(14, TWI, TWI_SCL_M, NONE);
	392	+SPARX5_P(15, TWI, NONE, NONE);
	393	+SPARX5_P(16, SI, TWI_SCL_M, SFP);
	394	+SPARX5_P(17, SI, TWI_SCL_M, SFP);
	395	+SPARX5_P(18, SI, TWI_SCL_M, SFP);
	396	+SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP);
	397	+SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP);
	398	+SPARX5_P(21, IRQ1_OUT, TACHO, SFP);
	399	+SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M);
	400	+SPARX5_P(23, PWM, UART3, TWI_SCL_M);
	401	+SPARX5_P(24, PTP2, UART3, TWI_SCL_M);
	402	+SPARX5_P(25, PTP3, SI, TWI_SCL_M);
	403	+SPARX5_P(26, UART2, SI, TWI_SCL_M);
	404	+SPARX5_P(27, UART2, SI, TWI_SCL_M);
	405	+SPARX5_P(28, TWI2, SI, SFP);
	406	+SPARX5_P(29, TWI2, SI, SFP);
	407	+SPARX5_P(30, SG2, SI, PWM);
	408	+SPARX5_P(31, SG2, SI, TWI_SCL_M);
	409	+SPARX5_P(32, SG2, SI, TWI_SCL_M);
	410	+SPARX5_P(33, SG2, SI, SFP);
	411	+SPARX5_P(34, NONE, TWI_SCL_M, EMMC);
	412	+SPARX5_P(35, SFP, TWI_SCL_M, EMMC);
	413	+SPARX5_P(36, SFP, TWI_SCL_M, EMMC);
	414	+SPARX5_P(37, SFP, NONE, EMMC);
	415	+SPARX5_P(38, NONE, TWI_SCL_M, EMMC);
	416	+SPARX5_P(39, SI2, TWI_SCL_M, EMMC);
	417	+SPARX5_P(40, SI2, TWI_SCL_M, EMMC);
	418	+SPARX5_P(41, SI2, TWI_SCL_M, EMMC);
	419	+SPARX5_P(42, SI2, TWI_SCL_M, EMMC);
	420	+SPARX5_P(43, SI2, TWI_SCL_M, EMMC);
	421	+SPARX5_P(44, SI, SFP, EMMC);
	422	+SPARX5_P(45, SI, SFP, EMMC);
	423	+SPARX5_P(46, NONE, SFP, EMMC);
	424	+SPARX5_P(47, NONE, SFP, EMMC);
	425	+SPARX5_P(48, TWI3, SI, SFP);
	426	+SPARX5_P(49, TWI3, NONE, SFP);
	427	+SPARX5_P(50, SFP, NONE, TWI_SCL_M);
	428	+SPARX5_P(51, SFP, SI, TWI_SCL_M);
	429	+SPARX5_P(52, SFP, MIIM, TWI_SCL_M);
	430	+SPARX5_P(53, SFP, MIIM, TWI_SCL_M);
	431	+SPARX5_P(54, SFP, PTP2, TWI_SCL_M);
	432	+SPARX5_P(55, SFP, PTP3, PCI_WAKE);
	433	+SPARX5_P(56, MIIM, SFP, TWI_SCL_M);
	434	+SPARX5_P(57, MIIM, SFP, TWI_SCL_M);
	435	+SPARX5_P(58, MIIM, SFP, TWI_SCL_M);
	436	+SPARX5_P(59, MIIM, SFP, NONE);
	437	+SPARX5_P(60, RECO_CLK, NONE, NONE);
	438	+SPARX5_P(61, RECO_CLK, NONE, NONE);
	439	+SPARX5_P(62, RECO_CLK, PLL_STAT, NONE);
	440	+SPARX5_P(63, RECO_CLK, NONE, NONE);
	441	+
	442	+#define SPARX5_PIN(n) { \
	443	+ .number = n, \
	444	+ .name = "GPIO_"#n, \
	445	+ .drv_data = &sparx5_pin_##n \
	446	+}
	447	+
	448	+static const struct pinctrl_pin_desc sparx5_pins[] = {
	449	+ SPARX5_PIN(0),
	450	+ SPARX5_PIN(1),
	451	+ SPARX5_PIN(2),
	452	+ SPARX5_PIN(3),
	453	+ SPARX5_PIN(4),
	454	+ SPARX5_PIN(5),
	455	+ SPARX5_PIN(6),
	456	+ SPARX5_PIN(7),
	457	+ SPARX5_PIN(8),
	458	+ SPARX5_PIN(9),
	459	+ SPARX5_PIN(10),
	460	+ SPARX5_PIN(11),
	461	+ SPARX5_PIN(12),
	462	+ SPARX5_PIN(13),
	463	+ SPARX5_PIN(14),
	464	+ SPARX5_PIN(15),
	465	+ SPARX5_PIN(16),
	466	+ SPARX5_PIN(17),
	467	+ SPARX5_PIN(18),
	468	+ SPARX5_PIN(19),
	469	+ SPARX5_PIN(20),
	470	+ SPARX5_PIN(21),
	471	+ SPARX5_PIN(22),
	472	+ SPARX5_PIN(23),
	473	+ SPARX5_PIN(24),
	474	+ SPARX5_PIN(25),
	475	+ SPARX5_PIN(26),
	476	+ SPARX5_PIN(27),
	477	+ SPARX5_PIN(28),
	478	+ SPARX5_PIN(29),
	479	+ SPARX5_PIN(30),
	480	+ SPARX5_PIN(31),
	481	+ SPARX5_PIN(32),
	482	+ SPARX5_PIN(33),
	483	+ SPARX5_PIN(34),
	484	+ SPARX5_PIN(35),
	485	+ SPARX5_PIN(36),
	486	+ SPARX5_PIN(37),
	487	+ SPARX5_PIN(38),
	488	+ SPARX5_PIN(39),
	489	+ SPARX5_PIN(40),
	490	+ SPARX5_PIN(41),
	491	+ SPARX5_PIN(42),
	492	+ SPARX5_PIN(43),
	493	+ SPARX5_PIN(44),
	494	+ SPARX5_PIN(45),
	495	+ SPARX5_PIN(46),
	496	+ SPARX5_PIN(47),
	497	+ SPARX5_PIN(48),
	498	+ SPARX5_PIN(49),
	499	+ SPARX5_PIN(50),
	500	+ SPARX5_PIN(51),
	501	+ SPARX5_PIN(52),
	502	+ SPARX5_PIN(53),
	503	+ SPARX5_PIN(54),
	504	+ SPARX5_PIN(55),
	505	+ SPARX5_PIN(56),
	506	+ SPARX5_PIN(57),
	507	+ SPARX5_PIN(58),
	508	+ SPARX5_PIN(59),
	509	+ SPARX5_PIN(60),
	510	+ SPARX5_PIN(61),
	511	+ SPARX5_PIN(62),
	512	+ SPARX5_PIN(63),
	513	+};
	514	+
186	515	static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
187	516	{
188	517	return ARRAY_SIZE(ocelot_function_names);
..	..	@@ -207,9 +536,10 @@
207	536	return 0;
208	537	}
209	538
210		-static int ocelot_pin_function_idx(unsigned int pin, unsigned int function)
	539	+static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
	540	+ unsigned int pin, unsigned int function)
211	541	{
212		- struct ocelot_pin_caps *p = ocelot_pins[pin].drv_data;
	542	+ struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
213	543	int i;
214	544
215	545	for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
..	..	@@ -220,40 +550,47 @@
220	550	return -1;
221	551	}
222	552
	553	+#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
	554	+
223	555	static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
224	556	unsigned int selector, unsigned int group)
225	557	{
226	558	struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
227		- struct ocelot_pin_caps *pin = ocelot_pins[group].drv_data;
	559	+ struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
	560	+ unsigned int p = pin->pin % 32;
228	561	int f;
229	562
230		- f = ocelot_pin_function_idx(group, selector);
	563	+ f = ocelot_pin_function_idx(info, group, selector);
231	564	if (f < 0)
232	565	return -EINVAL;
233	566
234	567	/*
235	568	* f is encoded on two bits.
236		- * bit 0 of f goes in BIT(pin) of ALT0, bit 1 of f goes in BIT(pin) of
237		- * ALT1
	569	+ * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
	570	+ * ALT[1]
238	571	* This is racy because both registers can't be updated at the same time
239	572	* but it doesn't matter much for now.
	573	+ * Note: ALT0/ALT1 are organized specially for 64 gpio targets
240	574	*/
241		- regmap_update_bits(info->map, OCELOT_GPIO_ALT0, BIT(pin->pin),
242		- f << pin->pin);
243		- regmap_update_bits(info->map, OCELOT_GPIO_ALT1, BIT(pin->pin),
244		- f << (pin->pin - 1));
	575	+ regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
	576	+ BIT(p), f << p);
	577	+ regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
	578	+ BIT(p), (f >> 1) << p);
245	579
246	580	return 0;
247	581	}
	582	+
	583	+#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
248	584
249	585	static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
250	586	struct pinctrl_gpio_range *range,
251	587	unsigned int pin, bool input)
252	588	{
253	589	struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	590	+ unsigned int p = pin % 32;
254	591
255		- regmap_update_bits(info->map, OCELOT_GPIO_OE, BIT(pin),
256		- input ? 0 : BIT(pin));
	592	+ regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
	593	+ input ? 0 : BIT(p));
257	594
258	595	return 0;
259	596	}
..	..	@@ -263,9 +600,12 @@
263	600	unsigned int offset)
264	601	{
265	602	struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	603	+ unsigned int p = offset % 32;
266	604
267		- regmap_update_bits(info->map, OCELOT_GPIO_ALT0, BIT(offset), 0);
268		- regmap_update_bits(info->map, OCELOT_GPIO_ALT1, BIT(offset), 0);
	605	+ regmap_update_bits(info->map, REG_ALT(0, info, offset),
	606	+ BIT(p), 0);
	607	+ regmap_update_bits(info->map, REG_ALT(1, info, offset),
	608	+ BIT(p), 0);
269	609
270	610	return 0;
271	611	}
..	..	@@ -281,13 +621,17 @@
281	621
282	622	static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
283	623	{
284		- return ARRAY_SIZE(ocelot_pins);
	624	+ struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	625	+
	626	+ return info->desc->npins;
285	627	}
286	628
287	629	static const char ocelot_pctl_get_group_name(struct pinctrl_dev pctldev,
288	630	unsigned int group)
289	631	{
290		- return ocelot_pins[group].name;
	632	+ struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	633	+
	634	+ return info->desc->pins[group].name;
291	635	}
292	636
293	637	static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
..	..	@@ -295,11 +639,226 @@
295	639	const unsigned int **pins,
296	640	unsigned int *num_pins)
297	641	{
298		- *pins = &ocelot_pins[group].number;
	642	+ struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	643	+
	644	+ *pins = &info->desc->pins[group].number;
299	645	*num_pins = 1;
300	646
301	647	return 0;
302	648	}
	649	+
	650	+static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
	651	+ unsigned int pin,
	652	+ unsigned int reg,
	653	+ int *val)
	654	+{
	655	+ int ret = -EOPNOTSUPP;
	656	+
	657	+ if (info->pincfg) {
	658	+ u32 regcfg = readl(info->pincfg + (pin * sizeof(u32)));
	659	+
	660	+ ret = 0;
	661	+ switch (reg) {
	662	+ case PINCONF_BIAS:
	663	+ *val = regcfg & BIAS_BITS;
	664	+ break;
	665	+
	666	+ case PINCONF_SCHMITT:
	667	+ *val = regcfg & SCHMITT_BIT;
	668	+ break;
	669	+
	670	+ case PINCONF_DRIVE_STRENGTH:
	671	+ *val = regcfg & DRIVE_BITS;
	672	+ break;
	673	+
	674	+ default:
	675	+ ret = -EOPNOTSUPP;
	676	+ break;
	677	+ }
	678	+ }
	679	+ return ret;
	680	+}
	681	+
	682	+static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
	683	+ unsigned int pin,
	684	+ unsigned int reg,
	685	+ int val)
	686	+{
	687	+ int ret = -EOPNOTSUPP;
	688	+
	689	+ if (info->pincfg) {
	690	+ void __iomem regaddr = info->pincfg + (pin sizeof(u32));
	691	+
	692	+ ret = 0;
	693	+ switch (reg) {
	694	+ case PINCONF_BIAS:
	695	+ ocelot_clrsetbits(regaddr, BIAS_BITS, val);
	696	+ break;
	697	+
	698	+ case PINCONF_SCHMITT:
	699	+ ocelot_clrsetbits(regaddr, SCHMITT_BIT, val);
	700	+ break;
	701	+
	702	+ case PINCONF_DRIVE_STRENGTH:
	703	+ if (val <= 3)
	704	+ ocelot_clrsetbits(regaddr, DRIVE_BITS, val);
	705	+ else
	706	+ ret = -EINVAL;
	707	+ break;
	708	+
	709	+ default:
	710	+ ret = -EOPNOTSUPP;
	711	+ break;
	712	+ }
	713	+ }
	714	+ return ret;
	715	+}
	716	+
	717	+static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,
	718	+ unsigned int pin, unsigned long *config)
	719	+{
	720	+ struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	721	+ u32 param = pinconf_to_config_param(*config);
	722	+ int val, err;
	723	+
	724	+ switch (param) {
	725	+ case PIN_CONFIG_BIAS_DISABLE:
	726	+ case PIN_CONFIG_BIAS_PULL_UP:
	727	+ case PIN_CONFIG_BIAS_PULL_DOWN:
	728	+ err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val);
	729	+ if (err)
	730	+ return err;
	731	+ if (param == PIN_CONFIG_BIAS_DISABLE)
	732	+ val = (val == 0 ? true : false);
	733	+ else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
	734	+ val = (val & BIAS_PD_BIT ? true : false);
	735	+ else /* PIN_CONFIG_BIAS_PULL_UP */
	736	+ val = (val & BIAS_PU_BIT ? true : false);
	737	+ break;
	738	+
	739	+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
	740	+ err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val);
	741	+ if (err)
	742	+ return err;
	743	+
	744	+ val = (val & SCHMITT_BIT ? true : false);
	745	+ break;
	746	+
	747	+ case PIN_CONFIG_DRIVE_STRENGTH:
	748	+ err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH,
	749	+ &val);
	750	+ if (err)
	751	+ return err;
	752	+ break;
	753	+
	754	+ case PIN_CONFIG_OUTPUT:
	755	+ err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
	756	+ &val);
	757	+ if (err)
	758	+ return err;
	759	+ val = !!(val & BIT(pin % 32));
	760	+ break;
	761	+
	762	+ case PIN_CONFIG_INPUT_ENABLE:
	763	+ case PIN_CONFIG_OUTPUT_ENABLE:
	764	+ err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin),
	765	+ &val);
	766	+ if (err)
	767	+ return err;
	768	+ val = val & BIT(pin % 32);
	769	+ if (param == PIN_CONFIG_OUTPUT_ENABLE)
	770	+ val = !!val;
	771	+ else
	772	+ val = !val;
	773	+ break;
	774	+
	775	+ default:
	776	+ return -EOPNOTSUPP;
	777	+ }
	778	+
	779	+ *config = pinconf_to_config_packed(param, val);
	780	+
	781	+ return 0;
	782	+}
	783	+
	784	+static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
	785	+ unsigned long *configs, unsigned int num_configs)
	786	+{
	787	+ struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	788	+ u32 param, arg, p;
	789	+ int cfg, err = 0;
	790	+
	791	+ for (cfg = 0; cfg < num_configs; cfg++) {
	792	+ param = pinconf_to_config_param(configs[cfg]);
	793	+ arg = pinconf_to_config_argument(configs[cfg]);
	794	+
	795	+ switch (param) {
	796	+ case PIN_CONFIG_BIAS_DISABLE:
	797	+ case PIN_CONFIG_BIAS_PULL_UP:
	798	+ case PIN_CONFIG_BIAS_PULL_DOWN:
	799	+ arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
	800	+ (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT :
	801	+ BIAS_PD_BIT;
	802	+
	803	+ err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg);
	804	+ if (err)
	805	+ goto err;
	806	+
	807	+ break;
	808	+
	809	+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
	810	+ arg = arg ? SCHMITT_BIT : 0;
	811	+ err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT,
	812	+ arg);
	813	+ if (err)
	814	+ goto err;
	815	+
	816	+ break;
	817	+
	818	+ case PIN_CONFIG_DRIVE_STRENGTH:
	819	+ err = ocelot_hw_set_value(info, pin,
	820	+ PINCONF_DRIVE_STRENGTH,
	821	+ arg);
	822	+ if (err)
	823	+ goto err;
	824	+
	825	+ break;
	826	+
	827	+ case PIN_CONFIG_OUTPUT_ENABLE:
	828	+ case PIN_CONFIG_INPUT_ENABLE:
	829	+ case PIN_CONFIG_OUTPUT:
	830	+ p = pin % 32;
	831	+ if (arg)
	832	+ regmap_write(info->map,
	833	+ REG(OCELOT_GPIO_OUT_SET, info,
	834	+ pin),
	835	+ BIT(p));
	836	+ else
	837	+ regmap_write(info->map,
	838	+ REG(OCELOT_GPIO_OUT_CLR, info,
	839	+ pin),
	840	+ BIT(p));
	841	+ regmap_update_bits(info->map,
	842	+ REG(OCELOT_GPIO_OE, info, pin),
	843	+ BIT(p),
	844	+ param == PIN_CONFIG_INPUT_ENABLE ?
	845	+ 0 : BIT(p));
	846	+ break;
	847	+
	848	+ default:
	849	+ err = -EOPNOTSUPP;
	850	+ }
	851	+ }
	852	+err:
	853	+ return err;
	854	+}
	855	+
	856	+static const struct pinconf_ops ocelot_confops = {
	857	+ .is_generic = true,
	858	+ .pin_config_get = ocelot_pinconf_get,
	859	+ .pin_config_set = ocelot_pinconf_set,
	860	+ .pin_config_config_dbg_show = pinconf_generic_dump_config,
	861	+};
303	862
304	863	static const struct pinctrl_ops ocelot_pctl_ops = {
305	864	.get_groups_count = ocelot_pctl_get_groups_count,
..	..	@@ -318,29 +877,57 @@
318	877	.owner = THIS_MODULE,
319	878	};
320	879
	880	+static struct pinctrl_desc jaguar2_desc = {
	881	+ .name = "jaguar2-pinctrl",
	882	+ .pins = jaguar2_pins,
	883	+ .npins = ARRAY_SIZE(jaguar2_pins),
	884	+ .pctlops = &ocelot_pctl_ops,
	885	+ .pmxops = &ocelot_pmx_ops,
	886	+ .owner = THIS_MODULE,
	887	+};
	888	+
	889	+static struct pinctrl_desc sparx5_desc = {
	890	+ .name = "sparx5-pinctrl",
	891	+ .pins = sparx5_pins,
	892	+ .npins = ARRAY_SIZE(sparx5_pins),
	893	+ .pctlops = &ocelot_pctl_ops,
	894	+ .pmxops = &ocelot_pmx_ops,
	895	+ .confops = &ocelot_confops,
	896	+ .owner = THIS_MODULE,
	897	+};
	898	+
321	899	static int ocelot_create_group_func_map(struct device *dev,
322	900	struct ocelot_pinctrl *info)
323	901	{
324		- u16 pins[ARRAY_SIZE(ocelot_pins)];
325	902	int f, npins, i;
	903	+ u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
	904	+
	905	+ if (!pins)
	906	+ return -ENOMEM;
326	907
327	908	for (f = 0; f < FUNC_MAX; f++) {
328		- for (npins = 0, i = 0; i < ARRAY_SIZE(ocelot_pins); i++) {
329		- if (ocelot_pin_function_idx(i, f) >= 0)
	909	+ for (npins = 0, i = 0; i < info->desc->npins; i++) {
	910	+ if (ocelot_pin_function_idx(info, i, f) >= 0)
330	911	pins[npins++] = i;
331	912	}
332	913
	914	+ if (!npins)
	915	+ continue;
	916	+
333	917	info->func[f].ngroups = npins;
334		- info->func[f].groups = devm_kcalloc(dev,
335		- npins,
336		- sizeof(char *),
337		- GFP_KERNEL);
338		- if (!info->func[f].groups)
	918	+ info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *),
	919	+ GFP_KERNEL);
	920	+ if (!info->func[f].groups) {
	921	+ kfree(pins);
339	922	return -ENOMEM;
	923	+ }
340	924
341	925	for (i = 0; i < npins; i++)
342		- info->func[f].groups[i] = ocelot_pins[pins[i]].name;
	926	+ info->func[f].groups[i] =
	927	+ info->desc->pins[pins[i]].name;
343	928	}
	929	+
	930	+ kfree(pins);
344	931
345	932	return 0;
346	933	}
..	..	@@ -356,7 +943,7 @@
356	943	return ret;
357	944	}
358	945
359		- info->pctl = devm_pinctrl_register(&pdev->dev, &ocelot_desc, info);
	946	+ info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info);
360	947	if (IS_ERR(info->pctl)) {
361	948	dev_err(&pdev->dev, "Failed to register pinctrl\n");
362	949	return PTR_ERR(info->pctl);
..	..	@@ -370,9 +957,9 @@
370	957	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
371	958	unsigned int val;
372	959
373		- regmap_read(info->map, OCELOT_GPIO_IN, &val);
	960	+ regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val);
374	961
375		- return !!(val & BIT(offset));
	962	+ return !!(val & BIT(offset % 32));
376	963	}
377	964
378	965	static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
..	..	@@ -381,9 +968,11 @@
381	968	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
382	969
383	970	if (value)
384		- regmap_write(info->map, OCELOT_GPIO_OUT_SET, BIT(offset));
	971	+ regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
	972	+ BIT(offset % 32));
385	973	else
386		- regmap_write(info->map, OCELOT_GPIO_OUT_CLR, BIT(offset));
	974	+ regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
	975	+ BIT(offset % 32));
387	976	}
388	977
389	978	static int ocelot_gpio_get_direction(struct gpio_chip *chip,
..	..	@@ -392,9 +981,12 @@
392	981	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
393	982	unsigned int val;
394	983
395		- regmap_read(info->map, OCELOT_GPIO_OE, &val);
	984	+ regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val);
396	985
397		- return !(val & BIT(offset));
	986	+ if (val & BIT(offset % 32))
	987	+ return GPIO_LINE_DIRECTION_OUT;
	988	+
	989	+ return GPIO_LINE_DIRECTION_IN;
398	990	}
399	991
400	992	static int ocelot_gpio_direction_input(struct gpio_chip *chip,
..	..	@@ -407,12 +999,14 @@
407	999	unsigned int offset, int value)
408	1000	{
409	1001	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
410		- unsigned int pin = BIT(offset);
	1002	+ unsigned int pin = BIT(offset % 32);
411	1003
412	1004	if (value)
413		- regmap_write(info->map, OCELOT_GPIO_OUT_SET, pin);
	1005	+ regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
	1006	+ pin);
414	1007	else
415		- regmap_write(info->map, OCELOT_GPIO_OUT_CLR, pin);
	1008	+ regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
	1009	+ pin);
416	1010
417	1011	return pinctrl_gpio_direction_output(chip->base + offset);
418	1012	}
..	..	@@ -434,7 +1028,8 @@
434	1028	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
435	1029	unsigned int gpio = irqd_to_hwirq(data);
436	1030
437		- regmap_update_bits(info->map, OCELOT_GPIO_INTR_ENA, BIT(gpio), 0);
	1031	+ regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
	1032	+ BIT(gpio % 32), 0);
438	1033	}
439	1034
440	1035	static void ocelot_irq_unmask(struct irq_data *data)
..	..	@@ -443,8 +1038,8 @@
443	1038	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
444	1039	unsigned int gpio = irqd_to_hwirq(data);
445	1040
446		- regmap_update_bits(info->map, OCELOT_GPIO_INTR_ENA, BIT(gpio),
447		- BIT(gpio));
	1041	+ regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
	1042	+ BIT(gpio % 32), BIT(gpio % 32));
448	1043	}
449	1044
450	1045	static void ocelot_irq_ack(struct irq_data *data)
..	..	@@ -453,7 +1048,8 @@
453	1048	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
454	1049	unsigned int gpio = irqd_to_hwirq(data);
455	1050
456		- regmap_write_bits(info->map, OCELOT_GPIO_INTR, BIT(gpio), BIT(gpio));
	1051	+ regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
	1052	+ BIT(gpio % 32), BIT(gpio % 32));
457	1053	}
458	1054
459	1055	static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
..	..	@@ -497,67 +1093,67 @@
497	1093	struct irq_chip *parent_chip = irq_desc_get_chip(desc);
498	1094	struct gpio_chip *chip = irq_desc_get_handler_data(desc);
499	1095	struct ocelot_pinctrl *info = gpiochip_get_data(chip);
500		- unsigned int reg = 0, irq;
	1096	+ unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride;
	1097	+ unsigned int reg = 0, irq, i;
501	1098	unsigned long irqs;
502	1099
503		- regmap_read(info->map, OCELOT_GPIO_INTR_IDENT, &reg);
504		- if (!reg)
505		- return;
	1100	+ for (i = 0; i < info->stride; i++) {
	1101	+ regmap_read(info->map, id_reg + 4 * i, &reg);
	1102	+ if (!reg)
	1103	+ continue;
506	1104
507		- chained_irq_enter(parent_chip, desc);
	1105	+ chained_irq_enter(parent_chip, desc);
508	1106
509		- irqs = reg;
	1107	+ irqs = reg;
510	1108
511		- for_each_set_bit(irq, &irqs, OCELOT_PINS) {
512		- generic_handle_irq(irq_linear_revmap(chip->irq.domain, irq));
	1109	+ for_each_set_bit(irq, &irqs,
	1110	+ min(32U, info->desc->npins - 32 * i))
	1111	+ generic_handle_irq(irq_linear_revmap(chip->irq.domain,
	1112	+ irq + 32 * i));
	1113	+
	1114	+ chained_irq_exit(parent_chip, desc);
513	1115	}
514		-
515		- chained_irq_exit(parent_chip, desc);
516	1116	}
517	1117
518	1118	static int ocelot_gpiochip_register(struct platform_device *pdev,
519	1119	struct ocelot_pinctrl *info)
520	1120	{
521	1121	struct gpio_chip *gc;
522		- int ret, irq;
	1122	+ struct gpio_irq_chip *girq;
	1123	+ int irq;
523	1124
524	1125	info->gpio_chip = ocelot_gpiolib_chip;
525	1126
526	1127	gc = &info->gpio_chip;
527		- gc->ngpio = OCELOT_PINS;
	1128	+ gc->ngpio = info->desc->npins;
528	1129	gc->parent = &pdev->dev;
529	1130	gc->base = 0;
530	1131	gc->of_node = info->dev->of_node;
531	1132	gc->label = "ocelot-gpio";
532	1133
533		- ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
534		- if (ret)
535		- return ret;
	1134	+ irq = irq_of_parse_and_map(gc->of_node, 0);
	1135	+ if (irq) {
	1136	+ girq = &gc->irq;
	1137	+ girq->chip = &ocelot_irqchip;
	1138	+ girq->parent_handler = ocelot_irq_handler;
	1139	+ girq->num_parents = 1;
	1140	+ girq->parents = devm_kcalloc(&pdev->dev, 1,
	1141	+ sizeof(*girq->parents),
	1142	+ GFP_KERNEL);
	1143	+ if (!girq->parents)
	1144	+ return -ENOMEM;
	1145	+ girq->parents[0] = irq;
	1146	+ girq->default_type = IRQ_TYPE_NONE;
	1147	+ girq->handler = handle_edge_irq;
	1148	+ }
536	1149
537		- irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
538		- if (irq <= 0)
539		- return irq;
540		-
541		- ret = gpiochip_irqchip_add(gc, &ocelot_irqchip, 0, handle_edge_irq,
542		- IRQ_TYPE_NONE);
543		- if (ret)
544		- return ret;
545		-
546		- gpiochip_set_chained_irqchip(gc, &ocelot_irqchip, irq,
547		- ocelot_irq_handler);
548		-
549		- return 0;
	1150	+ return devm_gpiochip_add_data(&pdev->dev, gc, info);
550	1151	}
551	1152
552		-static const struct regmap_config ocelot_pinctrl_regmap_config = {
553		- .reg_bits = 32,
554		- .val_bits = 32,
555		- .reg_stride = 4,
556		- .max_register = 0x64,
557		-};
558		-
559	1153	static const struct of_device_id ocelot_pinctrl_of_match[] = {
560		- { .compatible = "mscc,ocelot-pinctrl" },
	1154	+ { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
	1155	+ { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
	1156	+ { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
561	1157	{},
562	1158	};
563	1159
..	..	@@ -566,11 +1162,19 @@
566	1162	struct device *dev = &pdev->dev;
567	1163	struct ocelot_pinctrl *info;
568	1164	void __iomem *base;
	1165	+ struct resource *res;
569	1166	int ret;
	1167	+ struct regmap_config regmap_config = {
	1168	+ .reg_bits = 32,
	1169	+ .val_bits = 32,
	1170	+ .reg_stride = 4,
	1171	+ };
570	1172
571	1173	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
572	1174	if (!info)
573	1175	return -ENOMEM;
	1176	+
	1177	+ info->desc = (struct pinctrl_desc *)device_get_match_data(dev);
574	1178
575	1179	base = devm_ioremap_resource(dev,
576	1180	platform_get_resource(pdev, IORESOURCE_MEM, 0));
..	..	@@ -579,14 +1183,27 @@
579	1183	return PTR_ERR(base);
580	1184	}
581	1185
582		- info->map = devm_regmap_init_mmio(dev, base,
583		- &ocelot_pinctrl_regmap_config);
	1186	+ info->stride = 1 + (info->desc->npins - 1) / 32;
	1187	+
	1188	+ regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
	1189	+
	1190	+ info->map = devm_regmap_init_mmio(dev, base, &regmap_config);
584	1191	if (IS_ERR(info->map)) {
585	1192	dev_err(dev, "Failed to create regmap\n");
586	1193	return PTR_ERR(info->map);
587	1194	}
588	1195	dev_set_drvdata(dev, info->map);
589	1196	info->dev = dev;
	1197	+
	1198	+ /* Pinconf registers */
	1199	+ if (info->desc->confops) {
	1200	+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	1201	+ base = devm_ioremap_resource(dev, res);
	1202	+ if (IS_ERR(base))
	1203	+ dev_dbg(dev, "Failed to ioremap config registers (no extended pinconf)\n");
	1204	+ else
	1205	+ info->pincfg = base;
	1206	+ }
590	1207
591	1208	ret = ocelot_pinctrl_register(pdev, info);
592	1209	if (ret)
..	..	@@ -596,6 +1213,8 @@
596	1213	if (ret)
597	1214	return ret;
598	1215
	1216	+ dev_info(dev, "driver registered\n");
	1217	+
599	1218	return 0;
600	1219	}
601	1220