write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/phy/marvell/phy-pxa-28nm-hsic.c
..
..
@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 /*
2
3
  * Copyright (C) 2015 Linaro, Ltd.
3
4
  * Rob Herring <robh@kernel.org>
..
..
@@ -5,22 +6,13 @@
5
6
  * Based on vendor driver:
6
7
  * Copyright (C) 2013 Marvell Inc.
7
8
  * Author: Chao Xie <xiechao.mail@gmail.com>
8
- *
9
- * This software is licensed under the terms of the GNU General Public
10
- * License version 2, as published by the Free Software Foundation, and
11
- * may be copied, distributed, and modified under those terms.
12
- *
13
- * This program is distributed in the hope that it will be useful,
14
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
15
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
- * GNU General Public License for more details.
17
- *
18
9
  */
19
10
 
20
11
 #include <linux/delay.h>
21
12
 #include <linux/slab.h>
22
13
 #include <linux/of.h>
23
14
 #include <linux/io.h>
15
+#include <linux/iopoll.h>
24
16
 #include <linux/err.h>
25
17
 #include <linux/clk.h>
26
18
 #include <linux/module.h>
..
..
@@ -53,15 +45,12 @@
53
45
 	struct clk		*clk;
54
46
 };
55
47
 
56
-static bool wait_for_reg(void __iomem *reg, u32 mask, unsigned long timeout)
48
+static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms)
57
49
 {
58
-	timeout += jiffies;
59
-	while (time_is_after_eq_jiffies(timeout)) {
60
-		if ((readl(reg) & mask) == mask)
61
-			return true;
62
-		msleep(1);
63
-	}
64
-	return false;
50
+	u32 val;
51
+
52
+	return readl_poll_timeout(reg, val, ((val & mask) == mask),
53
+				  1000, 1000 * ms);
65
54
 }
66
55
 
67
56
 static int mv_hsic_phy_init(struct phy *phy)
..
..
@@ -69,6 +58,7 @@
69
58
 	struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
70
59
 	struct platform_device *pdev = mv_phy->pdev;
71
60
 	void __iomem *base = mv_phy->base;
61
+	int ret;
72
62
 
73
63
 	clk_prepare_enable(mv_phy->clk);
74
64
 
..
..
@@ -84,14 +74,14 @@
84
74
 		base + PHY_28NM_HSIC_PLL_CTRL2);
85
75
 
86
76
 	/* Make sure PHY PLL is locked */
87
-	if (!wait_for_reg(base + PHY_28NM_HSIC_PLL_CTRL2,
88
-	    PHY_28NM_HSIC_H2S_PLL_LOCK, HZ / 10)) {
77
+	ret = wait_for_reg(base + PHY_28NM_HSIC_PLL_CTRL2,
78
+			   PHY_28NM_HSIC_H2S_PLL_LOCK, 100);
79
+	if (ret) {
89
80
 		dev_err(&pdev->dev, "HSIC PHY PLL not locked after 100mS.");
90
81
 		clk_disable_unprepare(mv_phy->clk);
91
-		return -ETIMEDOUT;
92
82
 	}
93
83
 
94
-	return 0;
84
+	return ret;
95
85
 }
96
86
 
97
87
 static int mv_hsic_phy_power_on(struct phy *phy)
..
..
@@ -100,6 +90,7 @@
100
90
 	struct platform_device *pdev = mv_phy->pdev;
101
91
 	void __iomem *base = mv_phy->base;
102
92
 	u32 reg;
93
+	int ret;
103
94
 
104
95
 	reg = readl(base + PHY_28NM_HSIC_CTRL);
105
96
 	/* Avoid SE0 state when resume for some device will take it as reset */
..
..
@@ -117,20 +108,20 @@
117
108
 	 */
118
109
 
119
110
 	/* Make sure PHY Calibration is ready */
120
-	if (!wait_for_reg(base + PHY_28NM_HSIC_IMPCAL_CAL,
121
-	    PHY_28NM_HSIC_H2S_IMPCAL_DONE, HZ / 10)) {
111
+	ret = wait_for_reg(base + PHY_28NM_HSIC_IMPCAL_CAL,
112
+			   PHY_28NM_HSIC_H2S_IMPCAL_DONE, 100);
113
+	if (ret) {
122
114
 		dev_warn(&pdev->dev, "HSIC PHY READY not set after 100mS.");
123
-		return -ETIMEDOUT;
115
+		return ret;
124
116
 	}
125
117
 
126
118
 	/* Waiting for HSIC connect int*/
127
-	if (!wait_for_reg(base + PHY_28NM_HSIC_INT,
128
-	    PHY_28NM_HSIC_CONNECT_INT, HZ / 5)) {
119
+	ret = wait_for_reg(base + PHY_28NM_HSIC_INT,
120
+			   PHY_28NM_HSIC_CONNECT_INT, 200);
121
+	if (ret)
129
122
 		dev_warn(&pdev->dev, "HSIC wait for connect interrupt timeout.");
130
-		return -ETIMEDOUT;
131
-	}
132
123
 
133
-	return 0;
124
+	return ret;
134
125
 }
135
126
 
136
127
 static int mv_hsic_phy_power_off(struct phy *phy)