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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/drivers/pci/pci.h
....@@ -2,8 +2,11 @@
22 #ifndef DRIVERS_PCI_H
33 #define DRIVERS_PCI_H
44 
5
-#include <linux/android_kabi.h>
65 #include <linux/pci.h>
6
+#include <linux/android_kabi.h>
7
+
8
+/* Number of possible devfns: 0.0 to 1f.7 inclusive */
9
+#define MAX_NR_DEVFNS 256
710 
811 #define PCI_FIND_CAP_TTL	48
912 
....@@ -13,6 +16,7 @@
1316 extern bool pci_early_dump;
1417 
1518 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
19
+bool pcie_cap_has_rtctl(const struct pci_dev *dev);
1620 
1721 /* Functions internal to the PCI core code */
1822 
....@@ -40,8 +44,27 @@
4044 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
4145 int pci_bus_error_reset(struct pci_dev *dev);
4246 
47
+#define PCI_PM_D2_DELAY         200	/* usec; see PCIe r4.0, sec 5.9.1 */
48
+#define PCI_PM_D3HOT_WAIT       10	/* msec */
49
+#define PCI_PM_D3COLD_WAIT      100	/* msec */
50
+
51
+/*
52
+ * Following exit from Conventional Reset, devices must be ready within 1 sec
53
+ * (PCIe r6.0 sec 6.6.1).  A D3cold to D0 transition implies a Conventional
54
+ * Reset (PCIe r6.0 sec 5.8).
55
+ */
56
+#define PCI_RESET_WAIT		1000	/* msec */
57
+/*
58
+ * Devices may extend the 1 sec period through Request Retry Status completions
59
+ * (PCIe r6.0 sec 2.3.1).  The spec does not provide an upper limit, but 60 sec
60
+ * ought to be enough for any device to become responsive.
61
+ */
62
+#define PCIE_RESET_READY_POLL_MS 60000	/* msec */
63
+
4364 /**
4465  * struct pci_platform_pm_ops - Firmware PM callbacks
66
+ *
67
+ * @bridge_d3: Does the bridge allow entering into D3
4568  *
4669  * @is_manageable: returns 'true' if given device is power manageable by the
4770  *		   platform firmware
....@@ -49,6 +72,8 @@
4972  * @set_state: invokes the platform firmware to set the device's power state
5073  *
5174  * @get_state: queries the platform firmware for a device's current power state
75
+ *
76
+ * @refresh_state: asks the platform to refresh the device's power state data
5277  *
5378  * @choose_state: returns PCI power state of given device preferred by the
5479  *		  platform; to be used during system-wide transitions from a
....@@ -64,9 +89,11 @@
6489  * these callbacks are mandatory.
6590  */
6691 struct pci_platform_pm_ops {
92
+	bool (*bridge_d3)(struct pci_dev *dev);
6793 	bool (*is_manageable)(struct pci_dev *dev);
6894 	int (*set_state)(struct pci_dev *dev, pci_power_t state);
6995 	pci_power_t (*get_state)(struct pci_dev *dev);
96
+	void (*refresh_state)(struct pci_dev *dev);
7097 	pci_power_t (*choose_state)(struct pci_dev *dev);
7198 	int (*set_wakeup)(struct pci_dev *dev, bool enable);
7299 	bool (*need_resume)(struct pci_dev *dev);
....@@ -74,13 +101,18 @@
74101 
75102 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
76103 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
77
-void pci_power_up(struct pci_dev *dev);
104
+void pci_refresh_power_state(struct pci_dev *dev);
105
+int pci_power_up(struct pci_dev *dev);
78106 void pci_disable_enabled_device(struct pci_dev *dev);
79107 int pci_finish_runtime_suspend(struct pci_dev *dev);
108
+void pcie_clear_device_status(struct pci_dev *dev);
80109 void pcie_clear_root_pme_status(struct pci_dev *dev);
110
+bool pci_check_pme_status(struct pci_dev *dev);
111
+void pci_pme_wakeup_bus(struct pci_bus *bus);
81112 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
82113 void pci_pme_restore(struct pci_dev *dev);
83
-bool pci_dev_keep_suspended(struct pci_dev *dev);
114
+bool pci_dev_need_resume(struct pci_dev *dev);
115
+void pci_dev_adjust_pme(struct pci_dev *dev);
84116 void pci_dev_complete_resume(struct pci_dev *pci_dev);
85117 void pci_config_pm_runtime_get(struct pci_dev *dev);
86118 void pci_config_pm_runtime_put(struct pci_dev *dev);
....@@ -90,6 +122,8 @@
90122 void pci_free_cap_save_buffers(struct pci_dev *dev);
91123 bool pci_bridge_d3_possible(struct pci_dev *dev);
92124 void pci_bridge_d3_update(struct pci_dev *dev);
125
+int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
126
+				      int timeout);
93127 
94128 static inline void pci_wakeup_event(struct pci_dev *dev)
95129 {
....@@ -111,10 +145,24 @@
111145 	return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
112146 }
113147 
148
+static inline bool pcie_downstream_port(const struct pci_dev *dev)
149
+{
150
+	int type = pci_pcie_type(dev);
151
+
152
+	return type == PCI_EXP_TYPE_ROOT_PORT ||
153
+	       type == PCI_EXP_TYPE_DOWNSTREAM ||
154
+	       type == PCI_EXP_TYPE_PCIE_BRIDGE;
155
+}
156
+
114157 int pci_vpd_init(struct pci_dev *dev);
115158 void pci_vpd_release(struct pci_dev *dev);
116159 void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
117160 void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
161
+
162
+/* PCI Virtual Channel */
163
+int pci_save_vc_state(struct pci_dev *dev);
164
+void pci_restore_vc_state(struct pci_dev *dev);
165
+void pci_allocate_vc_save_buffers(struct pci_dev *dev);
118166 
119167 /* PCI /proc functions */
120168 #ifdef CONFIG_PROC_FS
....@@ -144,7 +192,7 @@
144192 
145193 extern raw_spinlock_t pci_lock;
146194 
147
-extern unsigned int pci_pm_d3_delay;
195
+extern unsigned int pci_pm_d3hot_delay;
148196 
149197 #ifdef CONFIG_PCI_MSI
150198 void pci_no_msi(void);
....@@ -189,6 +237,10 @@
189237 extern const struct device_type pci_dev_type;
190238 extern const struct attribute_group *pci_bus_groups[];
191239 
240
+extern unsigned long pci_hotplug_io_size;
241
+extern unsigned long pci_hotplug_mmio_size;
242
+extern unsigned long pci_hotplug_mmio_pref_size;
243
+extern unsigned long pci_hotplug_bus_size;
192244 
193245 /**
194246  * pci_match_one_device - Tell if a PCI device structure has a matching
....@@ -229,6 +281,9 @@
229281 	pci_bar_mem64,		/* A 64-bit memory BAR */
230282 };
231283 
284
+struct device *pci_get_host_bridge_device(struct pci_dev *dev);
285
+void pci_put_host_bridge_device(struct device *dev);
286
+
232287 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
233288 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
234289 				int crs_timeout);
....@@ -249,28 +304,35 @@
249304 
250305 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
251306 void pci_disable_bridge_window(struct pci_dev *dev);
307
+struct pci_bus *pci_bus_get(struct pci_bus *bus);
308
+void pci_bus_put(struct pci_bus *bus);
252309 
253
-/* PCIe link information */
254
-#define PCIE_SPEED2STR(speed) \
255
-	((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
256
-	 (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
257
-	 (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
258
-	 (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
259
-	 "Unknown speed")
310
+/* PCIe link information from Link Capabilities 2 */
311
+#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
312
+	((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
313
+	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
314
+	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
315
+	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
316
+	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
317
+	 PCI_SPEED_UNKNOWN)
260318 
261319 /* PCIe speed to Mb/s reduced by encoding overhead */
262320 #define PCIE_SPEED2MBS_ENC(speed) \
263
-	((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
321
+	((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
322
+	 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
264323 	 (speed) == PCIE_SPEED_8_0GT  ?  8000*128/130 : \
265324 	 (speed) == PCIE_SPEED_5_0GT  ?  5000*8/10 : \
266325 	 (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
267326 	 0)
268327 
328
+const char *pci_speed_string(enum pci_bus_speed speed);
269329 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
270330 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
271331 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
272332 			   enum pcie_link_width *width);
273333 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
334
+void pcie_report_downtraining(struct pci_dev *dev);
335
+void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
274336 
275337 /* Single Root I/O Virtualization */
276338 struct pci_sriov {
....@@ -303,20 +365,55 @@
303365 	ANDROID_KABI_RESERVE(4);
304366 };
305367 
306
-/* pci_dev priv_flags */
307
-#define PCI_DEV_DISCONNECTED 0
308
-#define PCI_DEV_ADDED 1
368
+/**
369
+ * pci_dev_set_io_state - Set the new error state if possible.
370
+ *
371
+ * @dev - pci device to set new error_state
372
+ * @new - the state we want dev to be in
373
+ *
374
+ * If the device is experiencing perm_failure, it has to remain in that state.
375
+ * Any other transition is allowed.
376
+ *
377
+ * Returns true if state has been changed to the requested state.
378
+ */
379
+static inline bool pci_dev_set_io_state(struct pci_dev *dev,
380
+					pci_channel_state_t new)
381
+{
382
+	pci_channel_state_t old;
383
+
384
+	switch (new) {
385
+	case pci_channel_io_perm_failure:
386
+		xchg(&dev->error_state, pci_channel_io_perm_failure);
387
+		return true;
388
+	case pci_channel_io_frozen:
389
+		old = cmpxchg(&dev->error_state, pci_channel_io_normal,
390
+			      pci_channel_io_frozen);
391
+		return old != pci_channel_io_perm_failure;
392
+	case pci_channel_io_normal:
393
+		old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
394
+			      pci_channel_io_normal);
395
+		return old != pci_channel_io_perm_failure;
396
+	default:
397
+		return false;
398
+	}
399
+}
309400 
310401 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
311402 {
312
-	set_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
403
+	pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
404
+
313405 	return 0;
314406 }
315407 
316408 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
317409 {
318
-	return test_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
410
+	return dev->error_state == pci_channel_io_perm_failure;
319411 }
412
+
413
+/* pci_dev priv_flags */
414
+#define PCI_DEV_ADDED 0
415
+#define PCI_DPC_RECOVERED 1
416
+#define PCI_DPC_RECOVERING 2
320417 
321418 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
322419 {
....@@ -356,13 +453,44 @@
356453 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
357454 #endif	/* CONFIG_PCIEAER */
358455 
456
+#ifdef CONFIG_PCIE_DPC
457
+void pci_save_dpc_state(struct pci_dev *dev);
458
+void pci_restore_dpc_state(struct pci_dev *dev);
459
+void pci_dpc_init(struct pci_dev *pdev);
460
+void dpc_process_error(struct pci_dev *pdev);
461
+pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
462
+bool pci_dpc_recovered(struct pci_dev *pdev);
463
+#else
464
+static inline void pci_save_dpc_state(struct pci_dev *dev) {}
465
+static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
466
+static inline void pci_dpc_init(struct pci_dev *pdev) {}
467
+static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
468
+#endif
469
+
359470 #ifdef CONFIG_PCI_ATS
471
+/* Address Translation Service */
472
+void pci_ats_init(struct pci_dev *dev);
360473 void pci_restore_ats_state(struct pci_dev *dev);
361474 #else
362
-static inline void pci_restore_ats_state(struct pci_dev *dev)
363
-{
364
-}
475
+static inline void pci_ats_init(struct pci_dev *d) { }
476
+static inline void pci_restore_ats_state(struct pci_dev *dev) { }
365477 #endif /* CONFIG_PCI_ATS */
478
+
479
+#ifdef CONFIG_PCI_PRI
480
+void pci_pri_init(struct pci_dev *dev);
481
+void pci_restore_pri_state(struct pci_dev *pdev);
482
+#else
483
+static inline void pci_pri_init(struct pci_dev *dev) { }
484
+static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
485
+#endif
486
+
487
+#ifdef CONFIG_PCI_PASID
488
+void pci_pasid_init(struct pci_dev *dev);
489
+void pci_restore_pasid_state(struct pci_dev *pdev);
490
+#else
491
+static inline void pci_pasid_init(struct pci_dev *dev) { }
492
+static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
493
+#endif
366494 
367495 #ifdef CONFIG_PCI_IOV
368496 int pci_iov_init(struct pci_dev *dev);
....@@ -372,7 +500,7 @@
372500 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
373501 void pci_restore_iov_state(struct pci_dev *dev);
374502 int pci_iov_bus_range(struct pci_bus *bus);
375
-
503
+extern const struct attribute_group sriov_dev_attr_group;
376504 #else
377505 static inline int pci_iov_init(struct pci_dev *dev)
378506 {
....@@ -411,7 +539,7 @@
411539 	return resource_alignment(res);
412540 }
413541 
414
-void pci_enable_acs(struct pci_dev *dev);
542
+void pci_acs_init(struct pci_dev *dev);
415543 #ifdef CONFIG_PCI_QUIRKS
416544 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
417545 int pci_dev_specific_enable_acs(struct pci_dev *dev);
....@@ -433,8 +561,9 @@
433561 #endif
434562 
435563 /* PCI error reporting and recovery */
436
-void pcie_do_fatal_recovery(struct pci_dev *dev, u32 service);
437
-void pcie_do_nonfatal_recovery(struct pci_dev *dev);
564
+pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
565
+		pci_channel_state_t state,
566
+		pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
438567 
439568 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
440569 #ifdef CONFIG_PCIEASPM
....@@ -449,12 +578,12 @@
449578 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
450579 #endif
451580 
452
-#ifdef CONFIG_PCIEASPM_DEBUG
453
-void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
454
-void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
581
+#ifdef CONFIG_PCIE_ECRC
582
+void pcie_set_ecrc_checking(struct pci_dev *dev);
583
+void pcie_ecrc_get_policy(char *str);
455584 #else
456
-static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
457
-static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
585
+static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
586
+static inline void pcie_ecrc_get_policy(char *str) { }
458587 #endif
459588 
460589 #ifdef CONFIG_PCIE_PTM
....@@ -503,6 +632,12 @@
503632 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
504633 int of_get_pci_domain_nr(struct device_node *node);
505634 int of_pci_get_max_link_speed(struct device_node *node);
635
+void pci_set_of_node(struct pci_dev *dev);
636
+void pci_release_of_node(struct pci_dev *dev);
637
+void pci_set_bus_of_node(struct pci_bus *bus);
638
+void pci_release_bus_of_node(struct pci_bus *bus);
639
+
640
+int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
506641 
507642 #else
508643 static inline int
....@@ -522,20 +657,18 @@
522657 {
523658 	return -EINVAL;
524659 }
525
-#endif /* CONFIG_OF */
526660 
527
-#if defined(CONFIG_OF_ADDRESS)
528
-int devm_of_pci_get_host_bridge_resources(struct device *dev,
529
-			unsigned char busno, unsigned char bus_max,
530
-			struct list_head *resources, resource_size_t *io_base);
531
-#else
532
-static inline int devm_of_pci_get_host_bridge_resources(struct device *dev,
533
-			unsigned char busno, unsigned char bus_max,
534
-			struct list_head *resources, resource_size_t *io_base)
661
+static inline void pci_set_of_node(struct pci_dev *dev) { }
662
+static inline void pci_release_of_node(struct pci_dev *dev) { }
663
+static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
664
+static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
665
+
666
+static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
535667 {
536
-	return -EINVAL;
668
+	return 0;
537669 }
538
-#endif
670
+
671
+#endif /* CONFIG_OF */
539672 
540673 #ifdef CONFIG_PCIEAER
541674 void pci_no_aer(void);
....@@ -543,13 +676,28 @@
543676 void pci_aer_exit(struct pci_dev *dev);
544677 extern const struct attribute_group aer_stats_attr_group;
545678 void pci_aer_clear_fatal_status(struct pci_dev *dev);
546
-void pci_aer_clear_device_status(struct pci_dev *dev);
679
+int pci_aer_clear_status(struct pci_dev *dev);
680
+int pci_aer_raw_clear_status(struct pci_dev *dev);
547681 #else
548682 static inline void pci_no_aer(void) { }
549683 static inline void pci_aer_init(struct pci_dev *d) { }
550684 static inline void pci_aer_exit(struct pci_dev *d) { }
551685 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
552
-static inline void pci_aer_clear_device_status(struct pci_dev *dev) { }
686
+static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
687
+static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
688
+#endif
689
+
690
+#ifdef CONFIG_ACPI
691
+int pci_acpi_program_hp_params(struct pci_dev *dev);
692
+#else
693
+static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
694
+{
695
+	return -ENODEV;
696
+}
697
+#endif
698
+
699
+#ifdef CONFIG_PCIEASPM
700
+extern const struct attribute_group aspm_ctrl_attr_group;
553701 #endif
554702 
555703 #endif /* DRIVERS_PCI_H */